CN113708766A - Configurable accurate delay circuit structure for high-speed ADC - Google Patents

Abstract

The invention discloses a configurable accurate time delay circuit structure for a high-speed ADC (analog to digital converter), which belongs to the field of electronic circuits and comprises a PMOS (P-channel metal oxide semiconductor) transistor P₁NMOS transistor N₁And a capacitor C_LPMOS tube P₁Gate terminal of and NMOS transistor N₁Are commonly connected to an input voltage V_inPMOS tube P₁Drain terminal and NMOS transistor N₁The drain terminals of the first and second transistors are commonly connected to an output voltage V_outCapacitor C_LOne end of which is connected with an output voltage V_outThe other end is grounded; also includes a resistor R₁And a resistance R₂And a plurality of capacitors, the resistor R₁Is connected in series with the PMOS tube P₁The drain terminal of, the resistance R₂Is connected in series with the NMOS tube N₁The drain terminal of (1); a plurality of capacitors connected in parallel to the capacitor C_LAnd an output voltage V_outIs connected in parallel to the capacitor C_LAnd an output voltage V_outEach capacitor between the two capacitors is respectively connected with a switching tube in series; the switch tube is an NMOS tube, and the drain ends of the switch tube are respectively connected with corresponding capacitorsAnd the source ends are all grounded.

Description

Configurable accurate delay circuit structure for high-speed ADC

Technical Field

The invention relates to the technical field of electronic circuits, in particular to a configurable accurate delay circuit structure for a high-speed ADC (analog to digital converter).

Background

An ADC (analog-to-digital converter) is a circuit that converts an analog signal into a digital signal, and is widely used in the fields of military, communication, industry, aerospace, precision instruments, and the like. With increasing demands on the performance of the instrument, high-speed ADCs (conversion times typically less than 1 μ s) are becoming an important branch in analog-to-digital converters.

In designing an ADC, a delay circuit is a commonly used circuit structure, which can delay signals in time sequence, especially for synchronization of clock signals and the like. The most common circuit for time delay is a CMOS inverter delay circuit, which has a structure as shown in FIG. 1 and is used when an input voltage V is applied_inWhen the voltage is equal to 0V, the PMOS tube is conducted and the NMOS tube is cut off, and the internal resistance R of the PMOS tube is_pAnd a capacitor C_LTogether determine the RC delay τ:

τ＝R_p·C_L

if the propagation delay means: at "V_inChange to 50% V_DDTo V_outChange to 50% V_DD"time between the two", the propagation delay t can be obtained_pThe calculation formula of (2) is as follows:

t_p＝ln2·τ＝0.69R_pC_L

when V is_in＝V_DDWhen the NMOS transistor is turned on, the PMOS transistor is turned off, and the propagation delay t can be obtained_nIs (R)_nRepresenting the internal resistance of the NMOS tube):

t_n＝0.69R_nC_L

the total propagation delay t of the whole CMOS inverter delay circuit is as follows:

however, R_pAnd R_nNot constant but a non-linear function of the voltage across the transistor, and due to process level limitations, R_pAnd R_nThe delay circuit cannot be accurately controlled, so that when the delay circuit is designed according to the traditional delay circuit, the error between the delay time obtained by the actual circuit and the original design purpose is very large, and the effect of accurate delay cannot be achieved; furthermore, many delay circuits require delay time configurable functionality, i.e. different delay times are used in different situationsTo meet various requirements, which this circuit does not have.

Disclosure of Invention

The invention aims to provide a configurable accurate delay circuit structure for a high-speed ADC (analog to digital converter), which aims to solve the problems that a large error exists between actual delay obtained by a traditional delay circuit and initial design delay, and delay time cannot be configured.

In order to solve the above technical problems, the present invention provides a configurable precise delay circuit structure for high-speed ADC, comprising a PMOS transistor P₁NMOS transistor N₁And a capacitor C_LPMOS tube P₁Gate terminal of and NMOS transistor N₁Are commonly connected to an input voltage V_inPMOS tube P₁Drain terminal and NMOS transistor N₁The drain terminals of the first and second transistors are commonly connected to an output voltage V_outCapacitor C_LOne end of which is connected with an output voltage V_outThe other end is grounded;

the configurable precise delay circuit structure further comprises:

resistance R₁And a resistance R₂Said resistance R₁Is connected in series with the PMOS tube P₁The drain terminal of, the resistance R₂Is connected in series with the NMOS tube N₁The drain terminal of (1);

a plurality of capacitors connected in parallel to the capacitor C_LAnd an output voltage V_outIn the meantime.

Optionally, connected in parallel to the capacitor C_LAnd an output voltage V_outAnd each capacitor between the two capacitors is respectively connected with a switching tube in series.

Optionally, the switch tube is an NMOS tube, the drain terminals of the switch tube are respectively connected to the corresponding capacitors, and the source terminals of the switch tube are all grounded.

Optionally, the resistor R₁Is a PMOS tube P₁Internal resistance R_pAbove 3 orders of magnitude, the resistance R₂Is an NMOS tube N₁Internal resistance R_nAbove 3 orders of magnitude.

Optionally, the PMOS tube P₁Source terminal of the transformer is connected with a voltage V_DDThe NMOS tube N₁The source terminal of which is grounded.

The invention also provides a delay chain circuit formed by serially connecting the configurable precise delay circuit structures for the high-speed ADC.

In the configurable precise time delay circuit structure for the high-speed ADC, the PMOS pipe P is included₁NMOS transistor N₁And a capacitor C_LPMOS tube P₁Gate terminal of and NMOS transistor N₁Are commonly connected to an input voltage V_inPMOS tube P₁Drain terminal and NMOS transistor N₁The drain terminals of the first and second transistors are commonly connected to an output voltage V_outCapacitor C_LOne end of which is connected with an output voltage V_outThe other end is grounded; also includes a resistor R₁And a resistance R₂And a plurality of capacitors, the resistor R₁Is connected in series with the PMOS tube P₁The drain terminal of, the resistance R₂Is connected in series with the NMOS tube N₁The drain terminal of (1); a plurality of capacitors connected in parallel to the capacitor C_LAnd an output voltage V_outIn the meantime.

The invention has the following beneficial effects:

(1) the drain end of the PMOS tube and the drain end of the NMOS tube are respectively connected with a high-precision resistor in series, and the resistance value of the high-precision resistor is greater than that of the on-resistance of the MOS tube, so that the influence of the internal resistance of the MOS tube on time delay is avoided;

(2) a load capacitor is added at the output end, so that the effect of accurately controlling the delay time is achieved; the load capacitor is selected by taking the NMOS tube as a switch to adjust the size of the total load capacitance value, so that the delay time is changed and controlled;

(3) the size of the load capacitance value of the output end can be adjusted, and a delay step length adjusting circuit is realized;

(4) the configurable precise delay circuit structure can be connected in series in multiple stages, and a circuit with longer delay is realized.

Drawings

FIG. 1 is a schematic diagram of a conventional delay circuit of a CMOS inverter;

FIG. 2 is a schematic diagram of a configurable precision delay circuit for a high-speed ADC according to the present invention;

fig. 3 is a schematic diagram of a delay chain circuit structure formed by serially connecting configurable precise delay circuit structures for a high-speed ADC.

Detailed Description

The following describes a configurable precise delay circuit structure for a high-speed ADC according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Example one

The invention provides a configurable precise time delay circuit structure for a high-speed ADC (analog to digital converter), which is shown in figure 2 and comprises a PMOS (P-channel metal oxide semiconductor) tube P₁NMOS transistor N₁And a capacitor C_LPMOS tube P₁Gate terminal of and NMOS transistor N₁Are commonly connected to an input voltage V_inPMOS tube P₁Drain terminal and NMOS transistor N₁The drain terminals of the first and second transistors are commonly connected to an output voltage V_outCapacitor C_LOne end of which is connected with an output voltage V_outThe other end is grounded;

with continued reference to FIG. 2, the configurable precise delay circuit structure further includes a resistor R₁And a resistance R₂And a plurality of capacitors C₁～C_nAnd n is an integer of not less than 1. The resistor R₁Is connected in series with the PMOS tube P₁The drain terminal of, the resistance R₂Is connected in series with the NMOS tube N₁The drain terminal of (1); a plurality of capacitors C₁～C_nIs connected in parallel with the capacitor C_LAnd an output voltage V_outBetween, capacitance C₁～C_nRespectively connected with an NMOS tube MN serving as a switching tube in series₁～MN_nSpecifically, a capacitor C₁Upper series NMOS transistor MN₁Capacitor C₂Upper series NMOS transistor MN₂,.., capacitance C_nUpper series NMOS transistor MN_n. NMOS tube MN₁～MN_nRespectively with corresponding capacitors C₁～C_nAnd the source ends are grounded.

Considering first only the capacitor C₁The case of a branch. When the input voltage isV_inWhen equal to 0V, PMOS tube P₁Conducting NMOS tube N₁Cut-off, RC delay τ and propagation delay t at this time_pRespectively as follows:

τ＝(R_p+R₁)·(C_L+C₁)

t_p＝ln2·τ＝0.69(R_p+R₁)(C_L+C₁)

R_pis a PMOS tube P₁Internal resistance of (d); when R is₁＞＞R_pSaid resistance R₁At least a PMOS tube P₁Internal resistance R_p3 orders of magnitude, the above formula is approximated as: t is t_p＝0.69R₁(C_L+C₁)

In the same way, R_nIs an NMOS tube N₁When V is an internal resistance of_in＝V_DDAnd R is₂＞＞R_nSaid resistance R₂At least an NMOS transistor N₁Internal resistance R_nOf 3 orders of magnitude, there are: t is t_n＝0.69R₂(C_L+C₁)

The total propagation delay t of the whole delay circuit is:

in sum, the delay circuit avoids the PMOS tube P₁And NMOS tube N₁The influence of the internal resistance on the time delay, and only the resistance R needs to be controlled well in design and processing₁、R₂And a capacitor C_L、C₁The delay time can be accurately controlled.

If n different capacitance branches are added, the circuit can generate time delay of a plurality of gears, and the delay time can be configured only by changing the on-off of the NMOS tube of the capacitance branch. Based on this characteristic, the circuit configuration can be used for a variety of applications, as follows.

Firstly, a plurality of delay circuits with different effects can be designed by utilizing the circuit. For example, let C₁＝C₂＝C₃＝…＝C_nIf C, then one capacitor branch is conducted every moreThe total propagation delay of the circuit is increased by a fixed value:

thereby obtaining an equal-difference delay incremental circuit; or order C₁、C₂、C₃、…、C_nDifferent values are taken, different NMOS tubes are conducted according to requirements, and 1+2 can be obtained in totalⁿDifferent delay schemes are adopted; meanwhile, by conducting more NMOS tubes, the total range of delay time can be increased, and the design requirement is met.

Secondly, a delay step length adjusting circuit can be designed by utilizing the delay circuit. Order to

Then turn on C in sequence₁、C₂、C₃、…、C_nThe delay step size can be increased bit by bit when the branch is located.

Finally, a delay chain circuit can be designed by utilizing the delay circuit. As shown in FIG. 3, a plurality of the configurable precise delay circuit structures are connected in series end to end, if the propagation delay t of the xth stage delay circuit is t_xComprises the following steps:

then V_outSignal to V_inThe total propagation delay t of the signal is: t is t₁+t₂+t₃+…+t_n. The delay chain circuit can realize a wider range of delay effect.

It is noted that the load capacitance C_LThe gate mainly comprises three parts, namely an internal diffusion capacitor of the gate, an interconnection line capacitor and a fan-out capacitor, and needs to be comprehensively considered during design.

The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.

Claims (6)

1. A configurable accurate delay circuit structure for high-speed ADC comprises a PMOS tube P₁NMOS transistor N₁And a capacitor C_LPMOS tube P₁Gate terminal of and NMOS transistor N₁Are commonly connected to an input voltage V_inPMOS tube P₁Drain terminal and NMOS transistor N₁The drain terminals of the first and second transistors are commonly connected to an output voltage V_outCapacitor C_LOne end of which is connected with an output voltage V_outThe other end is grounded;

the configurable precise time delay circuit structure is characterized by further comprising:

resistance R₁And a resistance R₂Said resistance R₁Is connected in series with the PMOS tube P₁The drain terminal of, the resistance R₂Is connected in series with the NMOS tube N₁The drain terminal of (1);

a plurality of capacitors connected in parallel to the capacitor C_LAnd an output voltage V_outIn the meantime.

2. The configurable precision delay circuit architecture for a high-speed ADC of claim 1 wherein said capacitor C is connected in parallel_LAnd an output voltage V_outAnd each capacitor between the two capacitors is respectively connected with a switching tube in series.

3. The configurable precise delay circuit structure of claim 2, wherein the switch transistors are NMOS transistors, the drain terminals of the NMOS transistors are connected to the corresponding capacitors, and the source terminals of the NMOS transistors are grounded.

4. The configurable precision delay circuit structure for a high speed ADC of claim 1 wherein said resistor R₁Is a PMOS tube P₁Internal resistance R_pAbove 3 orders of magnitude, the resistance R₂Is an NMOS tube N₁Internal resistance R_nAbove 3 orders of magnitude.

5. Such as rightThe configurable precision delay circuit structure for a high-speed ADC of claim 1, wherein said PMOS pipe P₁Source terminal of the transformer is connected with a voltage V_DDThe NMOS tube N₁The source terminal of which is grounded.

6. A delay chain circuit formed by connecting configurable precise delay circuit structures for a high-speed ADC according to any one of claims 1-5 in series.

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