CN221042821U - Grid voltage bootstrap switch circuit, analog-digital converter and electronic equipment - Google Patents
Grid voltage bootstrap switch circuit, analog-digital converter and electronic equipment Download PDFInfo
- Publication number
- CN221042821U CN221042821U CN202323089886.5U CN202323089886U CN221042821U CN 221042821 U CN221042821 U CN 221042821U CN 202323089886 U CN202323089886 U CN 202323089886U CN 221042821 U CN221042821 U CN 221042821U
- Authority
- CN
- China
- Prior art keywords
- node
- electrode
- gate
- clock signal
- switching tube
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims abstract description 20
- 230000005540 biological transmission Effects 0.000 claims description 63
- 239000003990 capacitor Substances 0.000 claims description 18
- 230000000694 effects Effects 0.000 abstract description 13
- 238000005070 sampling Methods 0.000 description 14
- 230000008859 change Effects 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000003252 repetitive effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Abstract
The utility model discloses a grid voltage bootstrapping switch circuit, an analog-digital converter and electronic equipment, which belong to the technical field of integrated circuits. The on-resistance of the sixth switching tube is set through the boost module, so that the on-resistance is not influenced by an analog input signal, the third switching tube and the fifth switching tube are set, the analog input signal is connected with the substrate end of the sixth switching tube, and the influence of the lining bias effect on the on-resistance is eliminated.
Description
Technical Field
The present utility model relates to the field of integrated circuits, and in particular, to a gate voltage bootstrap switch circuit, an analog-to-digital converter, and an electronic device.
Background
Analog-to-digital converters (ADCs) are widely used in various fields, and a sample-and-hold module is one of the key modules of an ADC, which is a key component determining the input bandwidth and sampling frequency of the ADC, and a key determining the sampling accuracy of the ADC is a sampling switch.
The precision of the sampling switch directly influences the effective digit and linearity of the ADC, the conventional sampling switch is realized by adopting an NMOS tube or a CMOS transmission gate, but the on-resistance of the conventional sampling switch is nonlinear, the resistance value of the on-resistance can change along with the change of an input signal, and the problems of lining bias effect and the like exist, so that the conventional sampling switch cannot meet the application requirements of the ADC on high precision.
It should be noted that the information disclosed in this background section is only for enhancement of understanding of the general background of the utility model and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of utility model
The utility model aims to provide a grid voltage bootstrap switch circuit, an analog-digital converter and electronic equipment, so as to solve the problem that a conventional sampling switch cannot meet the application requirement of ADC (analog-to-digital converter) with high precision.
In order to solve the above technical problems, the present utility model provides a gate voltage bootstrap switch circuit, including:
a first clock signal and a second clock signal, the logic voltages of the first clock signal and the second clock signal being opposite;
The first control signal input ends of the first transmission gate and the third transmission gate are connected with the first clock signal, and the second control signal input ends of the first transmission gate and the third transmission gate are connected with the second clock signal;
The signal input ends of the first transmission gate and the third transmission gate are connected with analog input signals and are also commonly connected to the second electrode of the sixth switching tube, the grid electrode of the sixth switching tube is connected with a fifth node, the substrate end of the sixth switching tube is connected with a fourth node, and the first electrode of the sixth switching tube is connected with analog output signals;
The signal output end of the first transmission gate is connected with a first node, the first node is also connected with a boosting module, the boosting module is connected with a second node so that a pressure difference exists between the second node and the first node, and the second node is connected with a fifth node;
The signal output end of the third transmission gate is connected with the fourth node, the fourth node is connected with the first electrode of the fifth switching tube, the grid electrode of the fifth switching tube is connected with the second clock signal, and the second electrode of the fifth switching tube is grounded.
Preferably, the boost module comprises a first capacitor and a first diode, the first node is connected with a first pole of the first capacitor, a second pole of the first capacitor is connected with a second node, the second node is also connected with a cathode of the first diode, and an anode of the first diode is connected with a power supply voltage.
Preferably, the circuit further comprises a first switch tube, the first node is connected with a first electrode of the first switch tube, a grid electrode of the first switch tube is connected with the second clock signal, and a second electrode of the first switch tube is grounded.
Preferably, the circuit further comprises a second transmission gate, wherein a first control signal input end of the second transmission gate is connected with the first clock signal, a second control signal input end of the second transmission gate is connected with the second clock signal, a signal input end of the second transmission gate is connected with the analog input signal and is also commonly connected to a second electrode of the sixth switching tube, a signal output end of the second transmission gate is connected with a third node, the third node is also connected with a gate electrode of a fifth transistor, a first electrode of the fifth transistor is connected with the second node, and a second electrode of the fifth transistor is connected with the fifth node.
Preferably, the first clock signal is further connected to a gate of a first transistor, a second electrode of the first transistor is connected to the third node, and a first electrode of the first transistor is connected to a power supply voltage.
Preferably, the circuit further comprises a seventh switching tube and an eighth switching tube, the fifth node is connected with a second electrode of the seventh switching tube, a grid electrode of the seventh switching tube is connected with a power supply voltage, the second electrode of the seventh switching tube is connected with a second electrode of the eighth switching tube, and a grid electrode of the eighth switching tube is connected with the second clock signal.
Preferably, the first clock signal is obtained by an inverter.
Preferably, the first, second and third transmission gates have the same structure.
An analog-to-digital converter comprises the gate voltage bootstrap switch circuit.
An electronic device comprises the gate voltage bootstrap switch circuit.
In the gate voltage bootstrapping switch circuit provided by the utility model, a constant voltage difference is provided between the grid electrode and the second electrode of the sixth switch tube between the analog input signal and the analog output signal through the boost module, so that the on-resistance of the sixth switch tube is not influenced by the analog input signal, the third transmission gate and the fifth switch tube are arranged, the voltage of the substrate end of the sixth switch tube N6 and the voltage of the source electrode (the second electrode) are equal in the on state, and the influence of the lining bias effect on the on-resistance is eliminated.
The analog-digital converter and the electronic equipment provided by the utility model belong to the same conception, so that the analog-digital converter and the electronic equipment provided by the utility model have at least all advantages of the gate voltage bootstrap switch circuit provided by the utility model and are not repeated here. The first control signal input ends of the first transmission gate and the third transmission gate are connected with a first clock signal, and the second control signal input ends of the first transmission gate and the third transmission gate are connected with a second clock signal; the signal input ends of the first transmission gate and the third transmission gate are connected with analog input signals and are also connected to the second electrode of the sixth switching tube, the grid electrode of the sixth switching tube is connected with the fifth node, the substrate end of the sixth switching tube is connected with the fourth node, and the first electrode of the sixth switching tube is connected with analog output signals; the signal output end of the first transmission gate is connected with a first node, the first node is also connected with a boosting module, the boosting module is connected with a second node, so that a pressure difference exists between the second node and the first node, and the second node is connected with a fifth node; the signal output end of the third transmission gate is connected with a fourth node, the fourth node is connected with the first electrode of the fifth switching tube, the grid electrode of the fifth switching tube is connected with the second clock signal, and the second electrode of the fifth switching tube is grounded. Furthermore, a constant voltage difference is provided between the grid electrode and the second electrode of the sixth switching tube between the analog input signal and the analog output signal through the boosting module, so that the on-resistance of the sixth switching tube is not influenced by the analog input signal, the third transmission gate and the fifth switching tube are arranged, the voltage of the substrate end of the sixth switching tube N6 and the voltage of the source electrode (the second electrode) are equal in the on state, and the influence of the lining bias effect on the on-resistance is eliminated.
Drawings
Fig. 1 is a circuit diagram of a gate voltage bootstrapped switch according to an embodiment of the present utility model.
Detailed Description
The gate voltage bootstrap switch circuit, the analog-to-digital converter and the electronic device provided by the utility model are further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present utility model will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model. It should be understood that the drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the utility model. Specific design features of the utility model disclosed herein, including for example, specific dimensions, orientations, positions, and configurations, will be determined in part by the specific intended application and use environment. In the embodiments described below, the same reference numerals are used in common between the drawings to denote the same parts or parts having the same functions, and the repetitive description thereof may be omitted. In this specification, like reference numerals and letters are used to designate like items, and thus once an item is defined in one drawing, no further discussion thereof is necessary in subsequent drawings.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
The inventor researches have found that the on-resistance of the conventional sampling switch varies with the transformation of the input signal, and that there is also a lining bias effect.
Based on the above, the utility model has the core concept that the on-resistance of the sixth switching tube is set by setting the boost module so as not to be influenced by the analog input signal, and the third switching tube and the fifth switching tube are set so as to connect the analog input signal with the substrate end of the sixth switching tube, thereby eliminating the influence of the lining bias effect on the on-resistance.
Specifically, please refer to fig. 1, which is a schematic diagram of an embodiment of the present utility model. As shown in fig. 1, a gate voltage bootstrapped switch circuit includes:
A first clock signal CLK and a second clock signal CLKN having opposite logic voltages;
The first control signal input ends of the first transmission gate and the third transmission gate are connected with the first clock signal CLK, and the second control signal input ends of the first transmission gate and the third transmission gate are connected with the second clock signal CLKN;
The signal Input ends of the first transmission gate and the third transmission gate are connected with an analog Input signal Input and are also commonly connected to a second electrode of the sixth switching tube N6, a grid electrode of the sixth switching tube N6 is connected with a fifth node Net5, a substrate end of the sixth switching tube N6 is connected with a fourth node Net4, and a first electrode of the sixth switching tube N6 is connected with an analog Output signal Output;
The signal output end of the first transmission gate is connected with a first node Net1, the first node Net1 is also connected with a boosting module, the boosting module is connected with a second node Net2, so that a pressure difference exists between the second node Net2 and the first node Net1, and the second node Net2 is connected with a fifth node Net 5;
The signal output end of the third transmission gate is connected with the fourth node Net4, the fourth node Net4 is connected with the first electrode of the fifth switching tube N5, the gate of the fifth switching tube N5 is connected with the second clock signal CLKN, and the second electrode of the fifth switching tube N5 is grounded.
Through setting up the boost module, boost to the analog Input signal Input of Input to signal transmission to the grid of sixth switching tube N6 after the boost, still set up the third transmission gate and transmit analog Input signal Input to the substrate end of sixth switching tube N6, the voltage of substrate end and source (second electrode) of sixth switching tube N6 equals under the on-state, eliminates the influence of lining offset effect to on-resistance.
The transistors used in all embodiments of the present application may be thin film transistors or field effect transistors or other devices of the same characteristics, and according to the role in the circuit, the transistors used in the embodiments of the present application are mainly CMOS transistors (Complementary Metal Oxide Semiconductor, complementary metal oxide semiconductors). Since the source and drain of the COMS tube are symmetrical, the source and drain can be interchanged. In the embodiment of the present application, in order to distinguish the other two stages of transistors except the gate, the input end of the transistor may be referred to as a first electrode, the output end of the transistor may be referred to as a second electrode, and the middle end may be the gate. In addition, the first switching tube N1, the second switching tube N2, the third switching tube N3, the fourth switching tube N4, the fifth switching tube N5, the sixth switching tube N6, the seventh switching tube N7 and the eighth switching tube N8 are all N-type MOS tubes, the first electrode of the N-type MOS tube is a drain electrode, and the second electrode is a source electrode; the first transistor P1, the second transistor P2, the third transistor P3, the fourth transistor P4 and the fifth transistor P5 are P-type MOS transistors, the first electrode of the P-type MOS transistor is a source electrode, and the second electrode is a drain electrode.
The second electrode (source) of the fifth switching tube N5 is connected to the substrate terminal (or base) and is commonly grounded Gnd, the gate is connected to the second clock signal CLKN, the first electrode (drain) is connected to the fourth node Net4, and to the third transfer gate and the substrate terminal of the sixth switching tube N6.
In one embodiment, the boost module includes a first capacitor C1 and a first diode D1, the first node Net1 is connected to a first pole of the first capacitor C1, a second pole of the first capacitor C1 is connected to a second node Net2, the second node Net2 is further connected to a cathode of the first diode D1, and an anode of the first diode D1 is connected to a power supply voltage VDD.
The first capacitor C1, the first diode D1 and the power supply voltage VDD are set, the first capacitor C1 is charged through the power supply voltage VDD and the first diode D1, and a voltage value higher than the analog Input signal Input by a constant value is output from the second node Net2 when the sampling switch (the sixth switching tube N6) is turned on.
Specifically, the circuit further comprises a first switching tube N1, the first node Net1 is connected with a first electrode of the first switching tube N1, a gate of the first switching tube N1 is connected with the second clock signal CLKN, and a second electrode of the first switching tube N1 is grounded.
It can be appreciated that the substrate end of the first switching transistor N1 and the second electrode (source) are commonly grounded Gnd, and the first switching transistor N1 is controlled to be turned on by the second clock signal CLKN.
Specifically, the circuit further comprises a second transmission gate, wherein a first control signal input end of the second transmission gate is connected with the first clock signal CLK, a second control signal input end of the second transmission gate is connected with the second clock signal CLKN, a signal input end of the second transmission gate is connected with the analog input signal and is also commonly connected to a second electrode of the sixth switching tube N6, a signal output end of the second transmission gate is connected with a third node Net3, the third node Net3 is also connected with a gate of a fifth transistor P5, a first electrode of the fifth transistor P5 is connected with the second node Net2, and a second electrode of the fifth transistor P5 is connected with the fifth node Net 5.
The second transmission gate is also connected to control conduction through the first clock signal CLK and the second clock signal CLKN, outputs an analog Input signal Input to the third node Net3, and also controls conduction between the second node Net2 and the fifth node Net5 through the fifth transistor P5.
Specifically, the first clock signal CLK is further connected to the gate of the first transistor P1, the second electrode of the first transistor P1 is connected to the third node Net3, and the first electrode of the first transistor P1 is connected to the power supply voltage VDD.
Specifically, the circuit further comprises a seventh switching tube N7 and an eighth switching tube N8, the fifth node Net5 is connected with the second electrode of the seventh switching tube N7, the gate electrode of the seventh switching tube N7 is connected with the power supply voltage, the second electrode of the seventh switching tube N7 is connected with the second electrode of the eighth switching tube N8, and the gate electrode of the eighth switching tube N8 is connected with the second clock signal CLKN.
In one embodiment, the first clock signal CLK is derived from the second clock signal CLKN through an inverter INV.
The first clock signal CLK is a clock for sampling the switch, and when the logic voltage of the first clock signal CLK is 0, the logic voltage of the second clock signal CLKN is 1.
In one embodiment, clkn=1 when clk=0. The first switching tube N1 is turned on, the first transmission gate formed by the second switching tube N2 and the second transistor P2 is turned off, and the first node Net1 (the left polar plate or the cathode of the first capacitor C1) is grounded Gnd through the first switching tube N1; the second pass gate switch consisting of the third switching transistor N3 and the third transistor P3 is turned off, the first transistor P1 is turned on, the third node Net3 is pulled to the supply voltage VDD, so the fifth transistor P5 is also turned off, and since the diode D1 is connected between the supply voltage VDD and the second node Net2, the second node Net2 node (the right plate or anode of the capacitor C1) is charged to VDD-0.7V (assuming that the forward conduction voltage drop of the first diode D1 is 0.7V). The fifth switching transistor N5 is turned on, the third transmission gate formed by the fourth transistor P4 and the fourth switching transistor N4 is turned off, the fourth node Net4 is pulled to Gnd through the fifth switching transistor N5, the eighth switching transistor N8 is turned on, and the fifth node Net5 is pulled to Gnd, so the sixth switching transistor N6 is turned off. In summary, in this state, the left plate (cathode) of the first capacitor C1 is charged to 0, the right plate (anode) is charged to VDD-0.7V, and the sampling switch sixth switching tube N6 is in an off state.
In one embodiment, clkn=0 when clk=1. The eighth switching transistor N8 is turned off, so that no matter whether the fifth transistor P5 is turned on or not, the charge on the first capacitor C1 is not discharged through the fifth transistor P5, and therefore the voltage drop between the two plates of the first capacitor C1 is maintained unchanged. The first switch tube N1 is disconnected, the first transmission gate formed by the second switch tube N2 and the second transistor P2 is conducted, the first node Net1 (the left polar plate or anode of the first capacitor C1) is changed into an analog Input signal Input from the original Gnd, so that the voltage of the second node Net2 of the right polar plate of the first capacitor C1, namely the anode, is also increased from the original VDD-0.7V to VDD-0.7V+input, and meanwhile, the first diode D1 is cut off. The first transistor P1 is turned off, the second transmission gate switch composed of the third switching transistor N3 and the third transistor P3 is turned on, the gate of the fifth transistor P5 is connected to the Input, and the voltage at the source (first electrode) and the substrate of the fifth transistor P5 is VDD-0.7+input due to the fact that the source (first electrode) and the substrate of the fifth transistor P5 are connected to the second node Net2, so that the voltage of the fifth transistor P5 is turned on, and the voltage of the fifth node Net5 (i.e., the gate of the sixth switching transistor N6) is equal to the voltage of the second node Net2, i.e., VDD-0.7+input.
Since the source of the sixth switching tube N6 is connected to Input and the gate is connected to the fifth node Net5, vgs=vdd-0.7V of N6, which is a constant independent of the voltage of the analog Input signal Input. The on-resistance R on of the sixth switching transistor N6 (NMOS transistor) can be expressed as
Where mu n and C ox are process-dependent constants,Is the aspect ratio and is also a constant. Vth is the threshold voltage of the sixth switching tube N6. Substituting the value of Vgs (VDD-0.7V) into the above equation yields:
If V th is constant, then R on is not affected by the Input voltage as can be seen from the above equation. However, in practice, considering the effect of the lining bias of the NMOS transistor, V th is affected by V SB (the voltage difference between the source and the substrate ends), so in order to eliminate the effect of the lining bias effect on the on-resistance R on, the fifth switching transistor N5, the fourth switching transistor N4 and the fourth transistor P4 are added, so that the fourth node Net4 (i.e. the substrate end of the sixth switching transistor N6) is connected to the analog Input signal Input when clk=1, so that the voltages of the source and the substrate ends of the sixth switching transistor N6 are equal in the on state, i.e. V SB =0, and thus the effect of the lining bias effect on R on is eliminated.
In one example, the first, second and third transmission gates have the same structure. As shown in fig. 1, the first transmission gate includes a second switching transistor N2 and a second transistor P2 which are disposed opposite to each other, a gate of the second switching transistor N2 is connected to the first clock signal CLK as a first control signal Input terminal, a gate of the second transistor P2 is connected to the second clock signal CLKN as a second control signal Input terminal, a source of the second switching transistor N2 is connected to a source drain of the second transistor P2, and the two interconnections are connected to an analog Input signal Input and the first node Net1, respectively.
An analog-to-digital converter comprises the gate voltage bootstrap switch circuit. Specifically, the analog-digital converter includes a sample-hold module, and the sample-hold module uses the gate voltage bootstrap switch circuit in the above embodiment as a sampling switch.
An electronic device comprises the gate voltage bootstrap switch circuit. Specifically, the analog-digital converter in the electronic device includes a sample-hold module, and the sample-hold module uses the gate voltage bootstrap switch circuit in the above embodiment as a sampling switch.
In summary, in the gate voltage bootstrap switch circuit, the analog-to-digital converter and the electronic device provided by the embodiments of the present utility model, by setting the boost module, the Input analog Input signal Input is boosted, and the boosted signal is transmitted to the gate of the sixth switching tube N6, and further setting the third transmission gate to transmit the analog Input signal Input to the substrate end of the sixth switching tube N6, the voltage of the substrate end of the sixth switching tube N6 and the voltage of the source (the second electrode) are equal in the on state, so as to eliminate the influence of the lining bias effect on the on-resistance.
The above description is only illustrative of the preferred embodiments of the present utility model and is not intended to limit the scope of the present utility model, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (10)
1. A gate voltage bootstrapped switch circuit, comprising:
a first clock signal and a second clock signal, the logic voltages of the first clock signal and the second clock signal being opposite;
The first control signal input ends of the first transmission gate and the third transmission gate are connected with the first clock signal, and the second control signal input ends of the first transmission gate and the third transmission gate are connected with the second clock signal;
The signal input ends of the first transmission gate and the third transmission gate are connected with analog input signals and are also commonly connected to the second electrode of the sixth switching tube, the grid electrode of the sixth switching tube is connected with a fifth node, the substrate end of the sixth switching tube is connected with a fourth node, and the first electrode of the sixth switching tube is connected with analog output signals;
The signal output end of the first transmission gate is connected with a first node, the first node is also connected with a boosting module, the boosting module is connected with a second node so that a pressure difference exists between the second node and the first node, and the second node is connected with a fifth node;
The signal output end of the third transmission gate is connected with the fourth node, the fourth node is connected with the first electrode of the fifth switching tube, the grid electrode of the fifth switching tube is connected with the second clock signal, and the second electrode of the fifth switching tube is grounded.
2. The gate voltage bootstrapped switch circuit of claim 1, wherein the boost module includes a first capacitor and a first diode, the first node is connected to a first pole of the first capacitor, a second pole of the first capacitor is connected to a second node, the second node is further connected to a cathode of the first diode, and an anode of the first diode is connected to a supply voltage.
3. The gate voltage bootstrapped switch circuit of claim 2, further comprising a first switch tube, the first node being connected to a first electrode of the first switch tube, a gate of the first switch tube being connected to the second clock signal, a second electrode of the first switch tube being grounded.
4. The gate voltage bootstrapped switch circuit of claim 1, further comprising a second transmission gate, a first control signal input of the second transmission gate being connected to the first clock signal, a second control signal input of the second transmission gate being connected to the second clock signal, a signal input of the second transmission gate being connected to the analog input signal, and further commonly connected to a second electrode of the sixth switch transistor, a signal output of the second transmission gate being connected to a third node, the third node further being connected to a gate of a fifth transistor, a first electrode of the fifth transistor being connected to the second node, and a second electrode of the fifth transistor being connected to the fifth node.
5. The gate voltage bootstrapped switch circuit of claim 4, wherein the first clock signal is further connected to a gate of a first transistor, a second electrode of the first transistor is connected to the third node, and a first electrode of the first transistor is connected to a supply voltage.
6. The gate voltage bootstrapped switch circuit of claim 1, further comprising a seventh switch tube and an eighth switch tube, wherein the fifth node is connected to a second electrode of the seventh switch tube, a gate electrode of the seventh switch tube is connected to a power supply voltage, a second electrode of the seventh switch tube is connected to a second electrode of the eighth switch tube, and a gate electrode of the eighth switch tube is connected to the second clock signal.
7. The gate voltage bootstrapped switch circuit of claim 1, wherein the first clock signal obtains the second clock signal through an inverter.
8. The gate voltage bootstrapped switch circuit of claim 4, wherein the first transmission gate, the second transmission gate, and the third transmission gate have the same structure.
9. An analog to digital converter comprising a gate voltage bootstrapped switch circuit as in any one of claims 1-8.
10. An electronic device comprising a gate voltage bootstrapped switch circuit as in any one of claims 1-8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323089886.5U CN221042821U (en) | 2023-11-15 | 2023-11-15 | Grid voltage bootstrap switch circuit, analog-digital converter and electronic equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202323089886.5U CN221042821U (en) | 2023-11-15 | 2023-11-15 | Grid voltage bootstrap switch circuit, analog-digital converter and electronic equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN221042821U true CN221042821U (en) | 2024-05-28 |
Family
ID=91179824
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202323089886.5U Active CN221042821U (en) | 2023-11-15 | 2023-11-15 | Grid voltage bootstrap switch circuit, analog-digital converter and electronic equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN221042821U (en) |
-
2023
- 2023-11-15 CN CN202323089886.5U patent/CN221042821U/en active Active
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6975142B2 (en) | Semiconductor device | |
| US20060202736A1 (en) | Bootstrapped switch for sampling inputs with a signal range greater than supply voltage | |
| US20110133810A1 (en) | System and Method for a Semiconductor Switch | |
| US7567112B2 (en) | Voltage level shifter and method thereof | |
| CN108777579B (en) | Grid voltage bootstrapping switch | |
| US6512400B1 (en) | Integrated circuit comparator or amplifier | |
| CN101001085B (en) | Signal sampling hold circuit | |
| US7271452B2 (en) | Analog switch | |
| US7332941B2 (en) | Analog switch circuit and sample-and-hold circuit including the same | |
| WO1995020268A1 (en) | Semiconductor device | |
| US7471122B2 (en) | Shift register | |
| US8138815B2 (en) | Level converter | |
| US6370066B1 (en) | Differential output circuit | |
| CN110690884A (en) | Grid voltage bootstrap switch circuit adopting CMOS transmission gate | |
| US7619459B2 (en) | High speed voltage translator circuit | |
| Pouya et al. | A low-voltage high-speed high-linearity MOSFET-only analog bootstrapped switch for sample-and-hold circuits | |
| CN221042821U (en) | Grid voltage bootstrap switch circuit, analog-digital converter and electronic equipment | |
| Munoz et al. | Analogue switch for very low-voltage applications | |
| US20220302903A1 (en) | Circuits and methods for reducing kickback noise in a comparator | |
| US6975153B2 (en) | Low power input with hysteresis circuit and methods therefor | |
| US10873256B1 (en) | Charge-pump boosting circuit | |
| US5113150A (en) | Unity gain inverting amplifier providing linear transfer characteristics | |
| US12003234B2 (en) | Bootstrapped switch | |
| CN115865091A (en) | Grid voltage bootstrap switch circuit | |
| US11626864B1 (en) | Level shift circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| GR01 | Patent grant | ||
| GR01 | Patent grant |