CN114337676B

CN114337676B - IDAC circuit with simplified structure

Info

Publication number: CN114337676B
Application number: CN202111530801.5A
Authority: CN
Inventors: 王志鹏
Original assignee: Shandong Xinhui Microelectronics Technology Co ltd
Current assignee: Shandong Xinhui Microelectronics Technology Co ltd
Priority date: 2021-12-14
Filing date: 2021-12-14
Publication date: 2024-05-17
Anticipated expiration: 2041-12-14
Also published as: CN114337676A

Abstract

The invention relates to an iDAC circuit with a simplified structure, and belongs to the technical field of integrated circuits. The input end of the iDAC circuit is connected with a current source, and the iDAC circuit comprises 3n+1 PMOS tubes, N two-out-of-one switches S ₁、S₂、……、S_n and two NMOS tubes N ₁、N₂, wherein the PMOS tubes are ,M₁、M₂、……、M_n、M_n+1,P₁、P₂、……、P_n,Q₁、Q₂、……、Q_n, respectively. The invention has simple structure, takes a 6bit iDAC as an example, the invention can realize the function by only 19 PMOS tubes, which greatly reduces the area cost of a chip, and effectively weakens the inherent defects of the CMOS technology due to the greatly reduced use quantity of the MOS tubes, namely the problems of reduced accuracy caused by mismatching of the MOS tubes and overlarge current mirror proportion; the circuit can be widely applied to iDAC modules, and conventional MOS transistors are used, so that the circuit is very convenient to integrate.

Description

IDAC circuit with simplified structure

Technical Field

The invention relates to an iDAC circuit with a simplified structure, and belongs to the technical field of integrated circuits.

Background

In an analog CMOS integrated circuit, a current source is one of the most common functional modules, and can provide bias current for circuits such as an operational amplifier and a band gap reference, however, in some applications, the size of the current source is required to be flexibly configured, which has an iDAC (current digital-to-analog conversion) circuit, a conventional iDAC circuit is a 6bit iDAC as shown in fig. 1, if Iref is 1uA, the iDAC circuit can realize currents of 1uA to 63uA and which are integer multiples of 1uA, but the structure has a fatal problem, on the one hand, the number of MOS transistors is also increased sharply with increasing bit number, which tends to bring about an increase in area, on the other hand, the problem of mismatch of the MOS transistors also causes a deviation in mirror proportion, and for a CMOS process, the MOS transistors are relatively easy to duplicate accurately, but are mirrored from 1uA to 32uA even more, and the accuracy is not easy to realize.

Disclosure of Invention

The invention aims to solve the technical problems that: a simplified and accurate iDAC circuit is provided.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: the iDAC circuit with the simplified structure comprises 3n+1 PMOS tubes ,M₁、M₂、……、M_n、M_n+1,P₁、P₂、……、P_n,Q₁、Q₂、……、Q_n,, N two-out-of-one switches S ₁、S₂、……、S_n and two NMOS tubes N ₁、N₂; the gate ends of the PMOS tubes M ₁、M₂、……、M_n、M_n+1 are grounded, except that the source end of the PMOS tube M ₁ is connected with the input end of the iDAC circuit, the drain end of the PMOS tube M _n+1 is grounded, and the drain end of the rest PMOS tube M _n and the source end of the PMOS tube M _n+1; the gate ends of the PMOS pipes P ₁、P₂、……、P_n,Q₁、Q₂、……、Q_n are grounded, and the source ends of the PMOS pipes P ₁、P₂、……、P_n are respectively connected with the source ends of the corresponding PMOS pipes M ₁、M₂、……、M_n; the drain end of the PMOS tube P ₁、P₂、……、P_n is respectively connected with the source end of the corresponding PMOS tube Q ₁、Q₂、……、Q_n, the drain end of the PMOS tube Q ₁、Q₂、……、Q_n is respectively connected with the A end of the corresponding alternative switch S ₁、S₂、……、S_n, the B end of the alternative switch S ₁、S₂、……、S_n is grounded, and the C end of the alternative switch S ₁、S₂、……、S_n is connected with the drain end of the NMOS tube N ₁; the drain end of the NMOS tube N ₁ is connected with the gate end of the NMOS tube N ₁, and the source end of the NMOS tube N ₁ is grounded; the gate of the NMOS tube N ₁ is connected with the gate end of the NMOS tube N ₂, the source end of the NMOS tube N ₂ is connected with the ground, and the drain end of the NMOS tube N ₂ is connected with the output end of the iDAC circuit.

The beneficial effects of the invention are as follows: the invention has simple structure, takes a 6bit iDAC as an example, the invention can realize the function by only 19 PMOS tubes, which greatly reduces the area cost of a chip, and effectively weakens the inherent defects of the CMOS technology due to the greatly reduced use quantity of the MOS tubes, namely the problems of reduced accuracy caused by mismatching of the MOS tubes and overlarge current mirror proportion; the circuit can be widely applied to iDAC modules, and conventional MOS transistors are used, so that the circuit is very convenient to integrate.

Drawings

Fig. 1 is a conventional iDAC circuit described in the background of the invention.

Fig. 2 is a circuit diagram of a simplified-structure iDAC circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of current splitting in an embodiment of the invention.

Fig. 4 is a MOS equivalent circuit diagram of an embodiment of the present invention.

Fig. 5 is a schematic diagram of a new distribution network according to an embodiment of the present invention.

Detailed Description

Example 1

The iDAC circuit with the simplified structure comprises 3n+1 PMOS tubes ,M₁、M₂、……、M_n、M_n+1,P₁、P₂、……、P_n,Q₁、Q₂、……、Q_n,, N two-out-of-one switches S ₁、S₂、……、S_n and two NMOS tubes N ₁、N₂; the gate ends of the PMOS tubes M ₁、M₂、……、M_n、M_n+1 are grounded, except that the source end of the PMOS tube M ₁ is connected with the input end of the iDAC circuit, the drain end of the PMOS tube M _n+1 is grounded, and the drain end of the rest PMOS tube M _n and the source end of the PMOS tube M _n+1; the gate ends of the PMOS pipes P ₁、P₂、……、P_n,Q₁、Q₂、……、Q_n are grounded, and the source ends of the PMOS pipes P ₁、P₂、……、P_n are respectively connected with the source ends of the corresponding PMOS pipes M ₁、M₂、……、M_n; the drain end of the PMOS tube P ₁、P₂、……、P_n is respectively connected with the source end of the corresponding PMOS tube Q ₁、Q₂、……、Q_n, the drain end of the PMOS tube Q ₁、Q₂、……、Q_n is respectively connected with the A end of the corresponding alternative switch S ₁、S₂、……、S_n, the B end of the alternative switch S ₁、S₂、……、S_n is grounded, and the C end of the alternative switch S ₁、S₂、……、S_n is connected with the drain end of the NMOS tube N ₁; the drain end of the NMOS tube N ₁ is connected with the gate end of the NMOS tube N ₁, and the source end of the NMOS tube N ₁ is grounded; the gate of the NMOS tube N ₁ is connected with the gate end of the NMOS tube N ₂, the source end of the NMOS tube N ₂ is connected with the ground, and the drain end of the NMOS tube N ₂ is connected with the output end of the iDAC circuit.

As shown in fig. 2, a current source IBIAS and an iDAC network are formed, one end of the current source IBIAS is connected with a power supply, the other end is connected with an input end I _IN of the iDAC network, the iDAC network is formed by (3n+1) PMOS tubes M₁、M₂、……、M_n、M_n+1,P₁、P₂、……、P_n,Q₁、Q₂、……、Q_n,n switches S ₁、S₂、……、S_n with identical sizes, and two NMOS tubes N1 and N2, wherein the gate ends of the PMOS tubes M ₁、M₂、……、M_n、M_n+1 are grounded, the source end of the PMOS tube M ₁ is connected with the input end I _IN of the iDAC network, the drain end of the PMOS tube M ₁ is connected with the source end of the PMOS tube M ₂, the drain end of the PMOS tube M ₂ is connected with the source end of the PMOS tube M ₃, the drain end of the PMOS tube M ₃ is connected with the source end of the PMOS tube M ₄, the drain end of the PMOS tube M _n-1 is connected with the source end of the PMOS tube M _n, the drain end of the PMOS tube M _n is connected with the source end of the PMOS tube M _n+1, and the drain end of the PMOS tube M _n+1 is grounded, and the gate ends of the PMOS tube P ₁、P₂、……、P_n,Q₁、Q₂、……、Q_n are all grounded; the source end of the PMOS tube P ₁ is connected with the source end of the PMOS tube M ₁, the drain end of the PMOS tube P ₁ is connected with the source end of the PMOS tube Q ₁, the drain end of the PMOS tube Q ₁ is connected with the end A of the alternative switch S ₁, the end B of the alternative switch S ₁ is grounded, and the end C of the alternative switch S ₁ is connected with the drain end of the NMOS tube N1; the source end of the PMOS tube P ₂ is connected with the source end of the PMOS tube M ₂, the drain end of the PMOS tube P ₂ is connected with the source end of the PMOS tube Q ₂, the drain end of the PMOS tube Q ₂ is connected with the end A of the alternative switch S ₂, the end B of the alternative switch S ₂ is grounded, and the end C of the alternative switch S ₂ is connected with the drain end of the NMOS tube N1; the source end of the PMOS pipe P ₃ is connected with the source end of the PMOS pipe M ₃, the drain end of the PMOS pipe P ₃ is connected with the source end of the PMOS pipe Q ₃, the drain end of the PMOS pipe Q ₃ is connected with the end A of the switch S ₃, the end B of the switch S ₃ is grounded, the end C of the switch S ₃ is connected with the drain end of the NMOS pipe N1, and the like, the source end of the PMOS pipe P _n-1 is connected with the source end of the PMOS pipe M _n-1, the drain end of the PMOS pipe P _n-1 is connected with the source end of the PMOS pipe Q _n-1, the drain end of the PMOS pipe Q _n-1 is connected with the end A of the switch S _n-1, the end B of the switch S _n-1 is grounded, and the end C of the switch S _n-1 is connected with the drain end of the NMOS pipe N1; the source end of the PMOS tube P _n is connected with the source end of the PMOS tube M _n, the drain end of the PMOS tube P _n is connected with the source end of the PMOS tube Q _n, the drain end of the PMOS tube Q _n is connected with the end A of the alternative switch S _n, the end B of the alternative switch S _n is grounded, and the C end of the alternative switch S _n is connected with the drain end of the NMOS tube N ₁; the drain of NMOS tube N ₁ is connected to the gate of NMOS tube N ₁, the source of NMOS tube N ₁ is connected to the ground, the gate of NMOS tube N ₁ is connected to the gate of NMOS tube N ₂, the source of NMOS tube N ₂ is connected to the ground, and the drain of NMOS tube N ₂ is connected to the output end I _OUT of iDAC network.

As shown in fig. 3, it is assumed that the end a of the alternative switch S _n is connected to the end B to the ground, and that the current flowing from the node D _n is I ₀, because the dimensions of the MOS transistors M _n、M_n+1、P_n and Q _n are equal, the equivalent impedance of the two branches from the node D _n to the ground are also equal, and therefore, the currents flowing through the MOS transistor M _n、M_n+1 and the MOS transistor P _n、Q_n to the ground are also equal and equal to 1/2*I ₀. As shown in fig. 4, since the MOS transistors M _n、M_n+1 are connected in series and the gate is grounded, the MOS transistor P _n、Q_n is connected in series and the gate is grounded, the equivalent impedance from the node D _n to the ground is equivalent to the MOS transistor M _eff and the size is exactly the same as the sizes of the MOS transistors M _n、M_n+1、P_n and Q _n, the equivalent MOS transistor M _eff and the MOS transistor M _n-1、P_n-1、Q_n-1 can form a new shunt network, as shown in fig. 5, and so on, assuming that the sizes of the MOS transistors N1 and N2 are the same. Taking n=5 as an example, by controlling the switching of the one-out-of-two switch S ₀、S₁、S₂、S₃、S₄、S₅, an arbitrary magnitude of current of 1uA to 63uA, which is an integer multiple of 1uA, can be achieved. The structure is very simple and ingenious, the use quantity of the MOS tubes can be greatly reduced, the MOS mismatch requirement of a circuit is reduced, the cost of the chip area is reduced, the cost is effectively reduced, and the integration is convenient.

The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be provided in addition to the above embodiments. Any modifications, equivalent substitutions, improvements, etc. made by those skilled in the art, which are within the spirit and principles of the present invention, are intended to be included within the scope of the present invention.

Claims

1. An iDAC circuit of retrench structure, the input of iDAC circuit is connected with the current source, its characterized in that: the iDAC circuit comprises 3n+1 PMOS tubes ,M₁、M₂、……、M_n、M_n+1,P₁、P₂、……、P_n,Q₁、Q₂、……、Q_n,, N two-out-of-one switches S ₁、S₂、……、S_n and two NMOS tubes N ₁、N₂; the gate ends of the PMOS tubes M ₁、M₂、……、M_n、M_n+1 are grounded, except that the source end of the PMOS tube M ₁ is connected with the input end of the iDAC circuit, the drain end of the PMOS tube M _n+1 is grounded, and the drain end of the rest PMOS tube M _n and the source end of the PMOS tube M _n+1; the gate ends of the PMOS pipes P ₁、P₂、……、P_n,Q₁、Q₂、……、Q_n are grounded, and the source ends of the PMOS pipes P ₁、P₂、……、P_n are respectively connected with the source ends of the corresponding PMOS pipes M ₁、M₂、……、M_n; the drain end of the PMOS tube P ₁、P₂、……、P_n is respectively connected with the source end of the corresponding PMOS tube Q ₁、Q₂、……、Q_n, the drain end of the PMOS tube Q ₁、Q₂、……、Q _n is respectively connected with the A end of the corresponding alternative switch S ₁、S₂、……、S_n, the B end of the alternative switch S ₁、S₂、……、S_n is grounded, and the C end of the alternative switch S ₁、S₂、……、S_n is connected with the drain end of the NMOS tube N ₁; the drain end of the NMOS tube N ₁ is connected with the gate end of the NMOS tube N ₁, and the source end of the NMOS tube N ₁ is grounded; the gate of the NMOS tube N ₁ is connected with the gate end of the NMOS tube N ₂, the source end of the NMOS tube N ₂ is connected with the ground, and the drain end of the NMOS tube N ₂ is connected with the output end of the iDAC circuit.