CN114337676A - Simplify iDAC circuit of structure - Google Patents

Abstract

The invention relates to an iDAC circuit with a simplified structure, and belongs to the technical field of integrated circuits. An iDAC circuit with a simplified structure, wherein the input end of the iDAC circuit is connected with a current source, and the iDAC circuit comprises 3n +1 PMOS tubes, M is₁、M₂、……、M_n、M_n+1，P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nAnd also comprises n two-to-one switches S₁、S₂、……、S_nAnd two NMOS transistors N₁、N₂. The CMOS chip has a simple structure, and takes a 6-bit iDAC as an example, the function can be realized by only 19 PMOS tubes, so that the area overhead of the chip is greatly reduced, the use number of the MOS tubes is greatly reduced, and the inherent defects of the CMOS process, namely the problem of accuracy reduction caused by MOS tube mismatch and overlarge current mirror ratio, are effectively weakened; the circuit can be widely applied to iDAC modules, and conventional MOS tubes are used, so that the circuit is very convenient to integrate.

Description

Simplify iDAC circuit of structure

Technical Field

The invention relates to an iDAC circuit with a simplified structure, and belongs to the technical field of integrated circuits.

Background

In an analog CMOS integrated circuit, a current source is one of the most common functional blocks, which can provide bias current for circuits such as an operational amplifier, a bandgap reference, etc., however, in some applications, it is required that the size of the current source can be flexibly configured, and there is an iDAC (current digital-to-analog conversion) circuit, and a conventional iDAC circuit is shown in fig. 1, which is a 6-bit iDAC, and if Iref is 1uA, the iDAC circuit can realize currents of 1uA to 63uA and of an integral multiple of 1uA, but this structure has a fatal problem that as the bit number increases, on one hand, the number of MOS transistors also increases sharply, which will certainly increase the area, on the other hand, the mismatch problem of the MOS transistors will also cause the deviation of the mirror ratio, and for the CMOS process, the MOS transistors are relatively easy to accurately copy from 1uA to 2uA, but are mirrored from 1uA to 32uA and even larger, the accuracy is less easily achieved.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: a simplified and precise iDAC circuit is provided.

In order to solve the technical problems, the technical scheme provided by the invention is as follows: an iDAC circuit with a simplified structure comprises 3n +1 PMOS tubes respectively of M₁、M₂、……、M_n、M_n+1，P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nAnd also comprises n two-to-one switches S₁、S₂、……、S_nAnd two NMOS transistors N₁、N₂(ii) a PMOS tube M₁、M₂、……、M_n、M_n+1The grid ends of the PMOS tubes are all grounded except the PMOS tube M₁Source end of the PMOS tube is connected with the input end of the iDAC circuit_n+1The drain terminal of the PMOS transistor is grounded, and M of the rest PMOS transistor_nDrain terminal and PMOS transistor M_n+1The source end of (1); PMOS tube P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nThe grid ends of the PMOS tubes are all grounded, and the PMOS tubes P₁、P₂、……、P_nSource ends of the PMOS transistors M are respectively corresponding to the PMOS transistors M₁、M₂、……、M_nThe source end of the transformer is connected; PMOS tube P₁、P₂、……、P_nDrain terminals of the PMOS transistors are respectively corresponding to the PMOS transistors Q₁、Q₂、……、Q_nSource terminal of (1) connected with a PMOS transistor Q₁、Q₂、……、Q_nThe drain terminals of the switches are respectively corresponding to the two-way switch S₁、S₂、……、S_nEnd A of the switch is connected with an alternative switch S₁、S₂、……、S_nThe B ends are all grounded, and an alternative switch S₁、S₂、……、S_nC terminal of the NMOS transistor is connected with the NMOS transistor N₁The drain end of the first transistor is connected; NMOS tube N₁Drain terminal and NMOS tube N₁Is connected with the gate terminal of the NMOS tube N₁The source end of the transformer is grounded; NMOS tube N₁Is connected with an NMOS tube N₂Gate terminal of (1), NMOS tube N₂The source end of the NMOS tube N is grounded₂The drain terminal of the iDAC circuit is connected with the output terminal of the iDAC circuit.

The invention has the beneficial effects that: the CMOS chip has a simple structure, and takes a 6-bit iDAC as an example, the function can be realized by only 19 PMOS tubes, so that the area overhead of the chip is greatly reduced, the use number of the MOS tubes is greatly reduced, and the inherent defects of the CMOS process, namely the problem of accuracy reduction caused by MOS tube mismatch and overlarge current mirror ratio, are effectively weakened; the circuit can be widely applied to iDAC modules, and conventional MOS tubes are used, so that the circuit is very convenient to integrate.

Drawings

Fig. 1 is a conventional iDAC circuit as described in the background of the invention.

Fig. 2 is a circuit diagram of an iDAC circuit with a reduced structure according to an embodiment of the present invention.

FIG. 3 is a schematic diagram of current splitting according to an embodiment of the present invention.

Fig. 4 is a MOS equivalent circuit diagram of an embodiment of the invention.

Fig. 5 is a schematic diagram of a new shunt network according to an embodiment of the present invention.

Detailed Description

Example one

The iDAC circuit with a simplified structure of the embodiment includes 3n +1 PMOS transistors, M₁、M₂、……、M_n、M_n+1，P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nAnd also comprises n two-to-one switches S₁、S₂、……、S_nAnd two NMOS transistors N₁、N₂(ii) a PMOS tube M₁、M₂、……、M_n、M_n+1The grid ends of the PMOS tubes are all grounded except the PMOS tube M₁Source terminal and the iDACInput end connection of circuit, M of PMOS tube_n+1The drain terminal of the PMOS transistor is grounded, and M of the rest PMOS transistor_nDrain terminal and PMOS transistor M_n+1The source end of (1); PMOS tube P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nThe grid ends of the PMOS tubes are all grounded, and the PMOS tubes P₁、P₂、……、P_nSource ends of the PMOS transistors M are respectively corresponding to the PMOS transistors M₁、M₂、……、M_nThe source end of the transformer is connected; PMOS tube P₁、P₂、……、P_nDrain terminals of the PMOS transistors are respectively corresponding to the PMOS transistors Q₁、Q₂、……、Q_nSource terminal of (1) connected with a PMOS transistor Q₁、Q₂、……、Q_nThe drain terminals of the switches are respectively corresponding to the two-way switch S₁、S₂、……、S_nEnd A of the switch is connected with an alternative switch S₁、S₂、……、S_nThe B ends are all grounded, and an alternative switch S₁、S₂、……、S_nC terminal of the NMOS transistor is connected with the NMOS transistor N₁The drain end of the first transistor is connected; NMOS tube N₁Drain terminal and NMOS tube N₁Is connected with the gate terminal of the NMOS tube N₁The source end of the transformer is grounded; NMOS tube N₁Is connected with an NMOS tube N₂Gate terminal of (1), NMOS tube N₂The source end of the NMOS tube N is grounded₂The drain terminal of the iDAC circuit is connected with the output terminal of the iDAC circuit.

As shown in fig. 2, a current source IBIAS and an iDAC network are formed, one end of the current source IBIAS is connected with the power supply, and the other end is connected with the input end I of the iDAC network_INThe iDAC network consists of (3n +1) PMOS tubes M with the same size₁、M₂、……、M_n、M_n+1，P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nN two-way switches S₁、S₂、……、S_nAnd two NMOS transistors N1 and N2, wherein the PMOS transistor M₁、M₂、……、M_n、M_n+1The grid ends of the PMOS tubes are all grounded, and the PMOS tubes M₁The source end of the power amplifier is connected with the input end I of the iDAC network_INPMOS transistor M₁Drain terminal of the PMOS transistor M₂Source end ofPMOS transistor M₂Drain terminal of the PMOS transistor M₃Source terminal of (PMOS) transistor M₃Drain terminal of the PMOS transistor M₄Source end of (D), and so on, PMOS tube M_n-1Drain terminal of the PMOS transistor M_nSource terminal of (PMOS) transistor M_nDrain terminal of the PMOS transistor M_n+1Source terminal of (PMOS) transistor M_n+1The drain terminal of the PMOS transistor is grounded₁、P₂、……、P_n，Q₁、Q₂、……、Q_nThe grid ends of the grid electrodes are all grounded; PMOS tube P₁Source end of the PMOS tube M₁Source terminal of (PMOS) transistor P₁Drain terminal of the PMOS transistor Q₁Source terminal of (PMOS) transistor Q₁The drain terminal of the switch is connected with an alternative switch S₁End A of (1), alternative switch S₁The B end of the switch is grounded, and the switch S is an alternative switch₁C is connected with the drain end of an NMOS tube N1; PMOS tube P₂Source end of the PMOS tube M₂Source terminal of (PMOS) transistor P₂Drain terminal of the PMOS transistor Q₂Source terminal of (PMOS) transistor Q₂The drain terminal of the switch is connected with an alternative switch S₂End A of (1), alternative switch S₂The B end of the switch is grounded, and the switch S is an alternative switch₂C is connected with the drain end of an NMOS tube N1; PMOS tube P₃Source end of the PMOS tube M₃Source terminal of (PMOS) transistor P₃Drain terminal of the PMOS transistor Q₃Source terminal of (PMOS) transistor Q₃The drain terminal of the switch is connected with an alternative switch S₃End A of (1), alternative switch S₃The B end of the switch is grounded, and the switch S is an alternative switch₃C end of the PMOS tube P is connected with the drain end of the NMOS tube N1, and so on_n-1Source end of the PMOS tube M_n-1Source terminal of (PMOS) transistor P_n-1Drain terminal of the PMOS transistor Q_n-1Source terminal of (PMOS) transistor Q_n-1The drain terminal of the switch is connected with an alternative switch S_n-1End A of (1), alternative switch S_n-1The B end of the switch is grounded, and the switch S is an alternative switch_n-1C is connected with the drain end of an NMOS tube N1; PMOS tube P_nSource end of the PMOS tube M_nSource terminal of (PMOS) transistor P_nDrain terminal of the PMOS transistor Q_nSource terminal of (PMOS) transistor Q_nThe drain terminal of the switch is connected with an alternative switch S_nEnd A of (1), alternative switch S_nThe B end of the switch is grounded, and the switch S is an alternative switch_nC end of N-channel metal oxide semiconductor (NMOS) tube N₁The drain terminal of (1); NMOS tube N₁Drain terminal of the NMOS tube N₁Gate terminal of (1), NMOS tube N₁The source end of the NMOS tube N is grounded₁Is connected with an NMOS tube N₂Gate terminal of (1), NMOS tube N₂The source end of the NMOS tube N is grounded₂The drain terminal of the first transistor is connected with the output terminal I of the iDAC network_OUT。

As shown in FIG. 3, assume that either switch S is selected_nIs connected to B terminal to ground, and is assumed to be from D_nThe current flowing into the node is I₀Because the MOS transistor M_n、M_n+1、P_nAnd Q_nEqual size, therefore, from D_nThe equivalent impedances of the two branches from the node to the ground are also equal, and therefore, flow through the MOS transistor M_n、M_n+1And flows through the MOS transistor P_n、Q_nThe current to ground will also be equal and equal to 1/2I₀. As shown in fig. 4 again, since the MOS transistor M_n、M_n+1Series and gate terminal grounded MOS transistor P_n、Q_nIn series and with the gate terminal grounded, from D_nThe equivalent impedance of the node to the ground is equivalent to an MOS transistor M_effAnd the size and MOS transistor M_n、M_n+1、P_nAnd Q_nAre identical in size, and the equivalent MOS transistor M_effAnd can be connected with MOS transistor M_n-1、P_n-1、Q_n-1A new shunt network is formed, as shown in fig. 5, and so on, assuming that MOS transistors N1 and N2 are the same size. Take n-5 as an example, by controlling the alternative switch S₀、S₁、S₂、S₃、S₄、S₅The switching of (1 uA) to (63 uA) can be realized, and the current can be any current of which the magnitude is an integral multiple of 1 uA. The structure is very simple and ingenious, the use number of MOS tubes can be greatly reduced, the mismatch requirement of a circuit on MOS is reduced, the cost of the chip area is reduced, the cost is effectively reduced, and the integration is convenient.

The present invention is not limited to the specific technical solutions described in the above embodiments, and other embodiments may be made in the present invention in addition to the above embodiments. It will be understood by those skilled in the art that various changes, substitutions of equivalents, and alterations can be made without departing from the spirit and scope of the invention.

Claims (1)

1. The utility model provides an iDAC circuit of retrench structure, the input and the current source of iDAC circuit are connected which characterized in that: the iDAC circuit comprises 3n +1 PMOS tubes, M₁、M₂、……、M_n、M_n+1，P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nAnd also comprises n two-to-one switches S₁、S₂、……、S_nAnd two NMOS transistors N₁、N₂(ii) a PMOS tube M₁、M₂、……、M_n、M_n+1The grid ends of the PMOS tubes are all grounded except the PMOS tube M₁Source end of the PMOS tube is connected with the input end of the iDAC circuit_n+1The drain terminal of the PMOS transistor is grounded, and M of the rest PMOS transistor_nDrain terminal and PMOS transistor M_n+1The source end of (1); PMOS tube P₁、P₂、……、P_n，Q₁、Q₂、……、Q_nThe grid ends of the PMOS tubes are all grounded, and the PMOS tubes P₁、P₂、……、P_nSource ends of the PMOS transistors M are respectively corresponding to the PMOS transistors M₁、M₂、……、M_nThe source end of the transformer is connected; PMOS tube P₁、P₂、……、P_nDrain terminals of the PMOS transistors are respectively corresponding to the PMOS transistors Q₁、Q₂、……、Q_nSource terminal of (1) connected with a PMOS transistor Q₁、Q₂、……、Q _nThe drain terminals of the switches are respectively corresponding to the two-way switch S₁、S₂、……、S_nEnd A of the switch is connected with an alternative switch S₁、S₂、……、S_nThe B ends are all grounded, and an alternative switch S₁、S₂、……、S_nC terminal of the NMOS transistor is connected with the NMOS transistor N₁The drain end of the first transistor is connected; NMOS tube N₁Drain terminal and NMOS tube N₁Is connected with the gate terminal of the NMOS tube N₁The source end of the transformer is grounded; NMOS tube N₁Is connected with an NMOS tube N₂Gate terminal of (1), NMOS tube N₂The source end of the NMOS tube N is grounded₂The drain terminal of the iDAC circuit is connected with the output terminal of the iDAC circuit.

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