CN113703093A - Ultra-low loss silicon waveguide and preparation method thereof - Google Patents
Ultra-low loss silicon waveguide and preparation method thereof Download PDFInfo
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Abstract
The invention provides an ultra-low loss silicon waveguide and a preparation method thereof, wherein the preparation method comprises the following steps: selecting an SOI wafer as a substrate; thermally oxidizing an upper portion of the first silicon layer; etching the second silicon dioxide layer; depositing silicon dioxide to form a third silicon dioxide layer; injecting oxygen ions above the third silicon dioxide layer to form an oxygen-rich ion layer; etching to remove the second silicon dioxide layer and the third silicon dioxide layer; depositing silicon dioxide above the first silicon layer to form a fourth silicon dioxide layer; annealing at high temperature to enable the oxygen-enriched ion layer to react to form a fifth silicon dioxide layer; and etching to remove the fourth silicon dioxide layer to obtain a finished product, wherein the first silicon layer below the fifth silicon dioxide layer in the finished product is the waveguide layer, and the first silicon layer below the third bulge is the silicon waveguide. According to the method, the waveguide pattern is transferred to the buried layer, the problem of high side wall roughness caused by etching in the conventional silicon waveguide preparation scheme is solved, and the prepared silicon waveguide has the advantage of ultralow loss.
Description
Technical Field
The disclosure relates to the field of optoelectronic chips and integration, in particular to an ultra-low loss silicon waveguide and a preparation method thereof.
Background
The optoelectronic chip and the integration technology have the outstanding advantages of low power consumption, high speed, high reliability, small volume and the like, the advantages are core key technologies for breaking through bottlenecks in aspects of rate bandwidth, energy consumption volume, intellectualization, reconfigurability and the like of an information network, and the optoelectronic chip and the integration technology are widely applied to the fields of optical communication, sensing, calculation, biology, medicine, agriculture and the like.
The carrier for preparing the photoelectron integrated chip comprises silicon base, indium phosphide, lithium niobate, silicon nitride, silicon dioxide, polymer and other materials, wherein the silicon base has the advantages of small size, low energy consumption, CMOS process compatibility, convenience for realizing monolithic and micro-nano integration with the existing electronic device and photonic device and the like, and is the most common material for preparing the photoelectron integrated chip. Silicon photonics, which uses silicon-based to realize the functions of light generation, modulation, transmission, manipulation, detection, etc., has been recognized as one of ideal technologies that break through the bottlenecks of ultra-large capacity of computers and communications, ultra-high speed information transmission and processing, and has received high attention from researchers, and has become a hotspot in the field of recent optoelectronic research.
The silicon-based optical waveguide is a medium for guiding light waves to propagate in the silicon-based optical waveguide, is the most basic unit structure in an optoelectronic chip and an integration technology, and mainly has the main functions of limiting, transmitting, coupling light waves and the like. The types of optical waveguides comprise rectangular waveguides and ridge waveguides, the two waveguides are prepared by adopting an etching process, the side wall of the waveguide formed by etching is rough, the transmission loss of the waveguide is closely related to the roughness of the outer surface (including the side wall and the upper surface) of the waveguide, the larger the roughness is, the more serious the light scattering is, the larger the transmission loss of the light in the waveguide is, and the larger the transmission loss of the light in the waveguide is, so that the large-scale photoelectronic chip integration is limited.
Disclosure of Invention
Aiming at the defects in the prior art, the ultra-low loss silicon waveguide and the preparation method thereof are provided, the waveguide pattern is transferred to the buried layer, the problem of high side wall roughness caused by etching in the conventional silicon waveguide preparation scheme is solved, and the prepared silicon waveguide has the advantage of ultra-low loss. Meanwhile, the silicon waveguide prepared by the scheme can be vertically integrated with top silicon, and has the advantage of 3D photon integration.
A preparation method of an ultra-low loss silicon waveguide comprises the following steps:
s1, selecting an SOI wafer as a substrate, wherein the SOI wafer comprises a first silicon layer, a first silicon dioxide layer and a second silicon layer which are sequentially arranged from top to bottom, the first silicon layer and the second silicon layer are made of silicon, and the first silicon dioxide layer is made of silicon dioxide;
s2 thermally oxidizing the upper part of the first silicon layer to form a second silicon dioxide layer;
s3, etching the second silicon dioxide layer to form a first concave part in the etched area of the second silicon dioxide layer, wherein the rest area is a first convex part;
s4, depositing silicon dioxide with the same thickness above the first concave part and the first convex part to form a third silicon dioxide layer;
s5, injecting oxygen ions above the third silicon dioxide layer to form an oxygen-enriched ion layer in the first silicon layer, wherein the oxygen-enriched ion layer divides the lower part of the first silicon layer into an upper layer and a lower layer, the oxygen-enriched ion layer forms a second convex part corresponding to the first convex part and a second concave part corresponding to the first concave part;
s6, removing the second silicon dioxide layer and the third silicon dioxide layer by using an etching process;
s7 depositing silicon dioxide on the first silicon layer to form a fourth silicon dioxide layer;
s8, annealing at high temperature to enable oxygen ions in the oxygen-rich ion layer to react with silicon atoms to form a fifth silicon dioxide layer, wherein the second convex parts are converted to form third convex parts, and the second concave parts are converted to form third concave parts;
and S9, removing the fourth silicon dioxide layer by using an etching process to obtain a finished product, wherein the first silicon layer below the fifth silicon dioxide layer in the finished product is the waveguide layer, and the first silicon layer below the third raised part is the silicon waveguide.
Optionally, the thickness of the first silicon layer in the step S1 is 600 nm; the thickness of the second silicon dioxide layer in the step S2 is 100 nm.
Optionally, in the step S3, etching the second silicon dioxide layer until the first silicon layer below the second silicon dioxide layer is exposed, and stopping the etching operation; and/or the etching method in the step S3 selects dry etching or wet etching of plasma etching or reactive ion etching.
Optionally, the thickness of the third silicon dioxide layer in the step S4 is 50 nm; and/or, the deposition method in the step S4 is vapor deposition by Plasma Enhanced Chemical (PECVD).
Optionally, in step S5, the dose range of the oxygen ion implantation is 2 × 10 per square centimeter17～7×1017And (4) respectively.
Optionally, in the step S5, the ion implantation energy range is 150-.
Optionally, in step S5, the wafer is rotated by 90 ° in the same direction around the center of the wafer for every one-fourth of the total implanted oxygen ion dose.
Optionally, in the step S7, the thickness of the fourth silicon dioxide layer is 350 nm; and/or, the deposition method in the step S7 is inductively coupled plasma enhanced chemical vapor deposition.
Optionally, in the step S8, the annealing temperature is 1300 to 1350 ℃, and the annealing time is 5 to 8 hours.
The ultra-low loss silicon waveguide prepared by the preparation method is characterized in that: the waveguide layer comprises a first silicon layer, a fifth silicon dioxide layer, a waveguide layer, a first silicon dioxide layer and a second silicon layer which are arranged from top to bottom in sequence; the middle part of the fifth silicon dioxide layer protrudes upwards, and the waveguide layer below the protrusion of the fifth silicon dioxide layer is a silicon waveguide.
According to the preparation method of the ultra-low loss silicon waveguide, the waveguide pattern is transferred to the buried layer through oxygen ion implantation and high-temperature annealing, the problem of high side wall roughness caused by etching in the conventional silicon waveguide preparation scheme is solved, and the prepared silicon waveguide has the advantage of ultra-low loss. Meanwhile, the silicon waveguide prepared by the scheme can be vertically integrated with top silicon, and has the advantage of 3D photon integration.
Drawings
FIG. 1 schematically illustrates a flow chart of a method of fabricating an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;
FIG. 2 schematically illustrates a profile of oxygen ion concentration in an oxygen-rich ion layer with a third silicon dioxide layer of varying thickness as a function of implantation depth, in accordance with an embodiment of the disclosure;
FIG. 3 schematically illustrates a structural schematic of an ultra-low loss silicon waveguide in accordance with an embodiment of the disclosure;
in the figure, a first silicon layer-1, a first silicon dioxide layer-2, a second silicon layer-3, a second silicon dioxide layer-4, a first convex part-5, a third silicon dioxide layer-6, an oxygen-rich ion layer-7, a fourth silicon dioxide layer-8, a fifth silicon dioxide layer-9, a silicon waveguide-10 and a waveguide layer-11.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
Example 1
The embodiment of the disclosure provides an ultra-low loss silicon waveguide and a preparation method thereof.
FIG. 1 schematically illustrates a flow chart of a method of fabricating an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;
a preparation method of an ultra-low loss silicon waveguide comprises the following steps:
s1, selecting an SOI wafer as a substrate, wherein the SOI wafer comprises a first silicon layer 1, a first silicon dioxide layer 2 and a second silicon layer 3 which are sequentially arranged from top to bottom, the first silicon layer 1 and the second silicon layer 3 are made of silicon, and the first silicon dioxide layer 2 is made of silicon dioxide;
s2 thermally oxidizing the upper portion of the first silicon layer 1 to form a second silicon dioxide layer 4;
s3, etching the second silicon dioxide layer 4 to enable the etched area of the second silicon dioxide layer 4 to form a first concave part, and enabling the rest area to be a first convex part 5;
s4 depositing silicon dioxide with the same thickness on the first concave portion and the first convex portion 5 to form a third silicon dioxide layer 6;
s5 implanting oxygen ions above the third silicon dioxide layer 6, so as to form an oxygen-rich ion layer 7 in the first silicon layer 1, wherein the oxygen-rich ion layer 7 divides the lower portion of the first silicon layer 1 into an upper layer and a lower layer, the oxygen-rich ion layer 7 includes a second protrusion and a second recess, the second protrusion is correspondingly below the first protrusion 5, and the second recess is correspondingly below the first recess;
s6 removing the second silicon dioxide layer 4 and the third silicon dioxide layer 6 by using an etching process;
s7 depositing silicon dioxide over the first silicon layer 1 to form a fourth silicon dioxide layer 8;
s8, annealing at high temperature to enable oxygen ions in the oxygen-rich ion layer 7 to react with silicon atoms, wherein the oxygen-rich ion layer 7 after reaction is a fifth silicon dioxide layer 9, the second convex part is converted into a third convex part, and the second concave part is converted into a third concave part;
s9 uses an etching process to remove the fourth silicon dioxide layer 8, so as to obtain a finished product, in which the first silicon layer 1 under the fifth silicon dioxide layer 9 is the waveguide layer 11, and the first silicon layer 1 under the third protrusion is the silicon waveguide 10.
Further, the thickness of the first silicon layer 1 in the step S1 is 600 nm.
The first silicon layer 1 with the thickness of 600nm is selected, and the residual first silicon layer 1 with enough thickness can be remained for preparing other optoelectronic devices while the buried silicon waveguide 10 is formed, so that 3D photon integration is realized.
Further, the thickness of the second silicon dioxide layer 4 in the step S2 is 100 nm.
Further, in the step S2, the second silicon dioxide layer 4 is etched until the first silicon layer 1 under the second silicon dioxide layer 4 is exposed, and the etching operation is stopped.
Further, the etching method adopts dry etching or wet etching of plasma etching or reactive ion etching.
In general, the thickness of the second silica layer 4 is the ridge height of the silicon waveguide 10, that is, the thickness of the second protrusion is the ridge height of the silicon waveguide 10, and in this design, silicon waveguides 10 having different thicknesses can be manufactured as required.
Further, the thickness of the third silicon oxide layer 6 in the step S4 is 50 nm.
Further, the deposition method adopts the plasma enhanced chemical vapor deposition.
Further, in the step S5, the dose range of the oxygen ion implantation is 2 × 10 per square centimeter17And (4) respectively.
Further, in the step S5, the ion implantation energy is 150 KeV.
Further, in step S5, the wafer is rotated by 90 ° in the same direction around the center of the wafer for every one-fourth of the total implanted oxygen ion dose.
FIG. 2 schematically shows a profile of oxygen ion concentration in an oxygen-rich ion layer with a third silicon dioxide layer having thicknesses of 0nm, 50nm, 100nm, and 150nm, respectively, according to an embodiment of the disclosure;
because the thicknesses of the first concave part and the first convex part 5 formed after the second silicon dioxide layer 4 is etched are different, the thicknesses of all areas of the silicon dioxide barrier layer formed after the second silicon dioxide layer is combined with the third silicon dioxide layer 6 are also different. The silicon dioxide barrier layer reduces the oxygen ion implantation rate and thus affects the oxygen ion implantation depth, the thicker the silicon dioxide barrier layer, the shallower the oxygen ion implantation depth, which makes the oxygen ion-rich layer 7 directly under the first convex portion 5 shallower than the oxygen ion-rich layer 7 under the first concave portion.
Further, in step S6, the etching method is plasma etching.
Further, in step S7, the thickness of the fourth silicon dioxide layer 8 is 350nm, and the deposition method is inductively coupled plasma enhanced chemical vapor deposition.
The provision of the fourth silicon dioxide layer 8 prevents the first silicon layer 1 from being oxidised during a subsequent high temperature anneal.
Further, in the step S8, the annealing temperature is 1300 ℃, and the annealing time is 5 hours.
The melting point of silicon is 1410 ℃, the melting point of silicon dioxide is 1723 ℃, the annealing temperature is set to 1300 ℃, so that the silicon and the silicon dioxide are in a solid and liquid state, the interface of the silicon waveguide 10 and the fifth silicon dioxide layer 9 is smooth, and the loss of the silicon waveguide 10 is reduced; preferably, the annealing time is 5 hours; during the annealing, the oxygen ions react slowly with the silicon atoms, including the nucleation, growth, combination of the silicon dioxide precipitates and finally the formation of the uniform fifth silicon dioxide layer 9, the annealing time is too short to form the uniform fifth silicon dioxide layer 9, and the annealing time of 5 hours is an optimal time for forming the uniform fifth silicon dioxide layer 9.
Since the oxygen ion implantation depth directly under the first convex portion 5 is shallower than that of the other region, the fifth silicon oxide layer 9 directly under the first convex portion 5 is convex upward, thereby forming the silicon waveguide 10.
Because the annealing temperature is high and the annealing time is long, silicon and silicon dioxide are in a solid and liquid state, the viscosity is reduced, and atoms and molecules are almost in a flowing state, a very smooth silicon and silicon dioxide interface is formed, the problem of side wall roughness caused by etching in the conventional preparation method is avoided, and the silicon waveguide 10 has the ultralow loss characteristic; the damage caused by ion implantation in the first silicon layer 1 is repaired in high-temperature annealing, and the first silicon layer can be used for preparing other optoelectronic devices, so that the first silicon layer and the formed ultra-low loss silicon waveguide 10 are vertically integrated, 3D integration is realized, and the future large-scale optoelectronic integration is adapted.
Fig. 3 schematically illustrates a structural schematic of an ultra-low loss silicon waveguide in accordance with an embodiment of the present disclosure.
The ultra-low loss silicon waveguide prepared by the preparation method is characterized in that: the waveguide layer comprises a first silicon layer 1, a fifth silicon dioxide layer 9, a waveguide layer 11, a first silicon dioxide layer 2 and a second silicon layer 3 which are arranged from top to bottom in sequence; the middle part of the fifth silicon dioxide layer 9 protrudes upwards, and the waveguide layer 11 below the protrusion of the fifth silicon dioxide layer 9 is a silicon waveguide 10.
Example 2
The embodiment of the disclosure provides an ultra-low loss silicon waveguide and a preparation method thereof.
FIG. 1 schematically illustrates a flow chart of a method of fabricating an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;
a preparation method of an ultra-low loss silicon waveguide comprises the following steps:
s1, selecting an SOI wafer as a substrate, wherein the SOI wafer comprises a first silicon layer 1, a first silicon dioxide layer 2 and a second silicon layer 3 which are sequentially arranged from top to bottom, the first silicon layer 1 and the second silicon layer 3 are made of silicon, and the first silicon dioxide layer 2 is made of silicon dioxide;
s2 thermally oxidizing the upper portion of the first silicon layer 1 to form a second silicon dioxide layer 4;
s3, etching the second silicon dioxide layer 4 to enable the etched area of the second silicon dioxide layer 4 to form a first concave part, and enabling the rest area to be a first convex part 5;
s4 depositing silicon dioxide with the same thickness on the first concave portion and the first convex portion 5 to form a third silicon dioxide layer 6;
s5 implanting oxygen ions above the third silicon dioxide layer 6, so as to form an oxygen-rich ion layer 7 in the first silicon layer 1, wherein the oxygen-rich ion layer 7 divides the lower portion of the first silicon layer 1 into an upper layer and a lower layer, the oxygen-rich ion layer 7 includes a second protrusion and a second recess, the second protrusion is correspondingly below the first protrusion 5, and the second recess is correspondingly below the first recess;
s6 removing the second silicon dioxide layer 4 and the third silicon dioxide layer 6 by using an etching process;
s7 depositing silicon dioxide over the first silicon layer 1 to form a fourth silicon dioxide layer 8;
s8, annealing at high temperature to enable oxygen ions in the oxygen-rich ion layer 7 to react with silicon atoms, wherein the oxygen-rich ion layer 7 after reaction is a fifth silicon dioxide layer 9, the second convex part is converted into a third convex part, and the second concave part is converted into a third concave part;
s9 uses an etching process to remove the fourth silicon dioxide layer 8, so as to obtain a finished product, in which the first silicon layer 1 under the fifth silicon dioxide layer 9 is the waveguide layer 11, and the first silicon layer 1 under the third protrusion is the silicon waveguide 10.
Further, the thickness of the first silicon layer 1 in the step S1 is 600 nm.
The first silicon layer 1 with the thickness of 600nm is selected, and the residual first silicon layer 1 with enough thickness can be remained for preparing other optoelectronic devices while the buried silicon waveguide 10 is formed, so that 3D photon integration is realized.
Further, the thickness of the second silicon dioxide layer 4 in the step S2 is 100 nm.
Further, in the step S2, the second silicon dioxide layer 4 is etched until the first silicon layer 1 under the second silicon dioxide layer 4 is exposed, and the etching operation is stopped.
Further, the etching method adopts dry etching or wet etching of plasma etching or reactive ion etching.
In general, the thickness of the second silica layer 4 is the ridge height of the silicon waveguide 10, that is, the thickness of the second protrusion is the ridge height of the silicon waveguide 10, and in this design, silicon waveguides 10 having different thicknesses can be manufactured as required.
Further, the thickness of the third silicon oxide layer 6 in the step S4 is 50 nm.
Further, the deposition method adopts the plasma enhanced chemical vapor deposition.
Further, in the step S5, the dose range of the oxygen ion implantation is 7 × 10 per square centimeter17And (4) respectively.
Further, in the step S5, the ion implantation energy range is 200 KeV.
Further, in step S5, the wafer is rotated by 90 ° in the same direction around the center of the wafer for every one-fourth of the total implanted oxygen ion dose.
FIG. 2 schematically shows a profile of oxygen ion concentration in an oxygen-rich ion layer with a third silicon dioxide layer having thicknesses of 0nm, 50nm, 100nm, and 150nm, respectively, according to an embodiment of the disclosure;
because the thicknesses of the first concave part and the first convex part 5 formed after the second silicon dioxide layer 4 is etched are different, the thicknesses of all areas of the silicon dioxide barrier layer formed after the second silicon dioxide layer is combined with the third silicon dioxide layer 6 are also different. The silicon dioxide barrier layer reduces the oxygen ion implantation rate and thus affects the oxygen ion implantation depth, the thicker the silicon dioxide barrier layer, the shallower the oxygen ion implantation depth, which makes the oxygen ion-rich layer 7 directly under the first convex portion 5 shallower than the oxygen ion-rich layer 7 under the first concave portion.
Further, in step S6, the etching method is plasma etching.
Further, in step S7, the thickness of the fourth silicon dioxide layer 8 is 350nm, and the deposition method is inductively coupled plasma enhanced chemical vapor deposition.
The provision of the fourth silicon dioxide layer 8 prevents the first silicon layer 1 from being oxidised during a subsequent high temperature anneal
Further, in the step S8, the annealing temperature is 1350 ℃ and the annealing time is 8 hours.
The melting point of silicon is 1410 ℃, the melting point of silicon dioxide is 1723 ℃, the annealing temperature is set to 1350 ℃, so that the silicon and the silicon dioxide are in a solid and liquid state, the interface of the silicon waveguide 10 and the fifth silicon dioxide layer 9 is smooth, and the loss of the silicon waveguide 10 is reduced; preferably, the annealing time is 8 hours; during the annealing, the oxygen ions react slowly with the silicon atoms, including the nucleation, growth, combination of the silicon dioxide precipitates and finally the formation of the uniform fifth silicon dioxide layer 9, the annealing time is too short to form the uniform fifth silicon dioxide layer 9, and the annealing time of 8 hours is the optimum time for forming the uniform fifth silicon dioxide layer 9.
Since the oxygen ion implantation depth directly under the first convex portion 5 is shallower than that of the other region, the fifth silicon oxide layer 9 directly under the first convex portion 5 is convex upward, thereby forming the silicon waveguide 10.
Because the annealing temperature is high and the annealing time is long, silicon and silicon dioxide are in a solid and liquid state, the viscosity is reduced, and atoms and molecules are almost in a flowing state, a very smooth silicon and silicon dioxide interface is formed, the problem of side wall roughness caused by etching in the conventional preparation method is avoided, and the silicon waveguide 10 has the ultralow loss characteristic; the damage caused by ion implantation in the first silicon layer 1 is repaired in high-temperature annealing, and the first silicon layer can be used for preparing other optoelectronic devices, so that the first silicon layer and the formed ultra-low loss silicon waveguide 10 are vertically integrated, 3D integration is realized, and the future large-scale optoelectronic integration is adapted.
Fig. 3 schematically illustrates a structural schematic of an ultra-low loss silicon waveguide in accordance with an embodiment of the present disclosure.
The ultra-low loss silicon waveguide prepared by the preparation method is characterized in that: the waveguide layer comprises a first silicon layer 1, a fifth silicon dioxide layer 9, a waveguide layer 11, a first silicon dioxide layer 2 and a second silicon layer 3 which are arranged from top to bottom in sequence; the middle part of the fifth silicon dioxide layer 9 protrudes upwards, and the waveguide layer 11 below the protrusion of the fifth silicon dioxide layer 9 is a silicon waveguide 10.
Example 3
The embodiment of the disclosure provides an ultra-low loss silicon waveguide and a preparation method thereof.
FIG. 1 schematically illustrates a flow chart of a method of fabricating an ultra-low loss silicon waveguide according to an embodiment of the present disclosure;
a preparation method of an ultra-low loss silicon waveguide comprises the following steps:
s1, selecting an SOI wafer as a substrate, wherein the SOI wafer comprises a first silicon layer 1, a first silicon dioxide layer 2 and a second silicon layer 3 which are sequentially arranged from top to bottom, the first silicon layer 1 and the second silicon layer 3 are made of silicon, and the first silicon dioxide layer 2 is made of silicon dioxide;
s2 thermally oxidizing the upper portion of the first silicon layer 1 to form a second silicon dioxide layer 4;
s3, etching the second silicon dioxide layer 4 to enable the etched area of the second silicon dioxide layer 4 to form a first concave part, and enabling the rest area to be a first convex part 5;
s4 depositing silicon dioxide with the same thickness on the first concave portion and the first convex portion 5 to form a third silicon dioxide layer 6;
s5 implanting oxygen ions above the third silicon dioxide layer 6, so as to form an oxygen-rich ion layer 7 in the first silicon layer 1, wherein the oxygen-rich ion layer 7 divides the lower portion of the first silicon layer 1 into an upper layer and a lower layer, the oxygen-rich ion layer 7 includes a second protrusion and a second recess, the second protrusion is correspondingly below the first protrusion 5, and the second recess is correspondingly below the first recess;
s6 removing the second silicon dioxide layer 4 and the third silicon dioxide layer 6 by using an etching process;
s7 depositing silicon dioxide over the first silicon layer 1 to form a fourth silicon dioxide layer 8;
s8, annealing at high temperature to enable oxygen ions in the oxygen-rich ion layer 7 to react with silicon atoms, wherein the oxygen-rich ion layer 7 after reaction is a fifth silicon dioxide layer 9, the second convex part is converted into a third convex part, and the second concave part is converted into a third concave part;
s9, removing the fourth silicon dioxide layer 8 by etching to obtain the final product, wherein the first silicon layer 1 under the fifth silicon dioxide layer 9 is the waveguide layer 11, and the first silicon layer 1 under the third raised part is the silicon waveguide 10
Further, the thickness of the first silicon layer 1 in the step S1 is 600 nm.
The first silicon layer 1 with the thickness of 600nm is selected, and the residual first silicon layer 1 with enough thickness can be remained for preparing other optoelectronic devices while the buried silicon waveguide 10 is formed, so that 3D photon integration is realized.
Further, the thickness of the second silicon dioxide layer 4 in the step S2 is 100 nm.
Further, in the step S2, the second silicon dioxide layer 4 is etched until the first silicon layer 1 under the second silicon dioxide layer 4 is exposed, and the etching operation is stopped.
Further, the etching method adopts dry etching or wet etching of plasma etching or reactive ion etching.
In general, the thickness of the second silica layer 4 is the ridge height of the silicon waveguide 10, that is, the thickness of the second protrusion is the ridge height of the silicon waveguide 10, and in this design, silicon waveguides 10 having different thicknesses can be manufactured as required.
Further, the thickness of the third silicon oxide layer 6 in the step S4 is 50 nm.
Further, the deposition method adopts the plasma enhanced chemical vapor deposition.
Further, in the step S5, the dose range of the oxygen ion implantation is 5 × 10 per square centimeter17And (4) respectively.
Further, in the step S5, the ion implantation energy range is 180 KeV.
Further, in step S5, the wafer is rotated by 90 ° in the same direction around the center of the wafer for every one-fourth of the total implanted oxygen ion dose.
FIG. 2 schematically shows a profile of oxygen ion concentration in an oxygen-rich ion layer with a third silicon dioxide layer having thicknesses of 0nm, 50nm, 100nm, and 150nm, respectively, according to an embodiment of the disclosure;
because the thicknesses of the first concave part and the first convex part 5 formed after the second silicon dioxide layer 4 is etched are different, the thicknesses of all areas of the silicon dioxide barrier layer formed after the second silicon dioxide layer is combined with the third silicon dioxide layer 6 are also different. The silicon dioxide barrier layer reduces the oxygen ion implantation rate and thus affects the oxygen ion implantation depth, the thicker the silicon dioxide barrier layer, the shallower the oxygen ion implantation depth, which makes the oxygen ion-rich layer 7 directly under the first convex portion 5 shallower than the oxygen ion-rich layer 7 under the first concave portion.
The oxygen ion implantation dose and energy respectively determine the thickness and depth of the oxygen-rich ion layer 7, and the total oxygen ion implantation dose D in this figure is 5 × 10 in order to obtain a low defect density, high quality, continuous buried silicon dioxide layer17/cm2The ion implantation energy is 180KeV, and in the case where the thickness of the third silicon oxide layer 6 is 50nm, the oxygen ion concentration is mainly distributed at a depth of 380nm, which can easily form the silicon waveguide 10, and sufficient top silicon remains, so that the thickness of the third silicon oxide layer 6 is set to 50 nm.
Further, in step S6, the etching method is plasma etching.
Further, in step S7, the thickness of the fourth silicon dioxide layer 8 is 350nm, and the deposition method is inductively coupled plasma enhanced chemical vapor deposition.
The provision of the fourth silicon dioxide layer 8 prevents the first silicon layer 1 from being oxidised during a subsequent high temperature anneal
Further, in step S8, the annealing temperature is 1325 ℃ and the annealing time is 6.5 hours.
The melting point of silicon is 1410 ℃, the melting point of silicon dioxide is 1723 ℃, the annealing temperature is set to 1300-1350 ℃, so that the silicon and the silicon dioxide are in a solid and liquid state, the interface of the silicon waveguide 10 and the fifth silicon dioxide layer 9 is smooth, and the loss of the silicon waveguide 10 is reduced; preferably, the annealing time is 5-8 hours; in the annealing process, the reaction between the oxygen ions and the silicon atoms is slow, the reaction comprises the nucleation, the growth, the combination of silicon dioxide precipitates and the final formation of the uniform fifth silicon dioxide layer 9, the annealing time is too short to form the uniform fifth silicon dioxide layer 9, and the annealing time of 5-8 hours is the optimal time for forming the uniform fifth silicon dioxide layer 9.
Since the oxygen ion implantation depth directly under the first convex portion 5 is shallower than that of the other region, the fifth silicon oxide layer 9 directly under the first convex portion 5 is convex upward, thereby forming the silicon waveguide 10.
Because the annealing temperature is high and the annealing time is long, silicon and silicon dioxide are in a solid and liquid state, the viscosity is reduced, and atoms and molecules are almost in a flowing state, a very smooth silicon and silicon dioxide interface is formed, the problem of side wall roughness caused by etching in the conventional preparation method is avoided, and the silicon waveguide 10 has the ultralow loss characteristic; the damage caused by ion implantation in the first silicon layer 1 is repaired in high-temperature annealing, and the first silicon layer can be used for preparing other optoelectronic devices, so that the first silicon layer and the formed ultra-low loss silicon waveguide 10 are vertically integrated, 3D integration is realized, and the future large-scale optoelectronic integration is adapted.
Fig. 3 schematically illustrates a structural schematic of an ultra-low loss silicon waveguide in accordance with an embodiment of the present disclosure.
The ultra-low loss silicon waveguide prepared by the preparation method is characterized in that: the waveguide layer comprises a first silicon layer 1, a fifth silicon dioxide layer 9, a waveguide layer 11, a first silicon dioxide layer 2 and a second silicon layer 3 which are arranged from top to bottom in sequence; the middle part of the fifth silicon dioxide layer 9 protrudes upwards, the waveguide layer 11 below the protrusion of the fifth silicon dioxide layer 9 is a silicon waveguide 10, and the thickness of the first silicon layer 1 is 220 nm.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A preparation method of an ultra-low loss silicon waveguide is characterized by comprising the following steps:
s1, selecting an SOI wafer as a substrate, wherein the SOI wafer comprises a first silicon layer (1), a first silicon dioxide layer (2) and a second silicon layer (3) which are sequentially arranged from top to bottom, and the first silicon layer (1) is made of silicon;
s2 thermally oxidizing the upper part of the first silicon layer (1) to form a second silicon dioxide layer (4);
s3, etching the second silicon dioxide layer (4) to enable the etched area of the second silicon dioxide layer (4) to form a first concave part, and enabling the rest area to be a first convex part (5);
s4, depositing silicon dioxide with the same thickness above the first concave part and the first convex part (5) to form a third silicon dioxide layer (6);
s5, injecting oxygen ions above the third silicon dioxide layer (6) to form an oxygen-enriched ion layer (7) in the first silicon layer (1), wherein the oxygen-enriched ion layer (7) divides the lower part of the first silicon layer (1) into an upper layer and a lower layer, the oxygen-enriched ion layer (7) forms a second convex part corresponding to the first convex part (5) and a second concave part corresponding to the first concave part;
s6, removing the second silicon dioxide layer (4) and the third silicon dioxide layer (6) by using an etching process;
s7 depositing silicon dioxide on the first silicon layer (1) to form a fourth silicon dioxide layer (8);
s8, annealing at high temperature, so that oxygen ions in the oxygen ion-rich layer (7) react with silicon atoms to form a fifth silicon dioxide layer (9), the second convex parts are converted to form third convex parts, and the second concave parts are converted to form third concave parts;
s9, removing the fourth silicon dioxide layer (8) by using an etching process to obtain a finished product, wherein the first silicon layer (1) below the fifth silicon dioxide layer (9) in the finished product is the waveguide layer (11), and the first silicon layer (1) below the third raised portion is the silicon waveguide (10).
2. The production method according to claim 1, wherein the thickness of the first silicon layer (1) in the step S1 is 600 nm; the thickness of the second silicon dioxide layer (4) in the step S2 is 100 nm.
3. The production method according to claim 1, wherein the etching operation is stopped in the step S3 until the second silicon oxide layer (4) is etched until the first silicon layer (1) under the second silicon oxide layer (4) is exposed; and/or the etching method in the step S3 selects dry etching or wet etching of plasma etching or reactive ion etching.
4. The production method according to claim 1, wherein the thickness of the third silicon dioxide layer (6) in the step S4 is 50 nm; and/or the deposition method in the step S4 is vapor deposition with plasma enhanced chemical.
5. The method as claimed in claim 1, wherein the oxygen ion implantation dosage in step S5 is in the range of 2 x 10 per square centimeter17～7×1017And (4) respectively.
6. The method as claimed in claim 1, wherein in the step S5, the ion implantation energy is in the range of 150-200 KeV.
7. The method as claimed in claim 1, wherein in step S5, the wafer is rotated 90 ° around the center of the wafer in the same direction for every one-fourth of the total implanted oxygen ion dose.
8. The production method according to claim 1, wherein in the step S7, the thickness of the fourth silicon dioxide layer (8) is 350 nm; and/or the deposition method adopts inductively coupled plasma enhanced chemical vapor deposition.
9. The method according to claim 1, wherein in step S8, the annealing temperature is 1300-1350 ℃ and the annealing time is 5-8 hours.
10. An ultra-low loss silicon waveguide prepared by the preparation method of any one of claims 1 to 9, wherein: the waveguide structure comprises a first silicon layer (1), a fifth silicon dioxide layer (9), a waveguide layer (11), a first silicon dioxide layer (2) and a second silicon layer (3) which are arranged from top to bottom in sequence; the middle part of the fifth silicon dioxide layer (9) protrudes upwards, and the waveguide layer (11) below the protrusion of the fifth silicon dioxide layer (9) is a silicon waveguide (10).
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