CN113690136A - Method for manufacturing third generation semiconductor - Google Patents
Method for manufacturing third generation semiconductor Download PDFInfo
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- CN113690136A CN113690136A CN202110776052.8A CN202110776052A CN113690136A CN 113690136 A CN113690136 A CN 113690136A CN 202110776052 A CN202110776052 A CN 202110776052A CN 113690136 A CN113690136 A CN 113690136A
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/2003—Nitride compounds
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7781—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with inverted single heterostructure, i.e. with active layer formed on top of wide bandgap layer, e.g. IHEMT
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Abstract
The invention relates to the technical field of semiconductor manufacturing, and discloses a manufacturing method of a third generation semiconductor, which comprises the following steps: providing a substrate; epitaxially depositing a buffer layer on the substrate; epitaxially depositing an electronic property layer on the buffer layer; forming a protective layer on the electronic characteristic layer; and forming a through hole on the protective layer to penetrate to the electronic characteristic layer. The required electronic characteristic layer is preset on the substrate in an epitaxial deposition mode, then according to the required function, the via hole penetrates to the position in the corresponding electronic characteristic layer, the required function is realized, ion interpenetration and ion injury between different film layers generated by the traditional ion injection and high-temperature diffusion mode are avoided, the component characteristics are further stabilized, the performance reliability of a semiconductor device is improved, the influence of signal distortion is avoided, more stable work rate output is achieved, and stable application on high-frequency and high-power devices is realized.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to a manufacturing method of a third-generation semiconductor.
Background
In the semiconductor industry, semiconductor chips are typically formed using group IV element (e.g., silicon) based semiconductor devices and/or germanium based semiconductor devices. In particular, in the semiconductor industry, silicon-based semiconductors comprising silicon, silicon germanium alloys, or silicon carbon alloys are generally available at low cost.
In the prior art, a component channel is established by means of ion implantation and high-temperature diffusion, multiple times of ion implantation in a local area damages crystal lattices in an implantation junction area, and high-temperature diffusion of ions not only achieves the purpose of ion uniformity, but also causes ion mutual permeation side effects among different dielectric layers, and finally leads to distortion, short service life and reliability failure of a semiconductor device.
Disclosure of Invention
The invention mainly aims to provide a manufacturing method of a third generation semiconductor, aiming at solving the technical problems of distortion, shortened service life and failed reliability of a semiconductor device.
In order to achieve the above object, the present invention provides a method for manufacturing a third generation semiconductor, the method comprising the steps of:
providing a substrate;
epitaxially depositing a buffer layer on the substrate;
epitaxially depositing an electronic property layer on the buffer layer;
forming a protective layer on the electronic characteristic layer;
and forming a through hole on the protective layer to penetrate to the electronic characteristic layer.
Optionally, in an embodiment, the step of epitaxially depositing an electronic property layer on the buffer layer includes:
epitaxially depositing a collector layer on the buffer layer;
epitaxially depositing a base electrode layer on the collector layer;
and epitaxially depositing an emitter electrode layer on the base electrode layer.
Optionally, in an embodiment, the step of epitaxially depositing an electronic property layer on the buffer layer includes:
epitaxially depositing an N-type substrate with a first ion concentration on the buffer layer to form a collector layer;
epitaxially depositing a P-type substrate on the collector layer to form a base electrode layer;
epitaxially depositing an N-type substrate with a second ion concentration on the base electrode layer to form an emitter electrode layer;
wherein the first ion concentration is less than the second ion concentration.
Optionally, in an embodiment, the manufacturing method further includes the steps of:
the third generation semiconductor is divided into a plurality of blocks.
Optionally, in an embodiment, the step of dividing the third generation semiconductor into a plurality of blocks includes: the third generation semiconductor is divided into blocks by photolithography and/or etching.
Optionally, in an embodiment, after the step of dividing the third generation semiconductor into a plurality of blocks by photolithography and/or etching, the method further includes: and injecting inert gas in a photoetching or etched space by a high-energy ion injection mode.
Optionally, in one embodiment, the electronic properties layer is deposited in a single lattice.
Optionally, in an embodiment, the step of forming a via hole in the protection layer to penetrate through to the electronic property layer includes: and forming a through hole penetrating to the electronic characteristic layer on the protective layer by photoetching and/or etching.
Optionally, in an embodiment, the step of forming a protective layer on the electronic property layer includes: and forming a protective layer on the electronic characteristic layer by chemical vapor deposition.
Optionally, in an embodiment, the step of epitaxially depositing an electronic property layer on the buffer layer includes:
epitaxially depositing a collector layer on the buffer layer;
epitaxially depositing a base electrode layer on the collector layer;
epitaxially depositing a two-dimensional electrical layer on the base electrode layer;
and epitaxially depositing an emitter electrode layer on the two-dimensional electrical layer.
According to the technical scheme provided by the invention, a multilayer structure is preset on a substrate in an epitaxial deposition mode, namely a required electronic characteristic layer is preset on the substrate in an epitaxial deposition mode, and then a through hole penetrates to the position in the corresponding electronic characteristic layer according to the required function to realize the required function, so that the ion interpenetration between different film layers and the damage between ions generated in the traditional ion implantation and high-temperature diffusion mode are avoided, the component characteristics are stabilized, the performance reliability of a semiconductor device is improved, the influence of signal distortion is avoided, more stable work rate output is achieved, and the stable application on high-frequency and high-power devices is realized; adjusting the crystal lattice through the buffer layer, and growing the electronic characteristic layer according to the adjusted crystal lattice; finally, a protective layer is arranged on the electronic characteristic layer to prevent the internal structure of the compound semiconductor from being damaged, such as scratching or corrosion, so that the performance of the compound semiconductor is weakened, and meanwhile, the internal structure of the compound semiconductor is isolated from being contacted with the outside, so that the performance of the compound semiconductor is prevented from being changed due to reaction.
Drawings
One or more embodiments are illustrated in drawings corresponding to, and not limiting to, the embodiments, in which elements having the same reference number designation may be represented as similar elements, unless specifically noted, the drawings in the figures are not to scale.
Fig. 1 is a schematic flow chart of one embodiment of a method for manufacturing a compound semiconductor of the present invention;
FIG. 2 is a schematic flow chart diagram of one embodiment of epitaxially depositing an electronic property layer of the present invention;
FIG. 3 is a schematic flow chart diagram of another embodiment of epitaxially depositing an electronic property layer according to the present invention;
FIG. 4 is a schematic diagram of a third generation semiconductor according to an embodiment of the present invention;
FIG. 5 is a block diagram illustrating an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another embodiment of a block of the present invention.
100, third generation semiconductors; 200. a block; 210. a substrate; 220. a buffer layer; 230. a collector layer; 240. a base electrode layer; 250. an emitter electrode layer; 260. a two-dimensional electron gas layer; 270. a protective layer; 280. a via hole; 290. an emitter conductive layer; 300. and an insulating layer.
Detailed Description
In order to facilitate an understanding of the invention, the invention is described in more detail below with reference to the accompanying drawings and specific examples. It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may be present. The terms "vertical," "horizontal," "left," "right," "inner," "outer," and the like as used herein are for descriptive purposes only. In the description of the present invention, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Furthermore, the technical features mentioned in the different embodiments of the invention described below can be combined with each other as long as they do not conflict with each other.
The compound semiconductor is a crystalline inorganic compound semiconductor, that is, a compound formed by two or more elements in a certain atomic ratio and having semiconductor properties such as a certain forbidden bandwidth and energy band structure. Including crystalline inorganic compounds (e.g., group III-V, group II-VI compound semiconductors) and solid solutions thereof, amorphous inorganic compounds (e.g., glass semiconductors), organic compounds (e.g., organic semiconductors), oxide semiconductors, and the like. The compound semiconductor is generally referred to as a crystalline inorganic compound semiconductor.
The embodiment of the invention takes the process flow of the epitaxial generation of the wide bandgap of the third generation compound semiconductor as an example for explanation, and the structure is combined with the characteristics of the wide bandgap component of the third generation compound semiconductor and is preset on the substrate in an epitaxial deposition mode. The production of the wide bandgap component is achieved by matching the design and application requirements. The production mode of the process flow can be suitable for the epitaxial application of silicon-based gallium nitride and silicon carbide-based gallium nitride. The method is widely applicable to high-frequency radio frequency devices, high-power electronic devices, communication and sensing. The method comprises the following specific steps:
referring to fig. 1, an embodiment of the present invention discloses a method for manufacturing a compound semiconductor, including:
s1, providing a substrate;
wherein the substrate is made of SiC or Al2O3And one or more kinds of Si.
S2, epitaxially depositing a buffer layer on the substrate;
the buffer layer is made of AlGaN and is used for adjusting crystal lattices.
S3, epitaxially depositing an electronic characteristic layer on the buffer layer;
wherein the electronic characteristic layer is deposited in a single crystal lattice manner, so that the electronic characteristic layer is stably grown along the crystal lattice, and a uniform and stable channel which is not influenced by the outside is formed.
S4, forming a protective layer on the electronic characteristic layer;
specifically, in the step of S4, a protective layer is formed on the electronic characteristic layer by chemical vapor deposition, and the protective layer is made of SiN;
the protective layer is arranged on the surface of the compound semiconductor, so that the internal structure of the compound semiconductor is prevented from being damaged, such as scratching or corrosion, and the performance of the compound semiconductor is prevented from being weakened, and the internal structure of the compound semiconductor is also isolated from being in contact with the outside, so that the performance of the compound semiconductor is prevented from being changed due to reaction. SiN is an inorganic substance, is an important structural ceramic material, has high hardness, self lubricity and wear resistance, and is an atomic crystal; is resistant to oxidation at high temperature. It can resist cold and hot impact, and can be heated to above 1000 deg.C in air, and can be rapidly cooled and then rapidly heated, and can not be broken. Therefore, the SiN is used as a protective layer arranged on the surface of the compound semiconductor, so that the internal structure can be better protected, the service life of the compound semiconductor is prolonged, and the use performance of the compound semiconductor is ensured.
And S5, forming a via hole on the protective layer to penetrate to the electronic characteristic layer.
Specifically, a via hole is formed in the protective layer by photolithography and etching and penetrates to the electronic characteristic layer. The shape and size of the formed pattern can be precisely controlled by the photolithography and etching processes.
In the process of manufacturing the traditional silicon-based semiconductor, a component channel is established by means of ion implantation and high-temperature diffusion, multiple times of ion implantation in a local area damages crystal lattices in an implantation junction area, and high-temperature diffusion of ions achieves the aim of ion uniformity and also causes ion mutual permeation side effects among different dielectric layers, so that distortion, short service life and reliability failure of a semiconductor device are caused finally. In the scheme, a multilayer structure is preset on a substrate in an epitaxial deposition mode, namely a required electronic characteristic layer is preset on the substrate in an epitaxial deposition mode, and then a via hole penetrates to the position in the corresponding electronic characteristic layer according to the required function to realize the required function, so that the ion mutual permeation and the ion damage among different films generated in the traditional ion implantation and high-temperature diffusion mode are avoided, the component characteristics are stabilized, the performance reliability of a semiconductor device is improved, the influence of signal distortion is avoided, more stable work rate output is achieved, and the stable application on a high-frequency and high-power device is realized; adjusting the crystal lattice through the buffer layer, and growing the electronic characteristic layer according to the adjusted crystal lattice; finally, a protective layer is arranged on the electronic characteristic layer to prevent the internal structure of the compound semiconductor from being damaged, such as scratching or corrosion, so that the performance of the compound semiconductor is weakened, and meanwhile, the internal structure of the compound semiconductor is isolated from being contacted with the outside, so that the performance of the compound semiconductor is prevented from being changed due to reaction.
Further, the manufacturing method includes the steps of:
s6, dividing the third generation semiconductor into a plurality of blocks through photoetching and etching;
and S7, injecting inert gas in the photoetching or etched space by means of high-energy ion injection.
The shape and size of the formed pattern can be precisely controlled by the photolithography and etching processes, and in addition, it can simultaneously generate a profile over the entire chip surface. A plurality of blocks are formed through photoetching and etching processes, then inert gases such as helium and nitrogen are injected among the blocks to block the migration of ions, an isolation layer is formed, each block is isolated independently and not mutually interfered, and various different functions can be realized.
Specifically, referring to fig. 2, the step S3 includes:
s31, epitaxially depositing an N-type substrate with a first ion concentration on the buffer layer to form a collector layer;
the collector layer is made of GaN.
S32, epitaxially depositing a P-type substrate on the collector layer to form a base electrode layer;
and the base electrode layer is made of doped Be added into GaN.
S33, epitaxially depositing an N-type substrate with a second ion concentration on the base electrode layer to form an emitter electrode layer;
the emitter electrode layer is made of GaN and/or InGaN doped with Si.
In step S3, the first ion concentration is less than the second ion concentration.
According to the scheme, channels with different resistance values are formed by controlling the ion concentration in an epitaxial deposition N-type substrate, so that low opening resistance and high voltage resistance are formed, the using effect of a compound semiconductor is better, and the compound semiconductor is manufactured by an epitaxial deposition process method, so that the ion implantation concentration is easier to control, and the stability is better.
In another embodiment, referring to fig. 3, the step of S3 includes:
s34, epitaxially depositing an N-type substrate with a first ion concentration on the buffer layer to form a collector layer;
the collector layer is made of GaN.
S35, epitaxially depositing a P-type substrate on the collector layer to form a base electrode layer;
and the base electrode layer is made of doped Be added into GaN.
S36, epitaxially depositing a two-dimensional electric layer on the base electrode layer;
wherein the material of the two-dimensional electrical layer comprises AlGaN.
S37, epitaxially depositing an N-type substrate with a second ion concentration on the two-dimensional electric layer to form an emitter electrode layer;
the emitter electrode layer is made of GaN and/or InGaN doped with Si.
Specifically, the first ion concentration is less than the second ion concentration.
In this embodiment, the mobility of electrons is improved by providing a two-dimensional electric layer between the base electrode layer and the emitter electrode layer.
Referring to fig. 4 and 5, an embodiment of the invention further discloses a third generation semiconductor 100, which includes a plurality of blocks 200, each of the blocks 200 includes a substrate 210, a buffer layer 220, an electronic characteristic layer, a protection layer 270, and a plurality of vias 280; the buffer layer 220 is disposed on the substrate 210; the electronic property layer is arranged on the buffer layer 220, and the electronic property layer is of a multilayer structure; the protective layer 270 is disposed on the electronic characteristic layer; a plurality of the vias 280 penetrate from the outer surface of the protective layer 270 to the electronic properties layer.
In the present embodiment, the third generation semiconductor 100 is divided into a plurality of blocks 200, a required electronic characteristic layer is preset in each block 200, and then the via hole 280 penetrates to a position in the corresponding electronic characteristic layer according to a required function of each block 200, thereby implementing the function of each block 200; the required electronic characteristic layer is arranged on the substrate 210 in advance, and the through hole 280 is arranged as required, so that the ion interpenetration and ion damage between different film layers generated by the traditional ion implantation and high-temperature diffusion mode are avoided, the component characteristics are stabilized, the performance reliability of the semiconductor device is improved, the influence of signal distortion is avoided, more stable work rate output is achieved, and the stable application on high-frequency and high-power devices is realized; adjusting the crystal lattice through the buffer layer 220, and growing the electronic characteristic layer according to the adjusted crystal lattice; finally, a protective layer 270 is disposed on the electronic property layer to prevent the internal structure of the compound semiconductor from being damaged, such as scratched or corroded, and thus the performance of the compound semiconductor is reduced, and simultaneously, the internal structure of the compound semiconductor is isolated from contacting the outside, and the performance of the compound semiconductor is prevented from being changed due to reaction.
Specifically, the substrate 210 comprises one or more of SiC, Al2O3, and Si, and the thickness of the substrate 210 is 625 μm; the buffer layer 220 is arranged on the substrate 210 by means of epitaxial deposition, the epitaxial deposition thickness of the buffer layer 220 is 200nm, and the buffer layer 220 comprises AlGaN; the collector layer 230 is arranged on the buffer layer 220 in an epitaxial deposition mode, the epitaxial deposition thickness of the collector layer 230 is 700nm-1200nm, and the collector layer 230 comprises GaN; the base electrode layer 240 is arranged on the collector electrode layer 230 in an epitaxial deposition mode, the epitaxial deposition thickness of the base electrode layer 240 is 100nm-150nm, and the base electrode layer 240 comprises GaN; the emitter electrode layer 250 is disposed on the base electrode layer 240 by epitaxial deposition, the epitaxial deposition thickness of the emitter electrode layer 250 is 100nm-150nm, and the emitter electrode layer 250 includes GaN and/or InGaN; an emitter conductive layer 290 is disposed on the emitter layer 250 by epitaxial deposition, the epitaxial deposition thickness of the emitter conductive layer 290 is 100nm, the emitter conductive layer 290 includes InGaN, the protection layer 270 is disposed on the emitter layer 250 by epitaxial deposition, and the protection layer 270 includes SiN.
In the process of manufacturing the traditional silicon-based semiconductor, a component channel is arranged in a mode of ion implantation and high-temperature diffusion, the method is limited by the concentration and energy of an ion implanter, the resistance value and the width of the channel have a certain range, and the problems of distortion, shortened service life and failed reliability of a semiconductor device are easily caused due to the influence of uniformity and crystal lattice damage. In the scheme, a multilayer structure is preset on a substrate 210 in an epitaxial deposition mode, namely, a required electronic characteristic layer is preset on the substrate 210 in an epitaxial deposition mode, and then a via hole 280 penetrates to the position in the corresponding electronic characteristic layer according to the required function to realize the required function, so that the ion interpenetration between different films and the damage between ions generated in the traditional ion implantation and high-temperature diffusion mode are avoided, the component characteristics are stabilized, the performance reliability of a semiconductor device is improved, the influence of signal distortion is avoided, more stable work rate output is achieved, and stable application on high-frequency and high-power devices is realized.
And a protective layer 270 is disposed on the surface of the compound semiconductor to prevent the internal structure of the compound semiconductor from being damaged, such as scratched or corroded, and thus the performance of the compound semiconductor is reduced, and meanwhile, the internal structure of the compound semiconductor is isolated from contacting the outside, and the performance of the compound semiconductor is prevented from being changed due to reaction. SiN is an inorganic substance, is an important structural ceramic material, has high hardness, self lubricity and wear resistance, and is an atomic crystal; is resistant to oxidation at high temperature. It can resist cold and hot impact, and can be heated to above 1000 deg.C in air, and can be rapidly cooled and then rapidly heated, and can not be broken. Therefore, SiN is used as the protective layer 270 and is arranged on the surface of the compound semiconductor, so that the internal structure can be better protected, the service life of the compound semiconductor is prolonged, and the use performance of the compound semiconductor is guaranteed.
The collector layer 230, the base electrode layer 240 and the emitter layer 250 all include a plurality of film layers, and the via 280 can penetrate through any film layer as required to form a conduction channel. Of course, the collector layer 230, the base electrode layer 240 and the emitter layer 250 may have only one film layer to achieve some simple functions.
In this embodiment, the required film layers with various functional characteristics are formed on the substrate 210 in advance, the whole third generation semiconductor 100 is divided into a plurality of blocks 200 by the photolithography and etching process, each block 200 is formed with a via hole 280 penetrating to the corresponding film layer by the photolithography and etching process according to the function to be realized, so as to realize the corresponding function, and thus, each block 200 does not need to be separately manufactured according to the function to be realized; compared with the traditional process, the process for presetting the epitaxial buried layer avoids the influence of signal distortion and more stable work rate output, and is embodied in the wide application of future high-frequency communication and high-energy output devices. In addition, the advantage of etching the third generation semiconductor 100 by photolithography and etching processes is that it can precisely control the shape and size of the formed pattern, and in addition it can simultaneously produce a profile over the entire chip surface.
Further, the third generation compound semiconductor further includes an isolation layer 300, and the isolation layer 300 is disposed between each of the blocks 200 for isolating each of the blocks 200. The insulating layer 300 includes an inert gas such as helium, nitrogen, and the like. The isolation layer 300 is formed by injecting inert gas between each block 200 by high-energy ion implantation, and each block 200 is formed into independent elements without mutual interference by the isolation layer 300, so that various functions can be realized.
Referring to fig. 6, in an embodiment, the electronic characteristic layer further includes a two-dimensional electron gas layer 260 formed on the base electrode layer 240 by epitaxial deposition and located between the base electrode layer 240 and the emitter electrode layer 250. Specifically, the material of the two-dimensional electrical layer comprises aluminum gallium nitride. A two-dimensional electric layer is disposed between the base electrode layer 240 and the emitter electrode layer 250 to improve the mobility of electrons.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; within the idea of the invention, also technical features in the above embodiments or in different embodiments may be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the invention as described above, which are not provided in detail for the sake of brevity; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method of manufacturing a third generation semiconductor, the method comprising the steps of:
providing a substrate;
epitaxially depositing a buffer layer on the substrate;
epitaxially depositing an electronic property layer on the buffer layer;
forming a protective layer on the electronic characteristic layer;
and forming a through hole on the protective layer to penetrate to the electronic characteristic layer.
2. The method of claim 1, wherein the step of epitaxially depositing an electronic properties layer on the buffer layer comprises:
epitaxially depositing a collector layer on the buffer layer;
epitaxially depositing a base electrode layer on the collector layer;
and epitaxially depositing an emitter electrode layer on the base electrode layer.
3. The method of claim 2, wherein the step of epitaxially depositing an electronic properties layer on the buffer layer comprises:
epitaxially depositing an N-type substrate with a first ion concentration on the buffer layer to form a collector layer;
epitaxially depositing a P-type substrate on the collector layer to form a base electrode layer;
epitaxially depositing an N-type substrate with a second ion concentration on the base electrode layer to form an emitter electrode layer;
wherein the first ion concentration is less than the second ion concentration.
4. The method of manufacturing a third generation semiconductor according to claim 1, further comprising the steps of:
the third generation semiconductor is divided into a plurality of blocks.
5. The method of manufacturing a third generation semiconductor according to claim 4, wherein the step of dividing the third generation semiconductor into a plurality of blocks comprises:
the third generation semiconductor is divided into blocks by photolithography and/or etching.
6. The method of manufacturing a third generation semiconductor according to claim 5, wherein the step of dividing the third generation semiconductor into a plurality of blocks by photolithography and/or etching further comprises:
and injecting inert gas in a photoetching or etched space by a high-energy ion injection mode.
7. The method of claim 1, wherein the electronic property layer is deposited in a single lattice.
8. The method for manufacturing a compound semiconductor according to claim 1, wherein the step of forming a via hole in the protective layer penetrating to the electronic characteristic layer comprises:
and forming a through hole penetrating to the electronic characteristic layer on the protective layer by photoetching and/or etching.
9. The method for manufacturing a compound semiconductor according to claim 1, wherein the step of forming a protective layer over the electronic characteristic layer comprises:
and forming a protective layer on the electronic characteristic layer by chemical vapor deposition.
10. The method of claim 1, wherein the step of epitaxially depositing an electronic properties layer on the buffer layer comprises:
epitaxially depositing a collector layer on the buffer layer;
epitaxially depositing a base electrode layer on the collector layer;
epitaxially depositing a two-dimensional electrical layer on the base electrode layer;
and epitaxially depositing an emitter electrode layer on the two-dimensional electrical layer.
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