CN113676184A - Successive approximation analog-digital converter switching method based on semi-dormant structure - Google Patents

Abstract

The invention discloses a switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure, which comprises the following steps: for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison of an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion; in the sampling stage, input signals VIP and VIN are connected to top electrode plates of upper and lower capacitor arrays of the two sub analog-to-digital converters through sampling switches, and bottom electrode plates of each capacitor are connected to corresponding voltages; in the conversion stage, the comparator compares MSB bit to LSB bit of the top plate voltage of the upper and lower capacitor arrays to obtain corresponding digital codes to control the state of the bottom plate of each capacitor; obtaining N-bit digital code through N times of comparison. The invention switches to generate +/-V for the first time_refIs measured by the capacitor array reference voltage V_refReduced to half of the general method(ii) a The power consumption is further reduced by multiple times of merging operation during switching; only the LSB bits introduce a common mode level offset of 0.5 LSB.

Description

Successive approximation analog-digital converter switching method based on semi-dormant structure

Technical Field

The invention relates to a switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure, and belongs to the field of low-power-consumption charge redistribution type SAR ADCs.

Background

With the development of internet of things (IoT) technology, the service life requirements of sensors on nodes of the internet of things are increasing, and thus more strict requirements are placed on the power consumption of analog-to-digital converters in the sensing devices. The SAR ADC has the advantages of simple structure, high energy efficiency, high digitalization, and wide application in medical monitoring, mobile equipment, wearable equipment and other occasions, and the SAR ADC has medium precision (8-12bits) and medium sampling rate (1-1000 kS/s).

Currently, charge redistribution DACs are the dominant direction of SAR ADCs. The purpose of successive approximation is achieved by changing the reference voltage connected with the bottom plate of the capacitor array. Under low voltage, dynamic switching power consumption generated by CDAC capacitance switching accounts for a large part of the whole ADC, so that various research teams at home and abroad make much effort in the direction and provide many energy-efficient switching algorithms. However, they introduce multiple levels, common mode level drift [1], or complex control logic [3], etc., while reducing the power consumption of the CDAC, and even face practical problems, and finally, reduce the power consumption of the CDAC while increasing the power consumption of other modules. Therefore, these switching algorithms are not effective in improving the overall energy efficiency of the SAR ADC. The invention designs a successive approximation analog-digital converter switching method based on a semi-dormant structure based on the structure of [2 ].

[1]Z.Zhu et al.:‘A 0.6-V 38-nW 9.4-ENOB 20-kS/s SAR ADC in 0.18-CMOS for medical implant devices’,IEEE Transactions on Circuits and Systems-I.,2015,62,(9),pp.2167-2176

[2]S.-E.Hsieh and C.-C.Hsieh.:‘A 0.44-fJ/conversion-step 11-bit 600-kS/s SAR ADC with semi-resting DAC’,IEEE Journal of Solid-State Circuits.,2018,53,(9),pp.2595-2603

[3]C.H.Kuo and C.E.Hsieh.:‘Floating capacitor switching SAR ADC’.Electronics Letters,2011,47，(13),742-743

Disclosure of Invention

The invention aims to provide a switching method of a successive approximation analog-to-digital converter based on a semi-dormant structure, so that the power consumption of a CDAC is reduced, and simultaneously, the requirement on other modules of the ADC is not too high.

In order to achieve the purpose, the invention adopts the technical scheme that:

a method for switching a successive approximation analog-to-digital converter based on a semi-dormant structure is characterized in that the analog-to-digital converter based on the method comprises two same sub analog-to-digital converters (ADC)₁And ADC₀Each sub-analog-to-digital converter comprises a sampling switch, a capacitor array, a comparator and digital control logic, wherein the capacitor array comprises identical upper capacitor array DACs_P1、DAC_N1And lower capacitor array DAC_P0、DAC_N0(ii) a The input signal VIP is connected to the DAC through the sampling switch_P1And DAC_P0The input signal VIN is connected to the DAC through the sampling switch_N1And DAC_N0The top plate of (1); DAC_P1And DAC_P0The top plate of the DAC is connected with the non-inverting input end of the comparator_N1And DAC_N0The top plate of the comparator is connected with the inverting input end of the comparator, and the differential output end of the comparator generates a control signal to control the bottom plate switches of the upper capacitor array and the lower capacitor array through digital control logic, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding voltages, combined, split or floated;

each sub-capacitor array is composed of a highest-order capacitor C_N-4And N-6 high-order capacitors and sub-low-order capacitors C₁Lowest order capacitor C₀And dummy capacitor C_dThe capacitor comprises the following capacitors: c_i＝2ⁱC, wherein i is more than or equal to 0 and less than or equal to N-4, and dummy capacitor C_dC, where N denotes the number of bits of the analog-to-digital converter and C is the unit capacitance size;

the method comprises the following steps: for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison of an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion; in the sampling stage, input signals VIP and VIN are connected to top electrode plates of upper and lower capacitor arrays of the two sub analog-to-digital converters through sampling switches, and bottom electrode plates of each capacitor are connected to corresponding voltages; in the conversion stage, the comparator compares MSB bit to LSB bit of the top plate voltage of the upper and lower capacitor arrays to obtain corresponding digital codes to control the state of the bottom plate of each capacitor; obtaining N-bit digital code through N times of comparison.

The sampling phase comprises the following steps:

input signals VIP and VIN are respectively connected to the ADC through sampling switches₁And ADC₀Top plate of capacitor array, ADC₁Sub-capacitor array DAC_P1All capacitor bottom plates of (2) are connected to V_refReference voltage, and sub-capacitor array DAC_N1All capacitor bottom plates of gnd are connected to gnd; ADC (analog to digital converter)₀Sub-capacitor array DAC_P0All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC_N0All capacitor bottom plates of (2) are connected to V_refA reference voltage.

The transition phase comprises the steps of:

step B1, the sampling switch of the analog-to-digital converter is turned off, then the comparator directly compares the input signals VIP and VIN held on the top plates of the upper capacitor array and the lower capacitor array to obtain the most significant bit D_N-1According to digital code D_N-1Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;

step B2, the comparator compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D_N-2According to digital code D_N-1And D_N-2Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;

step B3, the comparator compares the voltage of the top electrode plate of the upper capacitor array and the voltage of the bottom electrode plate of the lower capacitor array obtained from the step B2 to obtain a digital code D_KWhere K is greater than or equal to 1 and less than or equal to N-3, according to the digital code D_N-1And D_N-2And D_KControlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until the digital code D is obtained₁；

Step B4, according to the digital code D_N-1And D₁Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays, and comparing the voltages of the top plates of the upper and lower capacitor arrays by the comparator to obtainDigital code D₀。

In the step B1, according to the digital code D_N-1The control of the connection relation of the capacitor bottom plates in the upper and lower capacitor arrays is specifically as follows:

the first condition is as follows: if D is_N-1＝1，ADC₀The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₀Performing other operations, DAC_P1And DAC_N1All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V_ref；

Case two: if D is_N-1＝0，ADC₁The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₁Performing other operations, DAC_P0And DAC_N0All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is increased by V_ref。

In the step B2, according to the digital code D_N-1And D_N-2The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:

the first condition is as follows: if D is_N-1D_N-2＝11，DAC_P1All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V_ref；

Case two: if D is_N-1D_N-2＝10，DAC_P1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N1All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref；

Case three: if D is_N-1D_N-2＝01，DAC_P0All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N0All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V_ref；

Case four: if D is_N-1D_N-2＝00，DAC_P0All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N0All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref。

In the step B3, according to the digital code D_N-1、D_N-2And D_KThe method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:

the first condition is as follows: if D is_N-1D_N-2D_K＝111，DAC_P1C of (A)_K-1The capacitor being connected to gnd, DAC_N1C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case two: if D is_N-1D_N-2D_K＝110，DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case three: if D is_N-1D_N-2D_K＝101，DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case four: if D is_N-1D_N-2D_K＝100，DAC_P1C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_N1C of (A)_K-1The capacitor being connected to gnd, DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case five: if D is_N-1D_N-2D_K＝011，DAC_P0C of (A)_K-1The capacitor being connected to gnd, DAC_N0C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case six: if D is_N-1D_N-2D_K＝010，DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case seven: if D is_N-1D_N-2D_K＝001，DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case eight: if D is_N-1D_N-2D_K＝000，DAC_P0C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_N0C of (A)_K-1The capacitor being connected to gnd, DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Wherein N is the digit of the analog-to-digital converter, K is the ordinal number of the currently obtained digital code, and K is more than or equal to 1 and less than or equal to N-3, that is, D is obtained in sequence from high to low in step B4_N-3To D₁And a plurality of digital codes.

In the step B4, according to the digital code D_N-1And D₁The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:

the first condition is as follows: if D is_N-1D₁＝11，DAC_P1Capacitor C of₁Uncombined and connected to gnd, DAC_N1Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(2-N)V_ref；

Case two: if D is_N-1D₁＝10，DAC_P1Capacitor C of₁From a merged state to a floating state, DAC_N1Capacitor C of₁Uncombined and connected to gnd, so that the wholeThe differential voltage of the DAC will be increased by 2^(2-N)V_ref；

Case three: if D is_N-1D₁＝01，DAC_P0Capacitor C of₁Uncombined and connected to gnd, DAC_N0Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(2-N)V_ref；

Case four: if D is_N-1D₁＝00，DAC_P0Capacitor C of₁From a merged state to a floating state, DAC_N0Capacitor C of₁Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2^(2-N)V_ref；

Wherein N is the number of bits of the analog-to-digital converter. Has the advantages that: by adopting the technical scheme, the invention can produce the following technical effects:

the method for switching the successive approximation analog-to-digital converter based on the semi-dormant structure provided by the invention generates +/-V on the top plate of the capacitor by switching for the first time_refThus, the reference voltage V of the capacitor array under the same range condition_refThe range of the ADC can be expanded to twice of the normal range under the same reference voltage, and almost every step of switching in the switching process is combined, so that the power consumption of the DAC is further reduced; and a single-end switching algorithm is adopted only in the judgment of the last bit, so that the area of the capacitor is saved, and the common-mode level drift is reduced. Compared with the traditional switching algorithm, the invention reduces 99.22% of the power consumption of the capacitor DAC, saves 75% of the capacitor area, does not improve the requirements on other modules, and improves the integral energy efficiency of the SAR ADC.

Drawings

Fig. 1 is a schematic structural diagram of an SAR ADC used for realizing 10-bit resolution by the method of the present invention.

Fig. 2 is a schematic diagram of the switching of the 5-bit SAR ADC according to the present invention.

Fig. 3 is a diagram of the results of MATLAB simulation of the switching power consumption of a 10-bit SAR ADC as a function of the ADC output code (for comparison, V in the diagram is the CDAC reference voltage of most switching algorithms including the split-monotonic switching algorithm).

Detailed Description

The present invention will be further described with reference to the accompanying drawings.

The structure of a 10-bit successive approximation type analog-to-digital converter based on the method is shown in figure 1, and the method comprises two same sub analog-to-digital converters ADC₁And ADC₀Each sub-adc comprises a sampling switch 1, a capacitor array 2, a comparator 3 and digital control logic 4, wherein the capacitor array 2 comprises identical upper capacitor array DACs_P1、DAC_N1And lower capacitor array DAC_P0、DAC_N0(ii) a The input signal VIP is connected to the DAC through the sampling switch 1_P1And DAC_P0The input signal VIN is connected to the DAC through the sampling switch 1_N1And DAC_N0The top plate of (1); DAC_P1And DAC_P0The top plate of the DAC is connected with the non-inverting input end of the comparator_N1And DAC_N0The top plate of the comparator 3 is connected with the inverting input end of the comparator 3, and the differential output end of the comparator 3 generates a control signal to control the bottom plate switches of the upper capacitor array and the lower capacitor array through the digital control logic 4, so that the bottom plates of the upper capacitor array and the lower capacitor array are connected to corresponding voltages, combined, split or floated;

each sub-capacitor array is composed of a highest-order capacitor C_N-4And N-6 high-order capacitors and sub-low-order capacitors C₁Lowest order capacitor C₀And dummy capacitor C_dThe capacitor comprises the following capacitors: c_i＝2ⁱC, wherein i is more than or equal to 0 and less than or equal to N-4, and dummy capacitor C_dC, where N denotes the number of bits of the analog-to-digital converter and C is the unit capacitance size;

for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison by an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion, specifically as follows:

step A, sampling stage

Input signals VIP and VIN pass through sampling switchAre respectively connected to the ADC₁And ADC₀Top plate of capacitor array, ADC₁Sub-capacitor array DAC_P1All capacitor bottom plates of (2) are connected to V_refReference voltage, and sub-capacitor array DAC_N1All capacitor bottom plates of gnd are connected to gnd; ADC (analog to digital converter)₀Sub-capacitor array DAC_P0All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC_N0All capacitor bottom plates of (2) are connected to V_refA reference voltage;

step B, transition phase

Step B1, the sampling switch of the analog-to-digital converter is turned off, then the comparator directly compares the input signals VIP and VIN held on the top plates of the upper capacitor array and the lower capacitor array to obtain the most significant bit D_N-1According to digital code D_N-1Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;

the first condition is as follows: if D is_N-1＝1，ADC₀The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₀Performing other operations, DAC_P1And DAC_N1All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V_ref；

Case two: if D is_N-1＝0，ADC₁The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₁Performing other operations, DAC_P0And DAC_N0All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is increased by V_ref。

Step B2, the comparator 3 compares the voltages of the top plates of the upper and lower capacitor arrays obtained from step B1 to obtain a digital code D_N-2According to digital code D_N-1D_N-2Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays;

the first condition is as follows: if D is_N-1D_N-2＝11，DAC_P1All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, such as difference of whole DACThe voltage will be reduced by 0.5V_ref；

Case two: if D is_N-1D_N-2＝10，DAC_P1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N1All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref；

Case three: if D is_N-1D_N-2＝01，DAC_P0All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N0All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V_ref；

Case four: if D is_N-1D_N-2＝00，DAC_P0All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N0All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref。

Step B3, the comparator compares the voltage of the top electrode plate of the upper capacitor array and the voltage of the bottom electrode plate of the lower capacitor array obtained from the step B2 to obtain a digital code D_KWhere K is greater than or equal to 1 and less than or equal to N-3, according to the digital code D_N-1And D_N-2And D_KControlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until the digital code D is obtained₁；

The first condition is as follows: if D is_N-1D_N-2D_K＝111，DAC_P1C of (A)_K-1The capacitor being connected to gnd, DAC_N1C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case two: if D is_N-1D_N-2D_K＝110，DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased2^(K-N+1)V_ref；

Case three: if D is_N-1D_N-2D_K＝101，DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case four: if D is_N-1D_N-2D_K＝100，DAC_P1C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_N1C of (A)_K-1The capacitor being connected to gnd, DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case five: if D is_N-1D_N-2D_K＝011，DAC_P0C of (A)_K-1The capacitor being connected to gnd, DAC_N0C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case six: if D is_N-1D_N-2D_K＝010，DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case seven: if D is_N-1D_N-2D_K＝001，DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case eight: if D is_N-1D_N-2D_K＝000，DAC_P0C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_N0C of (A)_K-1The capacitor being connected to gnd, DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Wherein N is the digit of the analog-to-digital converter, K is the ordinal number of the currently obtained digital code, and K is more than or equal to 1 and less than or equal to N-3, that is, D is obtained in sequence from high to low in step B4_N-3To D₁And a plurality of digital codes.

Step B4, according to the digital code D_N-1And D₁Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays, and comparing the voltages of the top plates of the upper and lower capacitor arrays by the comparator to obtain a digital code D₀。

The first condition is as follows: if D is_N-1D₁＝11，DAC_P1Capacitor C of₁Uncombined and connected to gnd, DAC_N1Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(2-N)V_ref；

Case two: if D is_N-1D₁＝10，DAC_P1Capacitor C of₁From a merged state to a floating state, DAC_N1Capacitor C of₁Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2^(2-N)V_ref；

Case three: if D is_N-1D₁＝01，DAC_P0Capacitor C of₁Uncombined and connected to gnd, DAC_N0Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(2-N)V_ref；

Case four: if D is_N-1D₁＝00，DAC_P0Capacitor C of₁From a merged state to a floating state, DAC_N0Capacitor C of₁Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2^(2-N)V_ref；

Wherein N is the number of bits of the analog-to-digital converter.

The differential output end of the comparator generates a control signal to control the bottom plate switches of the upper and lower capacitor arrays after passing through the digital control logic, so that the bottom plate switches are connected to corresponding reference voltages, combined, split and floated. Through the special construction of the core module capacitor array and the combination of the provided novel switching algorithm, the power consumption of the DAC part in the conversion process can be greatly reduced, the capacitor area is saved, and the common mode level drift is reduced.

The invention will now be described in more detail with reference to an example, since D _N-11 and D_N-1In both cases 0, the MSB to LSB bit quantization process is completely symmetrical, and to avoid redundant description, D is set_N-1Fig. 2 shows a specific conversion process of a 5-bit SAR ADC according to an embodiment of the present invention:

step A, sampling stage

Input signals VIP and VIN are respectively connected to the top plates of ADC1 and ADC0 capacitor arrays through sampling switches, and sub-capacitor array DAC of ADC1_P1All capacitor bottom plates of (2) are connected to V_refReference voltage, and sub-capacitor array DAC_N1All capacitor bottom plates of gnd are connected to gnd; sub-capacitor array DAC of ADC0_P0All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC_N0All capacitor bottom plates of (2) are connected to V_refA reference voltage;

step B, transition phase

Step B1, the sampling switch of the A/D converter is turned off, then the comparator directly compares the input signals VIP and VIN held on the top plates of the upper and lower capacitor arrays to obtain the digital code D₄According to digital code D₄Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays;

due to D₄＝1，ADC₀The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₀Performing other operations, DAC_P1And DAC_N1All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V_ref；

Step B2, the comparator compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D₄According to digital code D₄D₃Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays;

the first condition is as follows: if D is₄D₃＝11，DAC_P1All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V_ref；

Case two: if D is₄D₃＝10，DAC_P1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N1All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref；

Step B3, the comparator compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B2 to obtain a digital code D_KWhere K is greater than or equal to 1 and less than or equal to 2, according to the digital code D₄D₃And D_KControlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until the digital code D is obtained₁；

The first condition is as follows: if D is₄D₃D₂＝111，DAC_P1C of (A)₁The capacitor being connected to gnd, DAC_N1C of (A)₁The capacitor is connected to V_refReference voltage, DAC_P1C of (A)₀Capacitor and DAC_N1C of (A)₀The capacitors are combined, so that the differential voltage of the whole DAC is reduced by 0.25V_ref；

Case two: if D is₄D₃D₂＝110，DAC_P1C of (A)₀Capacitor and DAC_N1C of (A)₀The capacitors are combined, so that the differential voltage of the whole DAC is increased by 0.25V_ref；

Case three: if D is₄D₃D₂＝101，DAC_P1C of (A)₀Capacitor and DAC_N1C of (A)₀The capacitors are combined, so that the differential voltage of the whole DAC is reduced by 0.25V_ref；

Case four: if D is₄D₃D₂＝100，DAC_P1C of (A)₁The capacitor is connected to V_refReference voltage, DAC_N1C of (A)₁The capacitor being connected to gnd, DAC_P1C of (A)₀Capacitor and DAC_N1C of (A)₀The capacitors are combined, so that the differential voltage of the whole DAC is increased by 0.25V_ref；

Step B4, according to the digital code D₄And D₁Controlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays, and comparing the voltages of the top plates of the upper and lower capacitor arrays by the comparator to obtain a digital code D₀。

The first condition is as follows: if D is₄D₁＝11，DAC_P1Capacitor C of₁Uncombined and connected to gnd, DAC_N1Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(-3)V_ref；

Case two: if D is₄D₁＝10，DAC_P1Capacitor C of₁From a merged state to a floating state, DAC_N1Capacitor C of₁Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2^(-3)V_ref；

As shown in fig. 3, the MATLAB simulation result graph is applied to the switching and resetting power consumption of the 10-bit SAR ADC, which varies with the ADC output code, and the invention can reduce 99.22% of the power consumption of the capacitor DAC, save 75% of the capacitor area, not increase the requirements for other modules, and improve the overall energy efficiency of the SAR ADC.

In summary, the method of the present invention utilizes the first switching of V_refThe voltage change and the multiple combined operation reduce the power consumption of the CDAC switch, and improve the integral energy efficiency of the SAR ADC.

The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims (7)

1. A successive approximation analog-to-digital converter switching method based on a semi-dormant structure is characterized in that: the analog-to-digital converter based on the method comprises two identical sub analog-to-digital convertersADC₁And ADC₀Each sub-analog-to-digital converter comprises a sampling switch (1), a capacitor array (2), a comparator (3) and digital control logic (4), wherein the capacitor array (2) comprises identical upper capacitor array DACs_P1、DAC_N1And lower capacitor array DAC_P0、DAC_N0(ii) a The input signal VIP is connected to the DAC via a sampling switch (1)_P1And DAC_P0The input signal VIN is connected to the DAC through the sampling switch (1)_N1And DAC_N0The top plate of (1); DAC_P1And DAC_P0The top plate of the DAC is connected with the non-inverting input end of the comparator (3)_N1And DAC_N0The top pole plate of the capacitor is connected with the inverting input end of the comparator (3), and the differential output end of the comparator (3) generates a control signal to control the bottom pole plate switches of the upper capacitor array and the lower capacitor array through the digital control logic (4), so that the bottom pole plates of the upper capacitor array and the lower capacitor array are connected to corresponding voltages, combined, split or floated;

each sub-capacitor array is composed of a highest-order capacitor C_N-4And N-6 high-order capacitors and sub-low-order capacitors C₁Lowest order capacitor C₀And dummy capacitor C_dThe capacitor comprises the following capacitors: c_i＝2ⁱC, wherein i is more than or equal to 0 and less than or equal to N-4, and dummy capacitor C_dC, where N denotes the number of bits of the analog-to-digital converter and C is the unit capacitance size;

the method comprises the following steps: for input signals VIP and VIN, N-bit digital output codes are obtained after N times of comparison of an analog-to-digital converter, and the N-bit digital output codes are divided into two stages of sampling and conversion; in the sampling stage, input signals VIP and VIN are connected to top electrode plates of upper and lower capacitor arrays of the two sub analog-to-digital converters through sampling switches, and bottom electrode plates of each capacitor are connected to corresponding voltages; in the conversion stage, the comparator compares MSB bit to LSB bit of the top plate voltage of the upper and lower capacitor arrays to obtain corresponding digital codes to control the state of the bottom plate of each capacitor; obtaining N-bit digital code through N times of comparison.

2. The method of claim 1, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: the sampling phase comprises the following steps:

input signals VIP and VIN are respectively connected to the ADC through a sampling switch (1)₁And ADC₀Top plate of capacitor array, ADC₁Sub-capacitor array DAC_P1All capacitor bottom plates of (2) are connected to V_refReference voltage, and sub-capacitor array DAC_N1All capacitor bottom plates of gnd are connected to gnd; ADC (analog to digital converter)₀Sub-capacitor array DAC_P0All capacitor bottom plates of (2) are connected to gnd, and the sub-capacitor array DAC_N0All capacitor bottom plates of (2) are connected to V_refA reference voltage.

3. The method of claim 1, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: the transition phase comprises the steps of:

step B1, the sampling switch (1) of the analog-to-digital converter is switched off, then the comparator (3) directly compares the input signals VIP and VIN held at the top plates of the upper capacitor array and the lower capacitor array to obtain the most significant bit D_N-1According to digital code D_N-1Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;

step B2, the comparator (3) compares the voltages of the top plates of the upper and lower capacitor arrays obtained in the step B1 to obtain a digital code D_N-2According to digital code D_N-1And D_N-2Controlling the connection relation of the capacitor bottom plates in the upper capacitor array and the lower capacitor array so as to obtain a new top plate voltage;

step B3, the comparator (3) compares the top plate voltage of the upper capacitor array and the bottom capacitor array obtained from step B2 to obtain the digital code D_KWhere K is greater than or equal to 1 and less than or equal to N-3, according to the digital code D_N-1And D_N-2And D_KControlling the connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays; and repeating the step B4 until the digital code D is obtained₁；

Step B4, according to the digital code D_N-1And D₁The connection relation of the bottom plates of the capacitors in the upper and lower capacitor arrays is controlled, and the comparator (3) compares the currentThe voltage of the top plate of the upper and lower capacitor arrays is obtained to obtain a digital code D₀。

4. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in the step B1, according to the digital code D_N-1The control of the connection relation of the capacitor bottom plates in the upper and lower capacitor arrays is specifically as follows:

the first condition is as follows: if D is_N-1＝1，ADC₀The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₀Performing other operations, DAC_P1And DAC_N1All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is reduced by V_ref；

Case two: if D is_N-1＝0，ADC₁The ADC is switched to a dormant state, and the ADC is not switched again in the conversion process₁Performing other operations, DAC_P0And DAC_N0All capacitor bottom plates are combined, so that the differential voltage of the whole DAC is increased by V_ref。

5. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in the step B2, according to the digital code D_N-1And D_N-2The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:

the first condition is as follows: if D is_N-1D_N-2＝11，DAC_P1All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V_ref；

Case two: if D is_N-1D_N-2＝10，DAC_P1All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N1All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref；

Case three: if D is_N-1D_N-2＝01，DAC_P0All but the most significant bit capacitance are connected to gnd by a combination, while the DAC_N0All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, so that the differential voltage of the whole DAC will be reduced by 0.5V_ref；

Case four: if D is_N-1D_N-2＝00，DAC_P0All capacitances except the highest order capacitance are connected by a combination to V_refReference voltage, and DAC_N0All the capacitors except the most significant capacitor are connected to gnd by combination, so that the differential voltage of the whole DAC will be increased by 0.5V_ref。

6. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in the step B3, according to the digital code D_N-1、D_N-2And D_KThe method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:

the first condition is as follows: if D is_N-1D_N-2D_K＝111，DAC_P1C of (A)_K-1The capacitor being connected to gnd, DAC_N1C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case two: if D is_N-1D_N-2D_K＝110，DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case three: if D is_N-1D_N-2D_K＝101，DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case four: if D is_N-1D_N-2D_K＝100，DAC_P1C of (A)_K-1Capacitive connectionTo V_refReference voltage, DAC_N1C of (A)_K-1The capacitor being connected to gnd, DAC_P1C of (A)_K-2Capacitor and DAC_N1C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case five: if D is_N-1D_N-2D_K＝011，DAC_P0C of (A)_K-1The capacitor being connected to gnd, DAC_N0C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case six: if D is_N-1D_N-2D_K＝010，DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Case seven: if D is_N-1D_N-2D_K＝001，DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be reduced by 2^(K-N+1)V_ref；

Case eight: if D is_N-1D_N-2D_K＝000，DAC_P0C of (A)_K-1The capacitor is connected to V_refReference voltage, DAC_N0C of (A)_K-1The capacitor being connected to gnd, DAC_P0C of (A)_K-2Capacitor and DAC_N0C of (A)_K-2The capacitors are combined so that the differential voltage of the whole DAC will be increased by 2^(K-N+1)V_ref；

Wherein N is the digit of the analog-to-digital converter, K is the ordinal number of the currently obtained digital code, and K is more than or equal to 1 and less than or equal to N-3, that is, D is obtained in sequence from high to low in step B4_N-3To D₁And a plurality of digital codes.

7. The method of claim 3, wherein the successive approximation analog-to-digital converter switching method based on the semi-sleep structure comprises: in said step B4, according toDigital code D_N-1And D₁The method comprises the following steps of controlling the connection relation of bottom plates of capacitors in an upper capacitor array and a lower capacitor array, specifically:

the first condition is as follows: if D is_N-1D₁＝11，DAC_P1Capacitor C of₁Uncombined and connected to gnd, DAC_N1Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(2-N)V_ref；

Case two: if D is_N-1D₁＝10，DAC_P1Capacitor C of₁From a merged state to a floating state, DAC_N1Capacitor C of₁Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2^(2-N)V_ref；

Case three: if D is_N-1D₁＝01，DAC_P0Capacitor C of₁Uncombined and connected to gnd, DAC_N0Capacitor C of₁From the merged state to the floating state, so that the differential voltage of the whole DAC is reduced by 2^(2-N)V_ref；

Case four: if D is_N-1D₁＝00，DAC_P0Capacitor C of₁From a merged state to a floating state, DAC_N0Capacitor C of₁Uncombined and connected to gnd so that the differential voltage of the whole DAC will increase by 2^(2-N)V_ref；

Wherein N is the number of bits of the analog-to-digital converter.

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