CN113675057A - Self-aligned graphene field emission gate structure and preparation method thereof - Google Patents
Self-aligned graphene field emission gate structure and preparation method thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J1/00—Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
- H01J1/02—Main electrodes
- H01J1/30—Cold cathodes, e.g. field-emissive cathode
- H01J1/304—Field-emissive cathodes
- H01J1/3042—Field-emissive cathodes microengineered, e.g. Spindt-type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J9/00—Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
- H01J9/02—Manufacture of electrodes or electrode systems
- H01J9/022—Manufacture of electrodes or electrode systems of cold cathodes
- H01J9/025—Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/304—Field emission cathodes
- H01J2201/30403—Field emission cathodes characterised by the emitter shape
- H01J2201/30407—Microengineered point emitters
- H01J2201/30411—Microengineered point emitters conical shaped, e.g. Spindt type
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2201/00—Electrodes common to discharge tubes
- H01J2201/30—Cold cathodes
- H01J2201/304—Field emission cathodes
- H01J2201/30446—Field emission cathodes characterised by the emitter material
- H01J2201/30453—Carbon types
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J2209/00—Apparatus and processes for manufacture of discharge tubes
- H01J2209/02—Manufacture of cathodes
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- H01J2209/0223—Field emission cathodes
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Abstract
The invention relates to a self-aligned graphene field emission gate structure and a preparation method thereof, belonging to the field of vacuum electronic devices, wherein the self-aligned graphene field emission gate structure comprises: a substrate; the insulating layer is deposited on the substrate, and the insulating layer is arranged on the substrate at intervals; a gate electrode is deposited on the insulating layer; the emission cone tip is arranged on the substrate between the insulating layers; the graphene is flatly laid on the grid; one pole of the grid voltage power supply is arranged on the substrate, the other pole of the grid voltage power supply is arranged on the grid electrode, and the grid voltage power supply is used for applying grid voltages with different sizes between the substrate and the grid electrode so as to controllably etch the graphene and form a self-aligned grid electrode hole. A very small grid voltage is applied between the substrate and the grid electrode, a very large enhancement electric field can be formed at the emission cone tip, the number of emitted electrons is changed by changing the size of the grid voltage, so that the upper graphene layer is controllably etched, a self-aligned grid electrode hole is finally formed, the modulation voltage of the grid electrode is greatly reduced, and the electron transmittance is effectively improved.
Description
Technical Field
The invention relates to the field of vacuum electronic devices, in particular to a self-aligned graphene field emission gate structure and a preparation method thereof.
Background
Due to the fact that graphene has ultrahigh carrier mobility and saturation drift velocity, the graphene attracts people's attention in recent years, and is expected to be applied to the fields of future high-speed electrons and radio frequency.
Vacuum electron emission currently takes many forms, such as thermionic emission, field electron emission, photo-induced electron emission, and the like. Electron sources have very important applications in various vacuum electronic devices such as X-ray sources, flat panel displays, electron microscopes, ion thrusters, etc., but these electron emission cathodes have the disadvantages of too low emission efficiency and low electron transmittance, and cannot be applied to the process of performing controlled etching on graphene layers.
As a core electron source of a vacuum electronic device, a Spindt cathode has the advantages of instantaneous start, low power consumption, room-temperature work, high current density and the like, is widely applied to the fields of X-ray tubes, flat panel displays, traveling wave tubes and the like, but no relevant research is available at present for applying the Spindt cathode to a process for carrying out controllable etching on graphene layers.
Therefore, in view of the above problems, a device with a self-aligned graphene field emission gate structure with good control performance is needed.
Disclosure of Invention
The invention aims to provide a self-aligned graphene field emission gate structure and a preparation method thereof, which can greatly reduce gate modulation voltage, effectively improve electron transmittance and carry out controllable etching on graphene.
In order to achieve the purpose, the invention provides the following scheme:
a self-aligned graphene field emission gate structure, comprising:
a substrate;
the insulating layers are deposited on the substrate and are arranged at intervals on the substrate;
a gate electrode deposited on the insulating layer;
the emission cone tip is arranged on the substrate between the insulating layers;
the graphene is flatly paved on the grid electrode;
and one pole of the grid voltage power supply is added on the substrate, the other pole of the grid voltage power supply is added on the grid electrode, and the grid voltage power supply is used for applying grid voltages with different sizes between the substrate and the grid electrode so as to controllably etch the graphene and form a self-aligned grid electrode hole.
Optionally, the emission cone height is less than a total height of the insulating layer and the gate.
Optionally, the material of the insulating layer is any one of the following materials: SiO 22、SiON、Al2O3。
Optionally, the material of the gate is any one of the following materials: molybdenum, niobium, chromium, silicon.
Optionally, the material of the emission cone tip is any one of the following materials: molybdenum, silicon, carbon nanotubes, diamond, silicon carbide.
Optionally, the radius of curvature of the emission cone tip is in a range of 5nm-20 nm.
Optionally, the emission cone tip has a height in the range of 800nm to 1.2 μm.
In order to achieve the above purpose, the invention also provides the following scheme:
a preparation method of a self-aligned graphene field emission gate structure comprises the following steps:
selecting a substrate material and preparing a substrate;
preparing an emission cone tip and an oxide layer corresponding to the emission cone tip on the substrate; a mask layer is arranged on the emission cone tip;
preparing insulating layers on the mask layer and the substrate through chemical vapor deposition or atomic layer deposition;
preparing a gate electrode on the insulating layer by using a thin film deposition method;
removing the oxide layer, the mask layer on the emission cone tip, the insulating layer and the grid by using a wet etching method to obtain a grid structure;
transferring graphene to the surface of the gate structure by wet transfer;
one pole of the grid voltage power supply is arranged on the substrate, and the other pole is arranged on the grid.
Optionally, the preparing an emission cone tip and an oxide layer corresponding to the emission cone tip on the substrate specifically includes:
preparing a mask layer on the substrate by utilizing a thermal oxidation process or a thin film deposition method, wherein the mask layer is used as a mask for subsequent etching of the cone tip;
spin-coating a layer of glue on the surface of the mask layer;
photoetching the photoresist by ultraviolet lithography or electron beam exposure to obtain a mask pattern array, and developing to obtain a pattern area;
etching the mask layer outside the pattern area by a reactive ion etching or inductively coupled plasma etching process;
removing the glue by sequentially adopting acetone and isopropanol to obtain a mask layer pattern array;
etching the mask layer pattern array to obtain a primary cone tip;
and sharpening the primary cone tip by a thermal oxidation process to obtain an emission cone tip and a corresponding oxide layer.
Optionally, the etching the mask layer pattern array to obtain a preliminary cone tip specifically includes:
and etching the mask layer pattern array by adopting a reactive ion etching or inductively coupled plasma etching process to obtain a primary cone tip.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects: the self-aligned graphene field emission gate structure comprises a substrate, an emission cone, an insulating layer, a gate and graphene from bottom to top; one pole of the grid voltage power supply is added on the substrate, the other pole is added on the grid, and a very large enhanced electric field can be formed at the tip by applying a very small grid voltage between the substrate and the grid, so that the emission cone tip emits electrons. The number of emitted electrons is changed by changing the size of the grid voltage, so that the graphene layer above the graphene layer is controllably etched, a self-aligned grid hole is finally formed, the modulation voltage of the grid is greatly reduced, and the electron transmittance is effectively improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
Fig. 1 is a schematic longitudinal cross-sectional view of a self-aligned graphene field emission gate structure according to the present invention;
fig. 2 is a flow chart of a method for fabricating a self-aligned graphene field emission gate structure according to the present invention;
FIG. 3 is a schematic longitudinal cross-sectional view of a mask layer;
FIG. 4 is a schematic longitudinal cross-sectional view of a patterned array of masking layers;
FIG. 5 is a schematic longitudinal cross-sectional view of a prepared cone tip;
FIG. 6 is a schematic longitudinal cross-sectional view of a sharpened tip;
FIG. 7 is a schematic longitudinal cross-sectional view of an insulating layer;
fig. 8 is a longitudinal cross-sectional view of a gate.
FIG. 9 is a schematic longitudinal cross-sectional view of the oxide layer, the mask layer on the emission cone tip, the insulating layer and the gate electrode removed;
FIG. 10 is a schematic longitudinal cross-sectional view after transferring and etching graphene;
fig. 11 is a SEM image of a scanning electron microscope of an embodiment of an emission cone tip.
Description of the symbols:
the manufacturing method comprises the following steps of 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 parts of a substrate, an insulating layer, a grid electrode, an emission cone tip, a graphene, a grid voltage power supply, a mask layer, an adhesive, a primary cone tip and an oxide layer.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a self-aligned graphene field emission gate structure, which comprises a substrate, an emission cone, an insulating layer, a gate and graphene from bottom to top; one pole of the grid voltage power supply is added on the substrate, the other pole is added on the grid, and a very large enhanced electric field can be formed at the tip by applying a very small grid voltage between the substrate and the grid, so that the emission cone tip emits electrons. The number of emitted electrons is changed by changing the size of the grid voltage, so that the graphene layer above the graphene layer is controllably etched, a self-aligned grid hole is finally formed, the modulation voltage of the grid is greatly reduced, and the electron transmittance is effectively improved.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
As shown in fig. 1, the self-aligned graphene field emission gate structure of the present invention includes: the device comprises a substrate 1, an insulating layer 2, a grid 3, an emission cone tip 4, graphene 5 and a grid voltage power supply 6.
Wherein, the insulating layer 2 is deposited on the substrate 1, and the insulating layer 2 is arranged on the substrate 1 at intervals. The insulating layer 2 is made of a material with a high dielectric constant. The material of the insulating layer 2 is any one of the following materials: SiO 22、SiON、Al2O3But is not limited thereto. The thickness of the insulating layer 2 ranges from 800nm to 1.2 μm.
In this embodiment, the substrate 1 is a silicon wafer, and the thickness of the substrate 1 is 500 um.
The gate 3 is deposited on the insulating layer 2. The material of the grid 3 is any one of the following materials: molybdenum, niobium, chromium, silicon, but not limited thereto. The thickness range of the gate 3 is 200nm-400 nm.
The emission cone tips 4 are arranged on the substrate 1 between the insulating layers 2. The material of the emission cone tip 4 is any one of the following materials: molybdenum, silicon, carbon nanotubes, diamond, silicon carbide, but not limited thereto. The curvature radius range of the emission cone tip 4 is 5nm-20 nm. The height range of the emission cone tip 4 is 800nm-1.2 μm.
In the present embodiment, the emission cone tip 4 is a silicon tip.
Preferably, the emission tip cone is obtained by an etching process. The height of the emission cone 4 is smaller than and close to the total height of the insulating layer 2 and the gate 3.
The graphene 5 is tiled on the gate 3.
One pole of the grid voltage power supply 6 is arranged on the substrate 1, the other pole of the grid voltage power supply 6 is arranged on the grid electrode 3, the grid voltage power supply 6 is used for applying grid voltages with different sizes between the substrate 1 and the grid electrode 3, and then the graphene 5 is subjected to controllable etching to form a self-aligned grid electrode hole.
Due to the small tip radius of the emission cone 4, a very large enhancement electric field can be formed at the tip of the emission cone 4 by applying a very small gate voltage between the substrate 1 and the gate 3, so that the emission cone 4 emits electrons.
Furthermore, the number of electrons reaching the graphene 5 at the emission cone tip 4 is changed by changing the gate voltage, so that the graphene 5 above is controllably etched, and finally, a self-aligned gate hole is formed, so that the modulation voltage of the gate 3 can be greatly reduced, and the electron transmittance is effectively improved.
As shown in fig. 2, the method for preparing the self-aligned graphene field emission gate structure of the present invention includes:
s1: a substrate material is selected and a substrate 1 is prepared. In the present embodiment, the material of the substrate 1 is silicon. For ease of processing, the substrate 1 is cut into 1cm by 1cm square pieces.
S2: and preparing an emission cone tip 4 and an oxide layer 10 corresponding to the emission cone tip 4 on the substrate 1. As shown in fig. 3, a mask layer 7 is disposed on the emission cone 4. In particular, the height of the emission cone 4 and the tip radius of curvature are mainly determined by etching parameters. Such as gas flow, pressure, etch time, temperature.
S3: as shown in fig. 7, an insulating layer 2 is prepared on the mask layer 7 and on the substrate 1 by chemical vapor deposition or atomic layer deposition. In this embodiment, the material of the insulating layer 2 is SiO2。
S4: as shown in fig. 8, a gate electrode 3 is prepared on the insulating layer 2 using a thin film deposition method. Specifically, the gate electrode 3 may be prepared on the insulating layer 2 using an electron beam evaporation, magnetron sputtering, or chemical vapor deposition process. In the present embodiment, the material of the gate electrode 3 is niobium Nb.
To match the height of the emission cone 4, SiO2The thickness of the insulating layer is 800nm-1.2 μm, and the thickness of the gate Nb is 200nm-400 nm.
S5: as shown in fig. 9, the oxide layer 10, the mask layer 7 on the emission cone 4, the insulating layer 2 and the gate 3 are removed by a wet etching method, so as to obtain a gate structure. Specifically, the insulating layer 2 and the gate electrode 3 may be removed using hydrofluoric acid or a buffer solution of hydrofluoric acid.
As shown in fig. 11, which is an SEM image of a specific example of an emission cone tip, in this embodiment, a mask layer is etched by using a buffered solution BOE of hydrofluoric acid, so as to obtain a Spindt-type emission cone tip array structure. In order to prevent the insulating layer from being excessively corroded, the corrosion time needs to be precisely controlled.
S6: as shown in fig. 10, graphene 5 is transferred to the surface of the gate 3 structure by wet transfer.
S7: one pole of a gate voltage source 6 is provided on the substrate 1 and the other pole is provided on the gate 3.
Preferably, the insulating layer 2 and the gate electrode 3 are prepared to a thickness matched to the height of the emission cone 4. I.e. the sum of the thicknesses of the insulating layer 2 and the gate 3 is greater than or equal to the height of the emission cone 4 to facilitate the transfer of the graphene 5.
Further, S2: preparing an emission cone tip 4 and an oxide layer 10 corresponding to the emission cone tip 4 on the substrate 1, specifically including:
s21: and preparing a mask layer on the substrate 1 by utilizing a thermal oxidation process or a thin film deposition method to be used as a mask for subsequently etching the cone tip. Specifically, the mask layer 7 may be prepared using magnetron sputtering, electron beam evaporation, atomic layer deposition, molecular beam epitaxy, or chemical vapor deposition processes. The mask layer 7 is made of SiO2Or SiN, but not limited thereto. The thickness of the mask layer 7 ranges from 50nm to 1um, in this embodiment 300 nm.
S22: as shown in fig. 4 (a), a layer of glue 8 is spin-coated on the surface of the mask layer. Specifically, a layer of photoresist or electron beam resist is spin coated on the surface of the mask layer.
S23: as shown in fig. 4 (b), the resist 8 is subjected to photolithography by ultraviolet lithography or electron beam exposure to obtain a mask pattern array, and the mask pattern array is developed to obtain a pattern region. In this embodiment, the photoresist used for preparing the mask pattern array by uv lithography is SUN-9i, and the photoresist used for preparing the mask pattern array by electron beam exposure is HSQ, but the invention is not limited to these two types of photoresists.
S24: as shown in part (c) of fig. 4, the mask layer outside the pattern region is etched by a reactive ion etching or inductively coupled plasma etching process.
S25: as shown in fig. 4 (d), the glue 8 is removed by acetone and isopropanol, thereby obtaining a mask layer pattern array. Specifically, the mask layer 7 pattern array is periodically arranged, and can be square or circular, the diameter or side length is 1.5um, and the interval is 10 um.
S26: as shown in fig. 5, the mask layer pattern array is etched to obtain a preliminary taper 9. Specifically, a reactive ion etching or inductively coupled plasma etching process is used to etch the mask layer pattern array, so as to obtain a preliminary cone tip 9. Specifically, the height and radius of curvature of the cone tip are determined by the etching parameters. Such as gas flow, pressure, etch time, temperature.
S27: as shown in fig. 6, the primary cone tip 9 is sharpened by a thermal oxidation process to obtain the emission cone tip 4 and the corresponding oxide layer 10. The radius of the emission cone tip 4 is between 5 and 20 nm.
Further, when the preliminary cone tip 9 is sharpened by a thermal oxidation process, an oxide layer 10 is formed corresponding to the emission cone tip 4. The thickness of the oxide layer 10 is determined by the thermal oxidation temperature and the oxidation time, and the thickness of the oxide layer 10 ranges from 100nm to 200 nm. In the present embodiment, the thickness of the oxide layer 10 ranges from 50nm to 1 um.
Compared with the prior art, the preparation method of the self-aligned graphene field emission gate structure has the same beneficial effects as the self-aligned graphene field emission gate structure, and details are not repeated herein.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.
The principles and embodiments of the present invention have been described herein using specific examples, which are provided only to help understand the method and the core concept of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (10)
1. A self-aligned graphene field emission gate structure, comprising:
a substrate;
the insulating layers are deposited on the substrate and are arranged at intervals on the substrate;
a gate electrode deposited on the insulating layer;
the emission cone tip is arranged on the substrate between the insulating layers;
the graphene is flatly paved on the grid electrode;
and one pole of the grid voltage power supply is added on the substrate, the other pole of the grid voltage power supply is added on the grid electrode, and the grid voltage power supply is used for applying grid voltages with different sizes between the substrate and the grid electrode so as to controllably etch the graphene and form a self-aligned grid electrode hole.
2. The self-aligned graphene field emission gate structure of claim 1, wherein the emission cone height is less than the total height of the insulating layer and the gate.
3. The self-aligned graphene field emission gate structure of claim 1, wherein the material of the insulating layer is any one of the following materials: SiO 22、SiON、Al2O3。
4. The self-aligned graphene field emission gate structure of claim 1, wherein the gate material is any one of the following materials: molybdenum, niobium, chromium, silicon.
5. The self-aligned graphene field emission gate structure of claim 1, wherein the material of the emission cone tip is any one of the following materials: molybdenum, silicon, carbon nanotubes, diamond, silicon carbide.
6. The self-aligned graphene field emission gate structure of claim 1, wherein the radius of curvature of the emission cone tip is in the range of 5nm-20 nm.
7. The self-aligned graphene field emission gate structure of claim 1, wherein the emission cone tip has a height in the range of 800nm-1.2 μ ι η.
8. A preparation method of a self-aligned graphene field emission gate structure is characterized by comprising the following steps:
selecting a substrate material and preparing a substrate;
preparing an emission cone tip and an oxide layer corresponding to the emission cone tip on the substrate; a mask layer is arranged on the emission cone tip;
preparing insulating layers on the mask layer and the substrate through chemical vapor deposition or atomic layer deposition;
preparing a gate electrode on the insulating layer by using a thin film deposition method;
removing the oxide layer, the mask layer on the emission cone tip, the insulating layer and the grid by using a wet etching method to obtain a grid structure;
transferring graphene to the surface of the gate structure by wet transfer;
one pole of the grid voltage power supply is arranged on the substrate, and the other pole is arranged on the grid.
9. The method according to claim 8, wherein the step of preparing the emission cone tip and the oxide layer corresponding to the emission cone tip on the substrate comprises:
preparing a mask layer on the substrate by utilizing a thermal oxidation process or a thin film deposition method, wherein the mask layer is used as a mask for subsequent etching of the cone tip;
spin-coating a layer of glue on the surface of the mask layer;
photoetching the photoresist by ultraviolet lithography or electron beam exposure to obtain a mask pattern array, and developing to obtain a pattern area;
etching the mask layer outside the pattern area by a reactive ion etching or inductively coupled plasma etching process;
removing the glue by sequentially adopting acetone and isopropanol to obtain a mask layer pattern array;
etching the mask layer pattern array to obtain a primary cone tip;
and sharpening the primary cone tip by a thermal oxidation process to obtain an emission cone tip and a corresponding oxide layer.
10. The method for manufacturing a self-aligned graphene field emission gate structure according to claim 9, wherein the etching the mask layer pattern array to obtain a preliminary taper specifically comprises:
and etching the mask layer pattern array by adopting a reactive ion etching or inductively coupled plasma etching process to obtain a primary cone tip.
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| CN202110793595.0A CN113675057B (en) | 2021-07-12 | 2021-07-12 | Self-aligned graphene field emission grid structure and preparation method thereof |
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| CN202110793595.0A CN113675057B (en) | 2021-07-12 | 2021-07-12 | Self-aligned graphene field emission grid structure and preparation method thereof |
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| CN113675057A true CN113675057A (en) | 2021-11-19 |
| CN113675057B CN113675057B (en) | 2023-11-03 |
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