CN113656343A

CN113656343A - On-site programmable gate array circuit, data transmission method, chip and system

Info

Publication number: CN113656343A
Application number: CN202110917643.2A
Authority: CN
Inventors: 黄宏锐; 符永逸
Original assignee: Guangzhou Huiruisitong Technology Co Ltd
Current assignee: Guangzhou Huiruisitong Technology Co Ltd
Priority date: 2021-08-10
Filing date: 2021-08-10
Publication date: 2021-11-16

Abstract

The invention provides a field programmable gate array circuit, a data transmission method, a chip and a system, wherein the FPGA circuit comprises a data bus, a control bus, an enhanced bus, a communication interface and at least one functional module; wherein: the data bus is used for transmitting data information between the functional module and the external chip; the control bus is used for transmitting control signals between the functional module and the external chip; the enhanced bus is used for transmitting configuration signals between the functional module and the external chip; and the functional module is used for processing the data information according to the control signal and the configuration signal. The data bus, the control bus and the enhanced bus are arranged to transmit the data signals, the control signals and the configuration signals, so that data interaction can be carried out with an external chip through the data bus, the control bus and the enhanced bus correspondingly, the complexity of the system is reduced, and the maintainability in the later period is improved.

Description

On-site programmable gate array circuit, data transmission method, chip and system

Technical Field

The present disclosure relates to the field of electronic circuit technologies, and in particular, to a field programmable gate array circuit, a data transmission method, a chip, and a system.

Background

An FPGA (Field Programmable Gate Array) circuit belongs to a semi-custom circuit in an application-specific integrated circuit, is a Programmable logic Array, and can effectively solve the problem of less Gate circuits of the original device.

As electronic circuits are increasingly advanced into various industries, more and more functions are implemented by using electronic circuits in the industries, and in related circuits, a plurality of FPGA circuits are generally used to implement more functions, and different FPGA circuits are connected through inherent interfaces provided by the FPGA circuits. When a plurality of FPGA circuits need to be interconnected to balance requirements, each FPGA circuit is usually connected through a high-speed interface in a customized system, so that each FPGA circuit communicates according to fixed settings, and a plurality of FPGA circuits are used to realize more functions.

Disclosure of Invention

The inventor finds that in the related art, when more functions need to be realized by adding an FPGA circuit on a designed circuit, because the connections between the interfaces of the circuit are relatively fixed and the customization is strong, the circuit system often needs to be designed again, and the workload and the development difficulty are greatly increased.

The disclosure mainly aims to provide a field programmable gate array circuit, a data transmission method, a chip and a system, and aims to solve the problems of difficulty in development and large workload of interconnection between FPGA circuits in the prior art.

In order to achieve the above object, a first aspect of the present disclosure provides a field programmable gate array FPGA circuit, which includes a data bus, a control bus, an enhanced bus, a communication interface, and at least one functional module; the data bus, the control bus and the enhanced bus are respectively connected with the functional module; the data bus, the control bus and the enhanced bus are also respectively connected with an external chip through the communication interface; wherein:

the data bus is used for transmitting data information between the functional module and the external chip;

the control bus is used for transmitting control signals between the functional module and the external chip;

the enhanced bus is used for transmitting configuration signals between the functional module and the external chip;

the functional module is configured to process the data information according to the control signal and the configuration signal.

Optionally, the communication interface includes a first sub-interface and a second sub-interface, wherein:

the first sub-interface is used for connecting the data bus with a data bus of the external chip and connecting the enhanced bus with an enhanced bus of the external chip;

the second sub-interface is used for connecting the control bus with the control bus of the external chip;

wherein, the first sub-interface is a high-speed interface.

Optionally, the communication interface includes a third sub-interface, wherein:

and the third sub-interface is used for connecting the control bus and an external management module.

Optionally, the communication interface includes a fourth sub-interface, wherein:

the fourth sub-interface is used for connecting the enhanced bus and an external configuration module.

Optionally, the functional module includes a storage unit, wherein:

the storage unit is connected with the data bus and used for storing data input by the data bus.

In a second aspect, to achieve the above object, the present disclosure further provides a method for transmitting data of an FPGA circuit, where the method is applied to an FPGA circuit, and the FPGA circuit includes a data bus, a control bus, an enhanced bus, a communication interface, and at least one functional module; the data bus, the control bus and the enhanced bus are respectively connected with the functional module; the data bus, the control bus and the enhanced bus are also respectively connected with an external chip through the communication interface; the method comprises the following steps:

transmitting data information between the functional module and the external chip through a data bus;

transmitting a control signal between the functional module and the external chip through a control bus;

transmitting a configuration signal between the functional module and the external chip through an enhanced bus;

and processing the data information through a functional module according to the control signal and the configuration signal.

Optionally, the step of processing the data information by the functional module according to the control signal and the configuration signal includes:

acquiring a data type of transmission data through the functional module, and matching a bus corresponding to the data type, wherein the transmission data comprises the data information, a control signal or the configuration signal, and the bus comprises the data bus, the control bus or the enhanced bus;

and sending the transmission data through a bus corresponding to the data type.

receiving address information on a bus through the functional module, and judging whether the address information is consistent with preset address information corresponding to the functional module, wherein the bus comprises the data bus, the control bus or the enhanced bus;

and if the address information is consistent with preset address information corresponding to the functional module, receiving transmission data corresponding to the address information through the functional module, wherein the transmission data comprises the data information, the control signal or the configuration signal.

Optionally, the function module includes a storage unit, and if the address information is consistent with preset address information corresponding to the function module, the step of receiving, by the function module, transmission data corresponding to the address information includes:

and if the address information on the data bus is consistent with the preset address information corresponding to the functional module, receiving and storing the transmission data corresponding to the address information through the storage unit.

In a third aspect, to achieve the above object, the present disclosure further provides an FPGA chip, where the FPGA chip includes the FPGA circuit.

In a fourth aspect, to achieve the above object, the present disclosure further provides an FPGA interconnection system, where the FPGA interconnection system includes a plurality of the FPGA circuits, data buses of the FPGA circuits are connected to each other, control buses of the FPGA circuits are connected to each other, and enhanced buses of the FPGA circuits are connected to each other.

Optionally, the system further includes at least one external management module and at least one external configuration module;

the external management module is connected with the control bus, and the external configuration module is connected with the enhanced bus.

According to the technical scheme, the data bus, the control bus and the enhanced bus are arranged on the FPGA circuit to transmit the data signals, the control signals and the configuration signals, so that the FPGA circuit can correspondingly interact with an external chip through the data bus, the control bus and the enhanced bus, the technical problem that the development difficulty and the workload of the system are increased is solved, the complexity of the system is reduced, and the later maintainability is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

FIG. 1 is a functional block diagram of one embodiment of an FPGA circuit of the present disclosure;

FIG. 2 is a functional block diagram of another embodiment of an FPGA circuit of the present disclosure;

fig. 3 is a schematic flow chart of a first embodiment of the FPGA circuit data transmission method of the present disclosure;

fig. 4 is a schematic flowchart of a second embodiment of the FPGA circuit data transmission method of the present disclosure.

The objects, features, and advantages of the present disclosure will be further explained with reference to the accompanying drawings.

The reference numbers illustrate:

reference numerals	Name (R)	Reference numerals	Name (R)
				100	Control bus	500	Communication interface
200	Data bus	510	High speed interface
				300	Enhanced bus	520	Low speed interface
400	Functional module	600	Interaction module
				410	Memory cell

Detailed Description

It should be understood that the specific embodiments described herein are merely illustrative of the disclosure and are not intended to limit the disclosure.

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

It should be noted that all directional indicators (such as up, down, left, right, front, and back) in the embodiments of the present disclosure are only used to explain the relative position relationship between the components, the motion situation, and the like in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, descriptions in this disclosure referring to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, technical solutions between various embodiments can be combined with each other, but must be realized by a person skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should not be considered to exist, and is not within the protection scope of the present disclosure.

The present disclosure provides a field programmable gate array FPGA circuit, which is applied to an FPGA interconnection system, please refer to fig. 1, and fig. 1 is a functional block diagram of an embodiment of the field programmable gate array FPGA circuit of the present disclosure. In this embodiment, the FPGA circuit includes a data bus 200, a control bus 100, an enhanced bus 300, a communication interface 500, and at least one functional module 400; the data bus 200, the control bus 100 and the enhanced bus 300 are respectively connected with the functional module 400; the data bus 200, the control bus 100 and the enhanced bus 300 are further connected to an external chip through the communication interface 500, respectively; wherein:

the data bus 200 is used for transmitting data information between the functional module 400 and the external chip;

the control bus 100 is used for transmitting control signals between the functional module 400 and the external chip;

the enhanced bus 300 is used for transmitting configuration signals between the functional module 400 and the external chip;

the functional module 400 is configured to process the data information according to the control signal and the configuration signal.

The FPGA circuit belongs to a semi-custom circuit in an application-specific integrated circuit, is a programmable logic array, and can effectively solve the problem of less gate circuits of the original device. The functional module 400 is a module arranged in the FPGA circuit according to the manufacturing requirement of the FPGA circuit, that is, the functional module 400 is used for realizing the actual function of the FPGA circuit; the functional module 400 includes, but is not limited to, a programmable input/output unit, a configurable logic block, a digital clock management module, an embedded block RAM, a wiring resource, an embedded dedicated hardmac, and a bottom embedded functional unit.

The external chip in the embodiment comprises an external FPGA circuit, an external management chip and an external configuration chip;

when a plurality of FPGA circuits and other external chips are expanded, the functional module 400 in the FPGA circuit needs to exchange signals with the functional modules 400 in the other FPGA circuits and the external chips in the operation process; meanwhile, signal communication is also required between the components inside the functional module 400. In this embodiment, signals to be transmitted are mainly divided into data signals, control signals and configuration signals; wherein the data signal mainly comprises operating data; the control signal mainly comprises a control instruction; the configuration signal mainly comprises information communicated with an external configuration chip. The data signals are mainly transmitted by a data bus 200 Memory-bus; the Control signal is mainly transmitted by a Control bus 100 Control-bus; the configuration signals are primarily transmitted by enhanced bus 300 Advanced-bus. It should be noted that, the data bus 200 transmits, in addition to the data signal, an address signal, a valid signal, a ready signal, and the like, so as to implement caching and reading and writing of data; the control bus 100 transmits control signals, address signals, request signals, reply signals and the like, so as to realize the configuration and management of the FPGA circuit by an external management chip; the enhanced bus 300 transmits, in addition to the configuration signals, address signals, data signals, valid signals, and the like, so as to realize the interaction between the configuration and the data of the FPGA circuit by the external configuration chip.

In the embodiment, the data bus 200, the control bus 100 and the enhanced bus 300 are arranged on the FPGA circuit to transmit the data signal, the control signal and the configuration signal, so that the FPGA circuit can perform data interaction with an external chip through the data bus 200, the control bus 100 and the enhanced bus 300, the complexity of the system is reduced, and the maintainability in the later period is improved.

Further, referring to fig. 2, the communication interface 500 includes a first sub-interface and a second sub-interface, wherein:

the first sub-interface is used for connecting the data bus 200 with the data bus 200 of the external chip and connecting the enhanced bus 300 with the enhanced bus 300 of the external chip;

the second sub-interface is configured to connect the control bus 100 with the control bus 100 of the external chip;

wherein the first sub-interface is a high-speed interface 510.

In this embodiment, the second sub-interface is a low-speed interface 520.

Because the data transmission amount of the data bus 200 and the enhanced bus 300 is large, the data bus 200 and the enhanced bus 300 are connected to the high-speed interface 510 to ensure the transmission rate of the data bus 200 and the enhanced bus 300; meanwhile, in order to avoid affecting the transmission rates of the data bus 200 and the enhanced bus 300, the transmission interface of the control bus 100 is independently arranged, and in addition, because the data transmission amount of the control bus 100 is considered to be small, the control bus 100 is connected to the low-speed interface 520, and resource waste is avoided.

The high-speed interface 510 in this embodiment includes 8 transmission lines lane, each having a transmission rate of 20.625 Gps. It should be noted that the number of transmission lines of the high-speed interface 510 and the transmission rate of each transmission line may be set according to the actual application, which is not described herein.

It should be noted that, when the FPGA circuit is connected to the external chip through the high-speed interface 510, the connection mode between the FPGA circuit and the external chip may be determined according to the number of the transmission lines of the high-speed interface 510 and the number of the external chips, for example, when the number of the transmission lines of the high-speed interface 510 of the FPGA circuit is enough to connect to all the external chips, all the external chips may be connected in parallel to the high-speed interface 510 of the FPGA circuit in sequence; when the number of the transmission lines of the high-speed interface 510 of the FPGA circuit is not enough to connect with all the external chips, all the external chips can be connected in series in sequence, that is, the first external chip is connected with the high-speed interface 510 of the FPGA circuit, and the second external chip is connected with the high-speed interface 510 of the first external chip; of course, various connection manners may also be combined, for example, firstly, the high-speed interface 510 of the FPGA circuit is connected in parallel with the external chip, and when the transmission line of the high-speed interface 510 of the FPGA circuit cannot be connected in parallel with the external chip, the remaining external chips are connected to the high-speed interface 510 of the external chip connected to the FPGA circuit.

The functional module 400 comprises a storage unit 410, wherein:

the storage unit 410 is connected to the data bus 200, and is configured to store data input by the data bus 200.

The storage unit 410RAM is a buffer space of the functional modules and a memory space between the functional modules, the functional module 400 stores data received from the data bus 200 into the storage unit 410, and each module reads data stored in the storage unit 410 as needed.

Further, the FPGA circuit may further include an interaction module 600, and the interaction module 600 is communicatively connected to the data bus 200; the interactive module 600 is used for providing an interactive interface for a user and displaying the working information of the FPGA circuit.

The present embodiment connects the data bus 200 and the enhanced bus 300 to the high-speed interface 510, and connects the control bus 100 to the low-speed interface 520, so that the transmission rates of the data bus 200 and the enhanced bus 300 can be ensured, and the influence of the control bus 100 can be avoided.

Further, the communication interface 500 comprises a third sub-interface, wherein:

the third sub-interface is used for connecting the control bus 100 with an external management module;

the external management module may be, but is not limited to, an Advanced RISC Machine (ARM) chip, which is a Reduced Instruction Set Computer (RISC) microprocessor designed for low-budget market oriented by Acorn computer limited. Earlier known as Acorn RISC Machine. The ARM chip has the advantages of low power consumption, strong function and 16-bit/32-bit double instruction set.

The FPGA circuit is mainly used for realizing high-speed sampling of data, and the ARM chip is used for displaying the data and providing a man-machine interaction function.

Further, the communication interface 500 comprises a fourth sub-interface, wherein:

the fourth sub-interface is used for connecting the enhanced bus 300 with an external configuration module,

the external configuration module can be but not limited to a Digital Signal Processing (DSP) chip, the DSP chip adopts a Harvard structure with separated programs and data, is provided with a special hardware multiplier, widely adopts pipeline operation, provides special DSP instructions, and can be used for quickly realizing various Digital Signal processing algorithms. The DSP chip has the advantages of large-scale integration, good stability, high precision, programmability, high-speed performance, embeddability, and convenient interface and integration.

For the basic architecture of the FPGA circuit and the DSP chip, the DSP circuit module mainly comprises the DSP chip and a FLASH chip for storing programs of the DSP chip, which are already in a minimum structure and cannot be simplified. The common configuration mode of the FPGA circuit module is an FPGA circuit and a corresponding configuration chip. The FPGA has various configuration modes, and different configuration modes have different required chips, so that the area of the circuit board can be saved to a certain extent by adopting the configuration mode with less chips.

Different manufacturers and different series of FPGA circuits have different configuration modes; there are 5 kinds of configuration modes, i.e. active serial, active parallel, passive serial, passive parallel and boundary scan. The boundary scanning mode can only burn and write the lost bit file after power failure, and the bit file cannot be used in a system independently; the active serial and active parallel configuration mode needs additional configuration chips, which is not beneficial to simplifying the system; the passive parallel and passive serial configuration modes are configured by a microprocessor connected with the exterior of the FPGA circuit, and the DSP chip can just serve as the microprocessor in the configuration circuit, so that the configuration chip can be omitted, and the system volume can be reduced to a certain extent.

In addition, the present disclosure also protects an FPGA circuit data transmission method, which is applied to an FPGA circuit, the circuit including a data bus, a control bus, an enhanced bus, a communication interface, and at least one functional module; the data bus, the control bus and the enhanced bus are respectively connected with the functional module; the data bus, the control bus and the enhanced bus are also respectively connected with an external chip through the communication interface; the structure of the FPGA circuit can also refer to the aforementioned embodiments, and is not described herein again. The implementation process is consistent with the structural embodiment and can be executed by reference; referring to fig. 3, fig. 3 is a schematic flow chart of a first embodiment of the FPGA circuit data transmission method of the present disclosure, and in the first embodiment of the FPGA circuit data transmission method of the present disclosure, the method includes the steps of:

step S10, transmitting data information between the functional module and the external chip through a data bus;

step S20, transmitting control signals between the functional module and the external chip through a control bus;

step S30, transmitting configuration signals between the functional module and the external chip through an enhanced bus;

and step S40, processing the data information through a functional module according to the control signal and the configuration signal.

In this embodiment, signals to be transmitted are mainly divided into data signals, control signals and configuration signals; wherein the data signal mainly comprises operating data; the control signal mainly comprises a control instruction; the configuration signal mainly comprises information communicated with an external configuration chip. The data signals are mainly transmitted by a data bus; the control signal is mainly transmitted by a control bus; the configuration signals are transmitted mainly by the enhanced bus. It should be noted that, the data bus transmits, for example, an address signal, an effective signal, a ready signal, and the like in addition to the data signal, so as to implement caching and reading and writing of data; the control bus transmits control signals, address signals, request signals, reply signals and the like, so that the configuration and management of the FPGA circuit by an external management chip are realized; the enhanced bus transmits configuration signals, address signals, data signals, valid signals and the like, so that the configuration and data interaction of the FPGA circuit by an external configuration chip is realized.

According to the embodiment, the data bus, the control bus and the enhanced bus are arranged on the FPGA circuit, and the transmission of the data signal, the control signal and the configuration signal is carried out through different types of buses according to the data type, so that the FPGA circuit can carry out data interaction with an external chip through the data bus, the control bus and the enhanced bus correspondingly, the complexity of the system is reduced, and the maintainability in the later period is improved.

Further, in a second embodiment of the present disclosure based on the first embodiment of the FPGA circuit data transmission method of the present disclosure, the step S40 includes the steps of:

step S41, obtaining a data type of transmission data through the functional module, and matching a bus corresponding to the data type, where the transmission data includes the data information, the control signal, or the configuration signal, and the bus includes the data bus, the control bus, or the enhanced bus;

and step S42, sending the transmission data through the bus corresponding to the data type.

Referring to fig. 4, in step S43, the functional module receives address information on a bus, and determines whether the address information is consistent with preset address information corresponding to the functional module, where the bus includes the data bus, the control bus, or the enhanced bus;

step S44, if the address information is consistent with the preset address information corresponding to the functional module, receiving, by the functional module, transmission data corresponding to the address information, where the transmission data includes the data information, the control signal, or the configuration signal.

Step S45, if the address information is inconsistent with the preset address information corresponding to the functional module, not receiving the transmission data corresponding to the address information.

According to different types of buses, the specific data receiving modes are different; specifically, when data is received through the data bus, the data bus performs data transmission through the high-speed interface according to read-write operations of each functional module and the chip, and stores the received data in the storage unit, when the data is stored, the data corresponding to the functional module is stored in an address corresponding to the functional module, and when the data is read by the functional module, the data corresponding to the address is read from the storage unit according to the address of the functional module. When data is received through the control bus, the request signal is validated, address information corresponding to the functional module is uploaded to the control bus at the same time, a reply signal is waited, and when the reply signal is validated, corresponding data is read from the control bus; specifically, the control bus performs data transmission through the low-speed interface, and the control bus is mainly used for transmitting a control signal sent by the ARM to the FPGA and acquiring a debugging signal. When data is received through the enhanced bus, the function module judges whether an incoming address corresponding to the data input by the enhanced bus corresponds to the address of the function module, if the incoming address corresponding to the data input by the enhanced bus corresponds to the address of the function module, the data input by the enhanced bus is the data required to be received by the function module, and the function module takes the data; if the incoming address corresponding to the data input by the enhanced bus does not correspond to the address of the functional module, it indicates that the data input by the enhanced bus is not the data that the functional module needs to receive, and the functional module does not take the data.

Optionally, the functional module includes a storage unit, and the step S44 includes:

and if the address information on the data bus is consistent with the preset address information corresponding to the functional module, receiving and storing the transmission data corresponding to the address information through the storage unit. In this embodiment, the storage unit in the functional module is a cache space of the functional module and an interactive memory space between the functional modules, and the functional module stores the received data in the storage unit and reads the data stored in the storage unit from the storage unit when necessary.

Similarly, the data writing mode is different according to different types of buses; specifically, when data is written through the data bus, an address of a module or a chip corresponding to a data receiving end in the storage unit is firstly acquired, after the address is acquired, a valid signal is validated, and meanwhile, data to be sent is stored into the corresponding address of the storage unit through the data bus. When data is written through the control bus, the request signal is first asserted, while data and address signals are sent through the control bus, and a reply signal is awaited, and when the reply signal is asserted, the next data can be written. When data is written through the enhanced bus, firstly, the address of a module or a chip corresponding to a data receiving end in a storage unit is obtained, after the address is obtained, an effective signal is validated, and meanwhile, data needing to be sent is stored in the corresponding address of the storage unit through the enhanced bus.

In this embodiment, the functional module in the FPGA circuit communicates with the external management module through the control bus, so that the external management module controls the functional module; the data bus is communicated with an external data module through the data bus, and is communicated with other FPGA circuits through a high-speed interface, so that each functional module receives data to be processed and sends out the processed data; and the enhanced bus is communicated with an external configuration module to realize the function configuration of each function module. For each functional module in the FPGA, only 3 buses are butted, and communication is realized through the 3 buses, so that the resource utilization rate is improved, and meanwhile, the data delay is reduced.

It is noted that while for simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present disclosure is not limited by the order of acts, as some steps may, in accordance with the present disclosure, occur in other orders and concurrently. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required for the disclosure.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present disclosure.

The present disclosure also protects an FPGA chip comprising an FPGA circuit as described above. It should be understood that, because the FPGA chip of this embodiment adopts the technical scheme of the FPGA circuit, the FPGA chip has all the beneficial effects of the FPGA circuit.

The present disclosure also protects an FPGA interconnection system, which includes a plurality of the FPGA circuits as described above, a plurality of data buses of the FPGA circuits being interconnected, a plurality of control buses of the FPGA circuits being interconnected, and a plurality of enhanced buses of the FPGA circuits being interconnected. It should be understood that, because the FPGA interconnection system of the present embodiment adopts the technical scheme of the FPGA circuit, the FPGA interconnection system has all the beneficial effects of the FPGA circuit.

According to the embodiment, the data bus, the control bus and the enhanced bus are arranged on the FPGA circuit to transmit the data signal, the control signal and the configuration signal, so that the FPGA circuit can perform data interaction with an external chip through the data bus, the control bus and the enhanced bus, the complexity of the system is reduced, and the maintainability in the later period is improved.

Further, the system also comprises at least one external management module and at least one external configuration module;

The external management module may be, but is not limited to, an ARM chip, which is a RISC microprocessor designed for the low budget market by Acorn computer limited. Earlier known as Acorn RISC Machine. The ARM chip has the advantages of low power consumption, strong function and 16-bit/32-bit double instruction set.

The external configuration module can be but is not limited to a DSP chip, a Harvard structure with a program and data separated is adopted in the DSP chip, a special hardware multiplier is arranged, pipeline operation is widely adopted, a special DSP instruction is provided, and various digital signal processing algorithms can be rapidly realized. The DSP chip has the advantages of large-scale integration, good stability, high precision, programmability, high-speed performance, embeddability, and convenient interface and integration.

For the basic architecture of FPGA + DSP, the DSP circuit module mainly comprises a DSP chip and a FLASH chip for storing programs thereof, which are already in a minimum structure and cannot be simplified. The common configuration mode of the FPGA circuit module is an FPGA circuit and a corresponding configuration chip. The FPGA has various configuration modes, and different configuration modes have different required chips, so that the area of the circuit board can be saved to a certain extent by adopting the configuration mode with less chips.

The above-mentioned serial numbers of the embodiments of the present disclosure are merely for description and do not represent the merits of the embodiments.

The integrated unit in the above embodiments, if implemented in the form of a software functional unit and sold or used as a separate product, may be stored in the above computer-readable storage medium. Based on such understanding, the technical solution of the present disclosure may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing one or more computer devices (which may be personal computers, servers, network devices, etc.) to execute all or part of the steps of the method according to the embodiments of the present disclosure.

In the above embodiments of the present disclosure, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In several embodiments provided in the present disclosure, it should be understood that the disclosed client may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implemented, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, units or modules, and may be in an electrical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The foregoing is merely a preferred embodiment of the present disclosure, and it should be noted that modifications and embellishments could be made by those skilled in the art without departing from the principle of the present disclosure, and these should also be considered as the protection scope of the present disclosure.

Claims

1. A field programmable gate array FPGA circuit is characterized by comprising a data bus, a control bus, an enhanced bus, a communication interface and at least one functional module; the data bus, the control bus and the enhanced bus are respectively connected with the functional module; the data bus, the control bus and the enhanced bus are also respectively connected with an external chip through the communication interface; wherein:

and the functional module is used for processing the data information according to the control signal and the configuration signal.

2. The field programmable gate array, FPGA, circuit of claim 1 wherein said communication interface comprises a first sub-interface and a second sub-interface, wherein:

the second sub-interface is used for connecting the control bus with a control bus of the external chip;

wherein the first sub-interface is a high-speed interface.

3. The field programmable gate array, FPGA, circuit of claim 1 or 2 wherein said communication interface comprises a third sub-interface, wherein:

4. The FPGA circuit of claim 1, wherein the communication interface comprises a fourth sub-interface, wherein:

and the fourth sub-interface is used for connecting the enhanced bus and an external configuration module.

5. The field programmable gate array FPGA circuit of claim 1 wherein said functional module comprises a memory cell, wherein:

6. The FPGA circuit data transmission method is characterized in that the method is applied to an FPGA circuit, and the circuit comprises a data bus, a control bus, an enhanced bus, a communication interface and at least one functional module; the data bus, the control bus and the enhanced bus are respectively connected with the functional module; the data bus, the control bus and the enhanced bus are also respectively connected with an external chip through the communication interface; the method comprises the following steps:

7. The method according to claim 6, wherein the step of processing the data information by the functional module according to the control signal and the configuration signal comprises:

and sending the transmission data through a bus corresponding to the data type.

8. The FPGA circuit data transmission method of claim 6 or 7, wherein said step of processing said data information by said functional module according to said control signal and said configuration signal comprises:

9. The method according to claim 8, wherein the functional module includes a storage unit, and the step of receiving the transmission data corresponding to the address information through the functional module if the address information is consistent with the preset address information corresponding to the functional module includes:

10. An FPGA chip, characterized in that it comprises an FPGA circuit according to any one of claims 1 to 5.

11. An FPGA interconnection system, characterized in that the system comprises a plurality of FPGA circuits according to any one of claims 1 to 5, data buses of the plurality of FPGA circuits are connected to each other, control buses of the plurality of FPGA circuits are connected to each other, and enhanced buses of the plurality of FPGA circuits are connected to each other.

12. The FPGA interconnect system of claim 11, further comprising at least one external management module and at least one external configuration module;