CN113632373A - 跨阻抗放大器电容隔离级 - Google Patents
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Abstract
公开了一种微机电系统陀螺仪(7)的电子电路(8)。该电子电路(8)包括电流缓冲器(1)、与电流缓冲器(1)耦接的跨阻放大器(2)、以及多个晶体管(5)。电流缓冲器(1)的反相输入端子和电流缓冲器(1)的非反相输入端子与多个第一电阻器(3)连接。电流缓冲器(1)的反相输入端子与多个晶体管(5)中的一个晶体管的源极连接,并且电流缓冲器(1)的非反相输入端子与多个晶体管(M SF)中的另一个晶体管的源极连接。多个第一电阻器(3)接地。电流缓冲器(1)被配置为将微机电系统陀螺仪(7)中的负载与跨阻放大器(2)隔离。
Description
技术领域
至少一个示例实施例涉及一种微机电系统陀螺仪的电子电路,并且具体地,涉及一种具有后接跨阻放大器的电流缓冲器的微机电系统陀螺仪的电子电路,其中电流缓冲器将微机电系统陀螺仪中的负载与跨阻放大器隔离。
背景技术
微机电系统(MEMS)陀螺仪的常规电子电路具有带电阻反馈架构的单个运算放大器(图1)以及具有经调节的公共栅极(RCG)输入的开环跨阻放大器架构(图2)。
然而,在单个运算放大器架构中,最大跨阻放大器增益受到MEMS的电容负载的限制,这降低了MEMS ASIC(专用集成电路)的信噪比(SNR)。另外,单个运算放大器架构消耗过多的功率。
在具有经调节的公共栅极输入的开环跨阻放大器架构中,输入电容负载效应被最小化,但是跨阻放大器增益不准确。即,增益对晶体管输出阻抗具有一定的依赖性。
因此,迫切需要一种微机电系统陀螺仪的电子电路以产生极低的噪声,以及具有低输入和输出阻抗和准确增益的高增益带宽跨阻放大器。
引用列表
专利文献
专利文献1
美国专利No.9,804,190
发明内容
根据一方面,提供了一种微机电系统陀螺仪的电子电路。电子电路可以包括电流缓冲器、与电流缓冲器耦接的跨阻放大器和多个晶体管。电流缓冲器的反相输入端子和电流缓冲器的非反相输入端子可以与多个第一电阻器连接。电流缓冲器的反相输入端子可以与多个晶体管中的一个晶体管的源极连接,并且电流缓冲器的非反相输入端子可以与多个晶体管中的另一个晶体管的源极连接。多个第一电阻器可以接地。电流缓冲器可以被配置为将微机电系统陀螺仪中的负载与跨阻放大器隔离。
在电子电路中,电流缓冲器的反相输入端子和电流缓冲器的非反相输入端子可以与多个第二电阻器连接。
在电子电路中,跨阻放大器的反相输入端子和跨阻放大器的非反相输入端子可以与多个第三电阻器连接。
在电子电路中,跨阻放大器的反相输入端子可以与多个晶体管中的一个的漏极连接,并且跨阻放大器的非反相输入端子可以与多个晶体管中的另一个晶体管的漏极连接。
在电子电路中,多个第一电阻器的电阻值和多个第二电阻器的电阻值可以不同。
在电子电路中,电子电路的输入侧阻抗和电子电路的输出侧阻抗可以不同。
示例实施例的附加方面将部分地在随后的描述中阐述,并且部分地将通过该描述而显而易见,或者可以通过本公开的实践进行获知。
附图说明
本发明的这些和/或其他方面、特征和优点将通过结合附图的示例实施例的以下描述而变得清楚明白且更容易理解。
图1是具有电阻反馈架构的单个运算放大器的示例的示图。
图2是具有经调节的公共栅极输入的开环跨阻架构的示例的示图。
图3是根据示例实施例的微机电系统陀螺仪的电子电路的示例的示图。
图4是根据示例实施例的电子电路中的电流缓冲器的示例的示图。
图5是根据示例实施例的电子电路中的跨阻放大器的示例的示图。
图6是根据示例实施例的微机电系统陀螺仪的电子电路中的各个点(A1、A2、B1、B2、C1和C3)处的信号波形的示例。
具体实施方式
本文中所描述的示例实施例的以下结构或功能描述仅仅旨在出于描述本文中所描述的示例实施例的目的,并且可以以各种形式实现。在此,示例实施例不被解释为限于本公开,并且应被理解为包括本公开的技术思想内的所有改变、等同和替换。
在下文中,将参考附图来详细描述示例实施例。关于分配给附图中的元素的附图标记,应该注意的是,尽管相同的元素在不同的附图中示出,但在可能的情况下将由相同的附图标记来表示相同的元素。而且,在对示例实施例的描述中,当认为公知的相关结构或功能的详细描述将导致本公开的模糊解释时,可以省略这样的描述。
图1是具有带电阻反馈架构的单个运算放大器的微机电系统(MEMS)陀螺仪的常规电子电路的示例的示图。
图2是具有开环跨阻放大器架构的微机电系统(MEMS)陀螺仪的另一常规电子电路的示例的示图,该开环跨阻放大器架构具有经调节的公共栅极(RCG)输入。
然而,如上所述,这些常规电路具有缺点。在单个运算放大器架构中,最大跨阻放大器增益受到MEMS的电容负载的限制,这降低了MEMS ASIC(专用集成电路)的信噪比(SNR)。另外,单个运算放大器架构可能会消耗过多的功率。在具有经调解的公共栅极输入的开环跨阻放大器架构中,输入电容负载效应被最小化,但是跨阻放大器增益不准确。即,增益对晶体管输出阻抗具有一定的依赖性。
图3是根据示例实施例的微机电系统陀螺仪的电子电路的示例的示图。图4是根据示例实施例的电子电路中的电流缓冲器的示例的示图。图5是根据示例实施例的电子电路中的跨阻放大器的示例的示图。
参考图3,MEMS陀螺仪7的电子电路8包括电流缓冲器1、与电流缓冲器1耦接的跨阻放大器2和多个晶体管5。电流缓冲器1的反相输入端子和电流缓冲器1的非反相输入端子与多个第一电阻器3连接。多个第一电阻器3的电阻可以是1.8MΩ。然而,该值不仅仅限于1.8MΩ。电阻器为晶体管提供静态偏置电流。
电流缓冲器1的反相输入端子与多个晶体管5中的一个晶体管的源极连接,并且电流缓冲器1的非反相输入端子与多个晶体管5中的另一个晶体管的源极连接。多个第一电阻器3接地。
电流缓冲器1将微机电系统陀螺仪7中的负载(Rm)与跨阻放大器2隔离。
电流缓冲器1的反相输入端子和电流缓冲器1的非反相输入端子可以与多个第二电阻器4连接。多个第二电阻器4的电阻可以是0.5MΩ。然而,该值不仅仅限于0.5MΩ。
跨阻放大器2的反相输入端子和跨阻放大器2的非反相输入端子与多个第三电阻器6连接。多个第三电阻器6的电阻可以是500kΩ。然而,该值不仅仅限于500kΩ。
跨阻放大器2的反相输入端子与多个晶体管5中的一个晶体管的连接,并且跨阻放大器2的非反相输入端子与多个晶体管5中的另一个的漏极连接。
多个第一电阻器的电阻值和多个第二电阻器的电阻值可以不同。
电子电路的输入侧的阻抗和电子电路的输出侧的阻抗可以不同。
图6是根据示例实施例的微机电系统陀螺仪的电子电路中的各个点(A1、A2、B1、B2、C1和C3)处的信号波形的示例。
参考图6,A1和A2(顶部)处的信号波形是正负差分AC电压信号。它是电子电路8的输入电压,其值非常小,并且几乎为零。B1和B2(中间)处的信号波形在幅度上与A1和A2处的波形相似,但是具有相移。C1和C2(底部)的信号波形具有比A1/A2和B1/B2两者处的信号波形高得多的峰值电压电平。
因此,电子电路8产生非常低的噪声,以及具有低输入和输出阻抗以及准确增益的高增益带宽跨阻放大器,这在图1和2中所示的常规电路中是不可能的。
可以使用硬件组件和软件组件来实现上述示例实施例。后端处理设备可以使用诸如以下项的一个或多个通用或专用计算机来实现:例如,处理器、控制器和算术逻辑单元(ALU)、数字信号处理器(DSP)、微型计算机、现场可编程门阵列(FPGA)、可编程逻辑单元(PLU)、微处理器、或者能够以所定义的方式响应并执行指令的任何其他的设备。处理设备可以运行操作系统(OS)以及在OS上运行的一个或多个软件应用。处理设备还可以响应于软件的执行而访问、存储、操控、处理和创建数据。为了简单起见,对处理设备的描述使用单数形式;然而,本领域技术人员应理解的是,硬件设备可以包括多个处理元件和多种类型的处理元件。
软件可以包括计算机程序、代码、指令、或它们的某种组合,以独立或共同地指示或配置陀螺仪系统以根据需要进行操作。软件和数据可以永久或临时地具体实施在任何类型的机器、组件、物理或虚拟装备、计算机存储介质或设备中,或者具体实施在能够向设备提供指令或数据或能够由没备解释的传播信号波中。
虽然本公开包括特定的示例,但是对于本领域普通技术人员来说显而易见的是:在不脱离权利要求及其等同物的精神和范围的情况下,可以在这些示例中进行形式和细节上的各种改变。本文描述的示例应仅被认为是描述性的,而不是为了限制的目的。每个示例中的特征或方面的描述被认为适用于其他示例中的类似特征或方面。如果所描述的技术以不同的顺序执行和/或如果所描述的系统、架构、设备或电路中的组件以不同的方式组合和/或被其他的组件或其等同替换或补充,则可以实现合适的结果。因此,本公开的范围不是由详细描述来限定,而是由权利要求及其等同物来限定,并且在权利要求及其等同物的范围内的所有变化都被解释为包括在本公开中。
[附图标记列表]
1电流缓冲器
2跨阻放大器(TIA)
3第一电阻器
4第二电阻器
5晶体管
6第三电阻器
7MEMS陀螺仪
8电子线路。
Claims (6)
1.一种微机电系统陀螺仪的电子电路,包括:
电流缓冲器;
跨阻放大器,与所述电流缓冲器耦接;以及
多个晶体管,
其中,所述电流缓冲器的反相输入端子与所述电流缓冲器的非反相输入端子与多个第一电阻器连接,
其中,所述电流缓冲器的反相输入端子与所述多个晶体管中的一个晶体管的源极连接,并且所述电流缓冲器的非反相输入端子与所述多个晶体管中的另一个晶体管的源极连接,
其中,所述多个第一电阻器接地,
其中,所述电流缓冲器被配置为将所述微机电系统陀螺仪中的负载与所述跨阻放大器隔离。
2.根据权利要求1所述的电子电路,其中,所述电流缓冲器的反相输入端子和所述电流缓冲器的非反相输入端子与多个第二电阻器连接。
3.根据权利要求1所述的电子电路,其中,所述跨阻放大器的反相输入端子和所述跨阻放大器的非反相输入端子与多个第三电阻器连接。
4.根据权利要求1所述的电子电路,其中,所述跨阻放大器的反相输入端子与所述多个晶体管中的一个晶体管的漏极连接,并且所述跨阻放大器的非反相输入端子与所述多个晶体管中的另一个晶体管的漏极连接。
5.根据权利要求2所述的电子电路,其中,所述多个第一电阻器的电阻值和所述多个第二电阻器的电阻值不同。
6.根据权利要求1所述的电子电路,其中,所述电子电路的输入侧的阻抗与所述电子电路的输出侧的阻抗不同。
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