CN113625854A - Mainboard power-on control system, method and device and readable storage medium - Google Patents

Mainboard power-on control system, method and device and readable storage medium Download PDF

Info

Publication number
CN113625854A
CN113625854A CN202110722505.9A CN202110722505A CN113625854A CN 113625854 A CN113625854 A CN 113625854A CN 202110722505 A CN202110722505 A CN 202110722505A CN 113625854 A CN113625854 A CN 113625854A
Authority
CN
China
Prior art keywords
power
chip
control
cpld
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110722505.9A
Other languages
Chinese (zh)
Other versions
CN113625854B (en
Inventor
张跃文
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Suzhou Inspur Intelligent Technology Co Ltd
Original Assignee
Suzhou Inspur Intelligent Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Suzhou Inspur Intelligent Technology Co Ltd filed Critical Suzhou Inspur Intelligent Technology Co Ltd
Priority to CN202110722505.9A priority Critical patent/CN113625854B/en
Publication of CN113625854A publication Critical patent/CN113625854A/en
Application granted granted Critical
Publication of CN113625854B publication Critical patent/CN113625854B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The invention provides a mainboard power-on control system, a method, a device and a readable storage medium, wherein the system comprises: the system comprises a control terminal, a BMC, a CPLD and a plurality of VR chips; the control terminal is in signal connection with the BMC through a serial port and is used for sending a control instruction; the BMC is connected with the CPLD through an I2C bus and is used for transmitting a control signal to the CPLD according to a control instruction; the CPLD is respectively in signal connection with each VR chip and is used for controlling the power-on time sequence of the VR chip according to the power-on control logic and starting the debugging function to suspend the power-on time sequence of the VR chip according to the control signal. The invention can selectively control VR chip control signal to be effective under the condition of keeping the original logic in the CPLD unchanged, thereby controlling the power-on time sequence to be suspended at a certain stage, and facilitating system debugging.

Description

Mainboard power-on control system, method and device and readable storage medium
Technical Field
The invention relates to the technical field of computers, in particular to a mainboard power-on control system, method and device and a readable storage medium.
Background
With the development of cloud computing applications, informatization gradually covers various fields of society. The application proportion of the server in various industries is getting bigger and bigger. The server can maintain continuous and stable operation, all parts are needed to cooperate to provide strong and powerful guarantee, a power supply system plays a crucial factor, and the stability of the whole system can be influenced by the stability of the power supply voltage. Therefore, the stable and reliable power-on time sequence of the mainboard needs to be ensured in the design and test stage of the mainboard, the voltage of the power supply end and the voltage of the output end are ensured to meet the requirements, and the anti-interference capability of the characteristics of output current, ripple waves and the like is also considered. In practical design, level voltage control can be satisfied by properly selecting and configuring a power management chip, but a single chip cannot complete control of multiple levels, and particularly in the design of a server mainboard, a single CPU needs multiple reference power supplies with different levels, and strict requirements are also imposed on the power-on sequence of the levels. Therefore, it is necessary for the external device to control the operating state of the power management chip and to control and adjust the corresponding level timing sequence, so as to observe and adjust the power-on sequence of the level and perform the system power test.
At present, the scheme for controlling the power-on of the power level, which is more frequently used, is to control an enable signal of a corresponding VR chip (power management chip) through a CPLD (Complex Programmable Logic Device). The control signal of the CPLD is connected with the enabling signal of the VR chip, and a designer can realize high-low level control on the corresponding enabling signal by modifying the logic code of the CPLD, so as to control the power-on sequence of a plurality of levels. In the design, a completion signal of one level is fed back to the CPLD to serve as an enabling basis of the next level, and an enabling signal of the next level is automatically given through internal logic of the chip, and the like. The logic code of the CPLD is stored in a Flash Memory inside the chip, and in order to modify or debug whether the power-on meets the requirements, a CPLD designer needs to write the logic code on a special editor and then burn the logic code into the CPLD chip.
However, in the existing scheme, the enable signals of each level during the power-on process of the motherboard are automatically completed according to the preset sequence of the internal logic of the CPLD. When some changes are not large or only some electricity is required to be enabled but some electricity is not enabled, for example, when the power-on state before some electricity needs to be observed and the rest electricity is invalid (for example, when the leakage current exists in the mainboard and the source of the leakage current needs to be confirmed and the interference by other electricity is not needed), the burning code needs to be recompiled. When the above requirements on other electricity need to be repeatedly performed, the burn-recording needs to be modified once and again, and a great amount of time, energy and manpower are consumed.
Disclosure of Invention
In view of the above problems, an object of the present invention is to provide a system, a method, a device and a readable storage medium for controlling power-on of a motherboard, which can selectively control a VR chip to control a signal to be valid and further control a power-on sequence to be suspended at a certain stage on the basis of keeping original logic in a CPLD unchanged, thereby facilitating system debugging.
In order to achieve the purpose, the invention is realized by the following technical scheme: a motherboard power-on control system comprising: the system comprises a control terminal, a BMC, a CPLD and a plurality of VR chips;
the control terminal is in signal connection with the BMC through a serial port and is used for sending a control instruction;
the BMC is connected with the CPLD through an I2C bus and is used for transmitting a control signal to the CPLD according to a control instruction;
the CPLD is respectively in signal connection with each VR chip and is used for controlling the power-on time sequence of the VR chip according to the power-on control logic and starting the debugging function to suspend the power-on time sequence of the VR chip according to the control signal.
Furthermore, the CPLD sends an enable signal EN to the VR chip to control the electrification of the VR chip, and the VR chip sends a feedback signal PWRGD to the CPLD after electrification.
Further, the I2C bus includes a serial data line SDA and a serial clock line SCL, which are used to cooperate with the power-on control logic of the CPLD to suspend the power-on timing sequence of the VR chip through the debugging function.
Further, the enable signal EN and the feedback signal PWRGD are both active at high level.
Further, the control terminal is used for determining a corresponding mark according to the VR chip to be observed, generating a control instruction according to the mark of the VR chip and sending the control instruction to the BMC, and is also used for sending a recovery signal to the CPLD when the power-on control logic is in a suspended execution state.
Further, the CPLD is used for adding a mark of the VR chip into the power-on control logic and storing the mark; and the power-on control logic is also used for controlling the power-on time sequence of the VR chip according to the power-on control logic, determining the powered-on VR chip according to the mark of the VR chip, and suspending the execution of the power-on control logic through a debugging function after the power-on of the VR chip to be observed is completed.
Further, CPLDs are specifically configured to: when programming the power-on control logic, sequencing the power-on time sequences of all VR chips, sequentially marking the VR chips in a digital form, and storing the marked power-on control logic in an internal register of the CPLD.
Correspondingly, the invention also discloses a mainboard power-on control method, which comprises the following steps:
adding a mark of a VR chip into the power-on control logic through the CPLD, and storing the mark;
the control terminal determines a corresponding mark according to the VR chip to be observed, and generates a control instruction according to the mark of the VR chip to be sent to the BMC;
the BMC generates a control signal according to the control instruction and sends the control signal to the CPLD;
the CPLD controls the power-on time sequence of the VR chip according to the power-on control logic, and determines the powered-on VR chip according to the mark of the VR chip;
and if the VR chip to be observed currently is powered on, the execution of the power-on control logic is suspended through the debugging function.
Further, the adding a mark of the VR chip into the power-on control logic through the CPLD and storing specifically includes:
when the CPLD writes the power-on control logic, sequencing the power-on time sequences of all VR chips, sequentially marking the VR chips in a digital form, and storing the marked power-on control logic in an internal register of the CPLD.
Further, the step of stopping the execution of the power-on control logic by the debugging function after the VR chip to be observed is powered on includes:
after the power-on of the VR chip to be observed is finished, the feedback signal PWRGD sent to the CPLD by the VR chip to be observed is in a high level, after the CPLD receives the high-level feedback signal PWRGD sent by the VR chip to be observed, the execution of the power-on control logic is suspended, the low-level enable signal EN is sent to the VR chip which is not powered on, and the enable signal EN of the VR chip which is not powered on is enabled to be invalid.
Further, the mainboard power-on control method further includes:
when the power-on control logic is in a suspended execution state, a recovery signal is sent to the CPLD through the control terminal, after the CPLD receives the recovery signal, a high-level enabling signal EN is sent to the VR chip which is not powered on, the enabling signal EN of the VR chip which is not powered on is effective, and the power-on control logic is continuously executed.
Correspondingly, the invention discloses a mainboard power-on control device, which comprises:
the memory is used for storing a mainboard power-on control program;
and the processor is used for realizing the steps of the mainboard power-on control method according to any one of the above items when executing the mainboard power-on control program.
Correspondingly, the invention discloses a readable storage medium, wherein a mainboard power-on control program is stored on the readable storage medium, and the mainboard power-on control program realizes the steps of the mainboard power-on control method according to any one of the above when being executed by a processor.
Compared with the prior art, the invention has the beneficial effects that:
1. the invention utilizes the control terminal connected with the BMC to send the instruction, controls the CPLD to generate the level effective signal of the appointed time sequence, and further suspends the execution of the power-on control logic after the appointed level is generated, thereby realizing the effect of selectively controlling the VR chip control signal to be effective under the condition of keeping the original logic in the CPLD unchanged, and further controlling the power-on time sequence to suspend at a certain stage. The invention realizes the observation and adjustment of the level power-on sequence and the system power supply test without modifying the power-on control logic.
2. The invention transmits the control signal through an I2C bus, only needs two signal wires of SCL and SDA, and can complete the debugging function by matching with the internal logic of the CPLD. The BMC is used as a host to send commands, and the CPLD is used as a slave to receive commands and execute control actions. The BMC has more external interfaces, can be conveniently adjusted to meet user requirements, and in the connection mode with the control terminal, the serial port of the BMC is used, and is directly connected with the control terminal through an external hardware circuit and hardware equipment, so that plug and play are realized.
3. The invention can sort the level generated by the VR chip, adds a debugging function in the CPLD, selectively gates part of enabling signals, conveniently generates the working level meeting the observation purpose, and effectively solves the problem that the CPLD code needs to be frequently changed for observing the specific level state in the mainboard debugging process.
4. The invention can be applied to places with requirements on working voltage in the design and debugging of the mainboard of electronic equipment such as a mobile phone, a server and the like.
Therefore, compared with the prior art, the invention has prominent substantive features and remarkable progress, and the beneficial effects of the implementation are also obvious.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
FIG. 1 is a system block diagram of the present invention;
FIG. 2 is a flow chart of the method of the present invention;
fig. 3 is a schematic diagram of the debugging function execution of the present invention.
In the figure, 1 is a control terminal; 2 is BMC; 3 is CPLD; and 4 is VR chip.
Detailed Description
The core of the invention is to provide a mainboard power-on control method, in the prior art, the enabling signals of each level in the mainboard power-on process can be automatically completed according to the preset sequence of the CPLD internal logic. When some changes are not large or only some electricity is required to be enabled and some electricity is not enabled, for example, when the power-on state before a certain electricity needs to be observed and the rest electricity is not available, the burning code needs to be recompiled. When the above requirements on other electricity need to be repeatedly performed, the burn-recording needs to be modified once and again, and a great amount of time, energy and manpower are consumed.
Firstly, adding a mark of a VR chip into the power-on control logic through a CPLD and storing the mark; then, the control terminal determines a corresponding mark according to the VR chip to be observed, and generates a control instruction according to the mark of the VR chip and sends the control instruction to the BMC; the BMC generates a control signal according to the control instruction and sends the control signal to the CPLD; the CPLD controls the power-on time sequence of the VR chip according to the power-on control logic, and determines the powered-on VR chip according to the mark of the VR chip; and if the VR chip to be observed currently is powered on, the execution of the power-on control logic is suspended through the debugging function. Therefore, the method can sequence the levels generated by the VR chip, add a debugging function in the CPLD, selectively gate part of enabling signals, conveniently generate the working level meeting the observation purpose, and effectively solve the problem that the CPLD codes are frequently changed for observing the specific level state in the mainboard debugging process.
In order that those skilled in the art will better understand the disclosure, the invention will be described in further detail with reference to the accompanying drawings and specific embodiments. It is to be understood that the described embodiments are merely exemplary of the invention, and not restrictive of the full scope of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The first embodiment is as follows:
as shown in fig. 1, the present embodiment provides a motherboard power-on control system, including: the system comprises a control terminal 1, a BMC 2, a CPLD3 and a plurality of VR chips 4; the control terminal 1 is in signal connection with the BMC 2 through a serial port and used for sending a control instruction; the BMC 2 is connected with the CPLD3 through an I2C bus and is used for transmitting a control signal to the CPLD3 according to a control instruction; the CPLD3 is respectively in signal connection with each VR chip 4 and is used for controlling the power-on time sequence of the VR chip according to the power-on control logic and starting the debugging function to suspend the power-on time sequence of the VR chip 4 according to the control signal.
The CPLD3 controls the power-on of the VR chip 4 by sending an enable signal EN to the VR chip 4, and the feedback signal PWRGD is sent to the CPLD3 after 4 powers on the VR chip. The enable signal EN and the feedback signal PWRGD are both active at high level. The I2C bus includes a serial data line SDA and a serial clock line SCL for cooperating with the power-on control logic of the CPLD3 to suspend the power-on timing of the VR chip 4 by the debugging function.
Based on the connection relationship, the control terminal 1 is configured to determine a corresponding mark according to the VR chip 4 to be observed, generate a control instruction according to the mark of the VR chip 4, and send the control instruction to the BMC 2, and is further configured to send a recovery signal to the CPLD3 when the power-on control logic is in a suspended execution state.
The CPLD3 is used for adding a mark of the VR chip 4 into the power-on control logic and storing the mark; and the power-on timing sequence of the VR chip 4 is controlled according to the power-on control logic, the VR chip 4 which is powered on is determined according to the mark of the VR chip 4, and the execution of the power-on control logic is suspended through a debugging function after the VR chip 4 to be observed is powered on.
CPLD3 is specifically used for: when programming the power-on control logic, sequencing the power-on time sequences of all VR chips 4, sequentially marking the VR chips 4 in a digital form, and storing the marked power-on control logic in an internal register of the CPLD 3.
In addition, when the mainboard power-on control system is designed, an additional I/O port can be selected in the CPLD3 to control the on-off state of the debugging function and the on-off state of the specified level, but this method not only wastes the I/O resources of the CPLD, but also needs additional hardware equipment. In this embodiment, the control signal is transmitted through one I2C bus, and only two signal lines SCL and SDA are needed, so that the debugging function can be completed by matching with the internal logic of the CPLD. The BMC is used as a host to send commands, and the CPLD is used as a slave to receive commands and execute control actions. BMC has more external interfaces, can conveniently adjust in order to satisfy user's demand, and in the connected mode with control terminal, this embodiment uses BMC's serial ports, directly links to each other with control terminal through external hardware circuit and hardware equipment, realizes plug-and-play.
The embodiment provides a mainboard power-on control system, which can sequence the levels generated by a VR chip, add a debugging function in a CPLD, selectively gate a part of enabling signals, conveniently generate a working level meeting the observation purpose, and effectively solve the problem that in the debugging process of a mainboard, the CPLD codes are frequently changed for observing a specific level state.
Example two:
based on the first embodiment, as shown in fig. 2, this embodiment further discloses a motherboard power-on control method, which includes the following steps:
s1: and adding a mark of the VR chip into the power-on control logic through the CPLD, and storing the mark.
When the CPLD writes the power-on control logic, the power-on time sequences of all VR chips are sequenced, and the VR chips are marked in sequence in a digital form. The marked power-on control logic is then saved in an internal register of the CPLD.
S2: and the control terminal determines a corresponding mark according to the VR chip to be observed, generates a control instruction according to the mark of the VR chip and sends the control instruction to the BMC.
S3: and the BMC generates a control signal according to the control instruction and sends the control signal to the CPLD.
The BMC is connected with the CPLD through an I2C bus, the I2C bus comprises a serial data line SDA and a serial clock line SCL, and the serial data line SDA and the serial clock line SCL are used for being matched with the power-on control logic of the CPLD and suspending the power-on time sequence of the VR chip through the debugging function.
S4: and the CPLD controls the power-on time sequence of the VR chip according to the power-on control logic, and determines the powered-on VR chip according to the mark of the VR chip.
And determining the powered-on VR chip by a feedback signal PWRGD sent by the VR chip to the CPLD, wherein if the feedback signal PWRGD is at a high level, the powered-on VR chip is powered on. Similarly, whether the VR chip executes the power-on control logic is controlled by an enable signal EN sent by the CPLD to the VR chip, and if the enable signal EN sent by the CPLD to the VR chip is in a high level, the VR chip executes the power-on control logic of the CPLD.
S5: and if the VR chip to be observed currently is powered on, the execution of the power-on control logic is suspended by starting the debugging function.
The method specifically comprises the following steps: after the power-on of the VR chip to be observed is finished, the feedback signal PWRGD sent to the CPLD by the VR chip to be observed is in a high level, after the CPLD receives the high-level feedback signal PWRGD sent by the VR chip to be observed, the execution of the power-on control logic is suspended, the low-level enable signal EN is sent to the VR chip which is not powered on, and the enable signal EN of the VR chip which is not powered on is enabled to be invalid.
S6: when the power-on control logic is in a suspended execution state, a recovery signal is sent to the CPLD through the control terminal, after the CPLD receives the recovery signal, a high-level enabling signal EN is sent to the VR chip which is not powered on, the enabling signal EN of the VR chip which is not powered on is effective, and the power-on control logic is continuously executed.
The embodiment provides a mainboard power-on control method, which is characterized in that a control terminal connected with a BMC (baseboard management controller) is used for sending an instruction to control a CPLD (complex programmable logic device) to generate an effective level signal of a specified time sequence, and then the execution of a power-on control logic is suspended after the specified level is generated, so that the control signal of a VR (virtual reality) chip is selectively controlled to be effective on the basis of keeping the original logic in the CPLD unchanged, and further the power-on time sequence is controlled to be suspended at a certain stage. According to the embodiment, the power-on sequence of the level can be observed and adjusted and the system power supply test can be carried out without modifying the power-on control logic.
Example three:
based on the foregoing embodiment, this embodiment discloses a motherboard power-on control method, which includes:
1. when the CPLD writes the power-on electric control logic, the power-on time sequences of the VR chips are sequenced, marked in sequence in a digital mode and stored in an internal register.
2. When a user needs to use the debugging function, the control terminal selects the switch state of a specific level and selects a specific identifier corresponding to the level. When the CPLD controls power-on, the control signals before the level are enabled to be effective in sequence according to a preset power-on control logic, when the power-on of the level is completed, the VR chip sends back a feedback signal (PWRGD high level), and after the CPLD recognizes that the specified level is successfully powered on, the control signals after the level are disabled, namely before a user does not send a next instruction, the effective signals of the level after the level are not sent.
As shown in fig. 3 in particular, the user sets the observation target to the level generated by the kth VR chip. At the moment, when the power-on control logic operates, the VR chips with the power-on sequence before k work normally to generate working electricity in a corresponding state; and the VR chip and the CPLD which are electrified sequentially after k are invalid with the connected enable signals, and the VR chip does not generate corresponding levels.
3. If the user needs to observe a certain level state after the level, the control terminal resends the control instruction, the enable signal before the level is enabled again, and the enable signal after the level is disabled; if the user does not need to debug the power-on state or finishes the debugging work, the debugging function can be quitted by directly inputting a command through the control terminal, and the CPLD internal logic returns to the normal power-on control logic until the next instruction for starting the debugging function comes.
Example four:
the embodiment discloses a mainboard power-on control device, which comprises a processor and a memory; when the processor executes the mainboard power-on control program stored in the memory, the following steps are realized:
1. and adding a mark of the VR chip into the power-on control logic through the CPLD, and storing the mark.
2. And the control terminal determines a corresponding mark according to the VR chip to be observed, generates a control instruction according to the mark of the VR chip and sends the control instruction to the BMC.
3. And the BMC generates a control signal according to the control instruction and sends the control signal to the CPLD.
4. And the CPLD controls the power-on time sequence of the VR chip according to the power-on control logic, and determines the powered-on VR chip according to the mark of the VR chip.
5. And if the VR chip to be observed currently is powered on, the execution of the power-on control logic is suspended through the debugging function.
6. When the power-on control logic is in a suspended execution state, a recovery signal is sent to the CPLD through the control terminal, after the CPLD receives the recovery signal, a high-level enabling signal EN is sent to the VR chip which is not powered on, the enabling signal EN of the VR chip which is not powered on is effective, and the power-on control logic is continuously executed.
Further, the power-on control device for the motherboard in this embodiment may further include:
and the input interface is used for acquiring a mainboard electrifying control program led in by the outside, storing the acquired mainboard electrifying control program into the memory, and also used for acquiring various instructions and parameters transmitted by the outside terminal equipment and transmitting the instructions and parameters to the processor, so that the processor utilizes the instructions and the parameters to perform corresponding processing. In this embodiment, the input interface may specifically include, but is not limited to, a USB interface, a serial interface, a voice input interface, a fingerprint input interface, a hard disk reading interface, and the like.
And the output interface is used for outputting various data generated by the processor to the terminal equipment connected with the output interface, so that other terminal equipment connected with the output interface can acquire various data generated by the processor. In this embodiment, the output interface may specifically include, but is not limited to, a USB interface, a serial interface, and the like.
And the communication unit is used for establishing remote communication connection between the mainboard power-on control device and the external server so that the mainboard power-on control device can mount the mirror image file into the external server. In this embodiment, the communication unit may specifically include, but is not limited to, a remote communication unit based on a wireless communication technology or a wired communication technology.
And the keyboard is used for acquiring various parameter data or instructions input by a user through real-time key cap knocking.
And the display is used for displaying relevant information in the short circuit positioning process of the power supply line of the running server in real time.
The mouse can be used for assisting a user in inputting data and simplifying the operation of the user.
The embodiment provides a mainboard power-on control device, which can sequence the levels generated by a VR chip, add a debugging function in a CPLD, selectively gate a part of enabling signals, conveniently generate a working level meeting the observation purpose, and effectively solve the problem that in the debugging process of a mainboard, the CPLD codes need to be frequently changed for observing a specific level state.
Example five:
the present embodiments also disclose a readable storage medium, where the readable storage medium includes Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable hard disk, a CD-ROM, or any other form of storage medium known in the art. The readable storage medium stores a mainboard power-on control program, and the mainboard power-on control program realizes the following steps when being executed by the processor:
1. and adding a mark of the VR chip into the power-on control logic through the CPLD, and storing the mark.
2. And the control terminal determines a corresponding mark according to the VR chip to be observed, generates a control instruction according to the mark of the VR chip and sends the control instruction to the BMC.
3. And the BMC generates a control signal according to the control instruction and sends the control signal to the CPLD.
4. And the CPLD controls the power-on time sequence of the VR chip according to the power-on control logic, and determines the powered-on VR chip according to the mark of the VR chip.
5. And if the VR chip to be observed currently is powered on, the execution of the power-on control logic is suspended through the debugging function.
6. When the power-on control logic is in a suspended execution state, a recovery signal is sent to the CPLD through the control terminal, after the CPLD receives the recovery signal, a high-level enabling signal EN is sent to the VR chip which is not powered on, the enabling signal EN of the VR chip which is not powered on is effective, and the power-on control logic is continuously executed.
The embodiment provides a readable storage medium, which can utilize a control terminal connected with a BMC to send an instruction, control a CPLD to generate a level effective signal of a specified time sequence, and then suspend execution of a power-on control logic after the specified level is generated, so that on the basis of keeping the original logic in the CPLD unchanged, a VR chip control signal is selectively controlled to be effective, and then the power-on time sequence is suspended at a certain stage.
In summary, the invention can selectively control the VR chip to control the signal to be effective on the basis of keeping the original logic in the CPLD unchanged, thereby controlling the power-on sequence to be suspended at a certain stage, and facilitating the system debugging.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The method disclosed by the embodiment corresponds to the system disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the description of the method part.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided by the present invention, it should be understood that the disclosed system, system and method can be implemented in other ways. For example, the above-described system embodiments are merely illustrative, and for example, the division of the units is only one logical functional division, and other divisions may be realized in practice, for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, systems or units, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit.
Similarly, each processing unit in the embodiments of the present invention may be integrated into one functional module, or each processing unit may exist physically, or two or more processing units are integrated into one functional module.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The mainboard power-on control system, method, device and readable storage medium provided by the invention are described in detail above. The principles and embodiments of the present invention are explained herein using specific examples, which are presented only to assist in understanding the method and its core concepts. It should be noted that, for those skilled in the art, it is possible to make various improvements and modifications to the present invention without departing from the principle of the present invention, and those improvements and modifications also fall within the scope of the claims of the present invention.

Claims (10)

1. A mainboard power-on control system, comprising: the system comprises a control terminal, a BMC, a CPLD and a plurality of VR chips;
the control terminal is in signal connection with the BMC through a serial port and is used for sending a control instruction;
the BMC is connected with the CPLD through an I2C bus and is used for transmitting a control signal to the CPLD according to a control instruction;
the CPLD is respectively in signal connection with each VR chip and is used for controlling the power-on time sequence of the VR chip according to the power-on control logic and starting the debugging function to suspend the power-on time sequence of the VR chip according to the control signal.
2. The mainboard power-on control system of claim 1, wherein the CPLD controls the VR chip to be powered on by sending an enable signal EN to the VR chip, and the VR chip sends a feedback signal PWRGD to the CPLD after being powered on.
3. The power-on control system for mainboard of claim 1, wherein the I2C bus includes a serial data line SDA and a serial clock line SCL, for cooperating with the power-on control logic of the CPLD to suspend the power-on timing of the VR chip through the debugging function.
4. The system according to claim 2, wherein the enable signal EN and the feedback signal PWRGD are both active high.
5. A mainboard power-on control method is characterized by comprising the following steps:
adding a mark of a VR chip into the power-on control logic through the CPLD, and storing the mark;
the control terminal determines a corresponding mark according to the VR chip to be observed, and generates a control instruction according to the mark of the VR chip to be sent to the BMC;
the BMC generates a control signal according to the control instruction and sends the control signal to the CPLD;
the CPLD controls the power-on time sequence of the VR chip according to the power-on control logic, and determines the powered-on VR chip according to the mark of the VR chip;
and if the VR chip to be observed currently is powered on, the execution of the power-on control logic is suspended through the debugging function.
6. The motherboard power-on control method according to claim 5, wherein the adding of the mark of the VR chip into the power-on control logic through the CPLD and the saving specifically include:
when the CPLD writes the power-on control logic, sequencing the power-on time sequences of all VR chips, sequentially marking the VR chips in a digital form, and storing the marked power-on control logic in an internal register of the CPLD.
7. The motherboard power-on control method as claimed in claim 5, wherein the VR chip to be observed currently is powered on, and the suspending of the execution of the power-on control logic by the debug function specifically comprises:
after the power-on of the VR chip to be observed is finished, the feedback signal PWRGD sent to the CPLD by the VR chip to be observed is in a high level, after the CPLD receives the high-level feedback signal PWRGD sent by the VR chip to be observed, the execution of the power-on control logic is suspended, the low-level enable signal EN is sent to the VR chip which is not powered on, and the enable signal EN of the VR chip which is not powered on is enabled to be invalid.
8. The power-on control method for a motherboard according to claim 5, further comprising:
when the power-on control logic is in a suspended execution state, a recovery signal is sent to the CPLD through the control terminal, after the CPLD receives the recovery signal, a high-level enabling signal EN is sent to the VR chip which is not powered on, the enabling signal EN of the VR chip which is not powered on is effective, and the power-on control logic is continuously executed.
9. A power-on control device for a motherboard, comprising:
the memory is used for storing a mainboard power-on control program;
a processor, configured to implement the steps of the motherboard power-on control method according to any one of claims 5 to 8 when executing the motherboard power-on control program.
10. A readable storage medium, characterized by: the readable storage medium stores a motherboard power-on control program, and the motherboard power-on control program, when executed by the processor, implements the steps of the motherboard power-on control method according to any one of claims 5 to 8.
CN202110722505.9A 2021-06-28 2021-06-28 Mainboard power-on control system, method and device and readable storage medium Active CN113625854B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110722505.9A CN113625854B (en) 2021-06-28 2021-06-28 Mainboard power-on control system, method and device and readable storage medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110722505.9A CN113625854B (en) 2021-06-28 2021-06-28 Mainboard power-on control system, method and device and readable storage medium

Publications (2)

Publication Number Publication Date
CN113625854A true CN113625854A (en) 2021-11-09
CN113625854B CN113625854B (en) 2023-08-15

Family

ID=78378500

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110722505.9A Active CN113625854B (en) 2021-06-28 2021-06-28 Mainboard power-on control system, method and device and readable storage medium

Country Status (1)

Country Link
CN (1) CN113625854B (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI810984B (en) * 2022-06-22 2023-08-01 立端科技股份有限公司 Power sequence control system and electronic device having the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104484248A (en) * 2014-11-28 2015-04-01 英业达科技有限公司 Diagnosis method and device for electrifying fault of computer motherboard
CN105160255A (en) * 2015-08-06 2015-12-16 浪潮电子信息产业股份有限公司 Trustworthy measurement apparatus and method

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104484248A (en) * 2014-11-28 2015-04-01 英业达科技有限公司 Diagnosis method and device for electrifying fault of computer motherboard
CN105160255A (en) * 2015-08-06 2015-12-16 浪潮电子信息产业股份有限公司 Trustworthy measurement apparatus and method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI810984B (en) * 2022-06-22 2023-08-01 立端科技股份有限公司 Power sequence control system and electronic device having the same

Also Published As

Publication number Publication date
CN113625854B (en) 2023-08-15

Similar Documents

Publication Publication Date Title
KR20120096858A (en) Remote wakeup of application processor of mobile device
CN104698950A (en) Peripheral device control method, microcontroller, upper computer and system
CN109542465B (en) Data writing method, system, device, equipment and medium of integrated circuit chip
CN111475362B (en) Multi-core isomorphic DSP processor test system and method
CN114237676A (en) FPGA (field programmable Gate array) logic updating method, device, equipment and readable storage medium
CN113625854A (en) Mainboard power-on control system, method and device and readable storage medium
TW201319601A (en) Testing method and apparatus applied to IP phone system
CN111830390B (en) Test method and related product
CN109901664B (en) Method, apparatus, system, device and readable storage medium for providing clock signal
EP2784901B1 (en) Universal serial bus chargers and charging management methods
CN103580975A (en) On-line reconfigurable generalized bus data conversion method
CN115562738B (en) Port configuration method, component and hard disk expansion device
CN116302921A (en) Chip function debugging method and device, electronic equipment and storage medium
CN112564924B (en) Computer expansion card and block chain terminal equipment
CN109753472B (en) Data processing method and device
Bhatt et al. Design of a controller for a universal input/output port
CN103983864A (en) Device used for graphic-card testing
CN113900718A (en) Method, system and device for decoupling asset information of BMC (baseboard management controller) and BIOS (basic input/output system)
JP2003122594A (en) Semiconductor device and evaluation tool
CN111857310A (en) Power supply system and method for components
CN115373646A (en) Information expansion method, device and related product
CN114121138B (en) Memory voltage testing method, device, computing equipment and system
CN210605428U (en) Novel combinational logic loop analysis device
CN115599191B (en) Power-on method and power-on device of intelligent network card
CN115237849B (en) Dynamically reconfigurable and heterogeneous computing module and computing device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant