CN113611257A - 显示设备 - Google Patents

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Publication number
CN113611257A
CN113611257A CN202110936272.2A CN202110936272A CN113611257A CN 113611257 A CN113611257 A CN 113611257A CN 202110936272 A CN202110936272 A CN 202110936272A CN 113611257 A CN113611257 A CN 113611257A
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China
Prior art keywords
transistor
output
voltage
stage
gate
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CN202110936272.2A
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CN113611257B (zh
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李贤准
安部胜美
李永旭
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
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    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
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    • G09G3/3611—Control of matrices with row and column drivers
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Abstract

本发明提供一种显示设备，包括：显示区，包括栅极线和数据线；以及栅极驱动器，连接至所述栅极线的一端，所述栅极驱动器包括集成在基板上并被配置为输出栅极电压的级，其中所述级包括输入单元和输出单元，其中所述输出单元包括第一晶体管和第一电容器，其中所述第一晶体管包括被配置为接收时钟信号的输入端、连接至所述输入单元的节点的控制端以及连接至被配置为输出所述栅极电压的栅极电压输出端的输出端，其中所述输入单元包括第二晶体管，并且其中所述第二晶体管包括输入端和共同连接至所述第二晶体管的所述输入端的第一控制端、被配置为接收来自低电压输入端的低电压的第二控制端以及连接至所述第一晶体管的所述控制端的输出端。

Description

显示设备
本申请是于2016年3月24日提交的申请号为201610172981.7、标题为“薄膜晶体管阵列面板及其制造方法”的专利申请的分案申请。
相关申请的交叉引用
本申请要求2015年3月24日提交的韩国专利申请No.10-2015-0040853的优先权和权益，由此为所有目的通过引用合并该韩国专利申请，如同完全在本文中阐述一样。
技术领域
示例性实施例涉及薄膜晶体管阵列面板和制造该薄膜晶体管阵列面板的方法。
背景技术
液晶显示器(LCD)是目前使用的平板显示器的最常见类型之一，其包括具有诸如像素电极和公共电极等的场生成电极的两片阵列面板。液晶层介于这两片阵列面板之间。液晶显示器通过向场生成电极施加电压而在液晶层中生成电场。液晶显示器通过所生成的电场确定液晶层的液晶分子的取向，并控制入射光的偏振，从而显示图像。
这种显示设备包括像素和不同类型的驱动器，每个像素是用于显示图像的单元。驱动器包括用于向像素施加数据电压的数据驱动器，以及施加对数据电压的传输进行控制的栅极信号的栅极驱动器。传统上，栅极驱动器和数据驱动器作为芯片被安装在印刷电路板(PCB)上。因此，以芯片安装的栅极驱动器和数据驱动器直接被安装在阵列面板上。最近，在栅极驱动器不要求薄膜晶体管的沟道的高迁移率时，制造商一直在开发集成在阵列面板上的(即，不作为分立的芯片形成的)栅极驱动器。作为集成栅极驱动器而不是形成分立栅极驱动芯片的结果，因为存在更少的制造步骤，制造商的成本降低。附加优势是，栅极驱动器可以由包括氧化物半导体的薄膜晶体管形成，氧化物半导体使用具有比大多数材料高的电子迁移率的金属氧化物。
栅极驱动器可以包括多个氧化物半导体薄膜晶体管。在一部分氧化物半导体薄膜晶体管中，高电压被施加于源电极和漏电极之间或者栅电极和源电极之间。相应地，形成引起热载流子的高电场，从而引起电荷捕获的产生。此外，高电场引起电流通过薄膜晶体管而泄露。
在本背景技术部分中公开的上述信息仅仅用于加深本发明构思的背景的理解，并且因此其可以包含不形成在本国对于本领域普通技术人员已知的现有技术的信息。
发明内容
示例性实施例提供一种可以防止泄漏电流的薄膜晶体管阵列面板及其制造方法。
示例性实施例还提供一种可以防止薄膜晶体管劣化的薄膜晶体管阵列面板及其制造方法。
附加方面将在下面的详细描述中阐述并且将部分地根据本公开显而易见，或者可以通过本发明构思的实践来领会。
示例性实施例公开一种薄膜晶体管阵列面板，包括：基板；设置在所述基板上的第一栅电极；设置在所述基板上的电压导线；设置在所述第一栅电极和所述电压导线上的栅绝缘层；设置在所述栅绝缘层上的包括氧化物半导体材料的半导体图案；以一距离彼此相隔地设置在所述半导体图案上的源电极和漏电极；设置在所述源电极和所述漏电极上的第一钝化层；以及设置在所述第一钝化层上并且与所述电压导线连接的第一电极。
示例性实施例还公开一种用于制造薄膜晶体管阵列面板的方法。该方法包括：在基板上设置第一栅电极和电压导线；在所述第一栅电极和所述电压导线上设置栅绝缘层；在所述栅绝缘层栅上设置包括氧化物半导体材料的半导体图案；在所述半导体图案上以一距离彼此相隔地设置源电极和漏电极；在所述源电极和所述漏电极上设置第一钝化层；以及在所述第一钝化层上设置与所述电压导线连接的第一电极。
前面的概括描述和下面的详细描述是示例性和说明性的，并且旨在提供所要求保护的主题的进一步解释。
附图说明
为提供本发明构思的进一步理解而包括并且合并在本说明书中且构成本说明书的一部分的附图，图示了本发明构思的示例性实施例，并且与描述一起用来解释本发明构思的原理。
图1是根据示例性实施例的显示设备的俯视图。
图2是图1的示例性实施例中的栅极驱动器和栅极线的详细框图。
图3是根据图2的示例性实施例的栅极驱动器中的一个级的放大电路图。
图4是根据示例性实施例的包括在一级中的薄膜晶体管的剖视图。
图5、图6、图7和图8是根据图4的示例性实施例的薄膜晶体管的制造方法的过程剖视图。
图9是根据另一示例性实施例的包括在一级中的薄膜晶体管的剖视图。
图10和图11是图示根据施加至根据示例性实施例的薄膜晶体管的第一电极的电压而确定的电流的图。
图12是图示根据施加至根据示例性实施例的薄膜晶体管的第一电极的变化的电压而确定的电流的图。
具体实施方式
在下面的描述中，为了解释的目的，阐述了许多具体细节，以便提供各个示例性实施例的全面理解。然而，应当清楚，在没有这些具体细节或者有一个或多个等价布置的情况下，也可以实施各个示例性实施例。在其它实例中，以框图形式示出众所周知的结构和设备，以便避免不必要地模糊各个示例性实施例。
在附图中，为了清楚和描述的目的，可以放大层、膜、面板、区域等的尺寸和相对尺寸。此外，相同的附图标记表示相同的元件。
当将一元件或层称为“位于另一元件或层上”、“连接至另一元件或层”或“耦接至另一元件或层”时，该元件或层可以直接位于另一元件或层上、直接连接至另一元件或层或直接耦接至另一元件或层，或者可以存在中间的元件或层。然而，当将一元件或层称为“直接位于另一元件或层上”、“直接连接至另一元件或层”或“直接耦接至另一元件或层”时，不存在中间的元件或层。为了本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z组成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z，或X、Y和Z中两个或更多个的任意组合，比如说例如XYZ、XYY、YZ和ZZ。在全文中，相同的附图标记指示相同的元件。本文中使用的术语“和/或”包括关联列出的项目中的一个或多个项目的任意组合和所有组合。
虽然在本文中可以使用术语第一、第二等来描述不同元件、部件、区域、层和/或部分，但这些元件、部件、区域、层和/或部分不应被这些术语限制。这些术语用于将一个元件、部件、区域、层和/或部分与另一元件、部件、区域、层和/或部分区分开。因此，在不背离本公开的教导的情况下，下面讨论的第一元件、部件、区域、层和/或部分可以被称为第二元件、部件、区域、层和/或部分。
为了描述性目的，本文中可以使用与空间有关的术语，如“下面”、“下方”、“下”、“上方”和“上”等，并由此来描述附图中图示的一个元件或特征与其它元件或特征的关系。空间相关的术语旨在涵盖装置在使用时、在操作时和/或在制造时除附图中描绘的朝向以外的不同朝向。例如，如果图中的装置被翻转，那么被描述为位于其它元件或特征“下方”或“下面”的元件将位于其它元件或特征的“上方”。因此，示例性术语“下方”可以涵盖上方和下方两个朝向。此外，装置可以朝向别的方向(例如，旋转90度或朝其它朝向)，并且因此相应地解释本文中使用的空间相关描述符。
本文中使用的术语仅仅是为了描述具体实施例的目的，而不旨在作为限制。本文中使用的单数形式“一”、“一个”和“该”旨在也包含复数形式，除非上下文清楚地给出其它指示。此外，术语“包括”和/或“包含”在本说明书中使用时，指明所述的特征、整数、步骤、操作、元件、部件和/或它们的组合的存在，但不排除存在或增加一个或多个其它特征、整数、步骤、操作、元件、部件和/或它们的组合。
本文中参考是理想化示例性实施例和/或中间结构的示意性图示的剖面图来描述各个示例性实施例。因此，应预期由于例如制造技术和/或公差而导致的图示形状的变化。因此，本文中公开的示例性实施例不应当被解释为局限于所图示的区域的特定形状，而是应包括由于例如制造而导致的形状偏差。例如，被图示为矩形的注入区域通常将具有圆角特征或弯曲特征，和/或在其边缘处具有注入浓度梯度，而不是从注入区域至未注入区域的二元改变。类似地，通过注入形成的掩埋区域可能在该掩埋区域和发生注入所通过的表面之间的区域中导致一些注入。因此，附图中图示的区域本质上是示意性的，且它们的形状不旨在图示器件的区域的实际形状并且不旨在作为限制。
除非另外限定，否则本文中使用的所有术语(包括技术术语和科学术语)具有与本公开是其一部分的领域中的普通技术人员所通常理解的含义相同的含义。术语，如在常用词典中定义的那些术语，应当被解释为具有与它们在相关领域的背景中的含义一致的含义，而不是从理想化的或过于形式的意义上去解释，除非本文中明确如此定义。
形成显示设备的晶体管被示例性地描述为N型金属氧化物半导体(NMOS)晶体管。
图1是根据示例性实施例的显示设备100的俯视图。参考图1，显示设备100可以包括显示图像的显示区300和向显示区300的栅极线G1至Gn供应栅极电压的栅极驱动器500。
显示设备可以包括向显示区300的数据线D1至Dm供应数据电压的数据驱动器集成电路(IC)460。数据驱动器IC 460可以形成在诸如柔性印刷电路(FPC)膜450的膜上。
数据驱动器IC 460和栅极驱动器500可以由信号控制器600控制。柔性印刷电路膜450可以电连接至印刷电路板(PCB)400。来自信号控制器600的信号可以通过印刷电路板400和柔性印刷电路膜450传输至数据驱动器IC 460和栅极驱动器500。
信号控制器600可以向数据驱动器IC 460、栅极驱动器500和显示区300供应信号(即，时钟信号CKV和CKVB及扫描开始信号STVP)和预定电平的低电压Vss1和Vss2。
显示区300可以包括像素PX。当显示设备100是液晶显示器时，每个像素PX可以包括薄膜晶体管Trsw、液晶电容器Clc和存储电容器Cst。薄膜晶体管Trsw的控制端连接至一条栅极线，薄膜晶体管Trsw的输入端连接至一条数据线，并且薄膜晶体管Trsw的输出端连接至液晶电容器Clc的第一端和存储电容器Cst的第一端。
液晶电容器Clc的第二端可以连接至公共电极(未示出)，并且存储电容器Cst的第二端可以接收从信号控制器600施加的存储电压(未示出)。液晶显示器的像素PX的结构可以由各种示例性实施例实现。在图1中，还可以应用具有除所图示的像素PX的基本结构以外的构造的像素PX。
图1将液晶显示器图示为显示设备100。然而，显示设备100可以是有机发光显示设备。作为有机发光显示设备，像素PX可包括薄膜晶体管和有机发光二极管。其他显示设备形成包括诸如薄膜晶体管的元件的显示区300。为了简便，贯穿本申请将显示设备描述为液晶显示器。然而，每个示例性实施例可以被实现为有机发光显示设备或任何其它适合的显示设备。
显示区300包括栅极线G1至Gn和数据线D1至Dm。栅极线G1至Gn和数据线D1至Dm以绝缘的方式彼此交叉。
数据驱动器IC 460可以设置在显示设备100的上侧或下侧，并且连接至沿基本竖直方向延伸的数据线D1至Dm。图1图示数据驱动器IC 460被设置在显示设备100的上侧的示例性实施例。
栅极驱动器500可以接收时钟信号CKV和CKVB、扫描开始信号STVP、与栅极截止电压对应的第一低电压Vss1、以及比栅极截止电压低的第二低电压Vss2。栅极驱动器500可以生成栅极电压(栅极导通电压和栅极截止电压)，并且可以向栅极线G1至Gn顺序地施加栅极导通电压。
如图1所示，时钟信号CKV和CKVB、扫描开始信号STVP、第一低电压Vss1和第二低电压Vss2可以通过数据驱动器IC 460所处的柔性印刷电路膜450中与栅极驱动器500最近的柔性印刷电路膜450施加至栅极驱动器500。这些信号通过印刷电路板400从外部源或信号控制器600传输至诸如柔性印刷电路膜450的膜。
图2是根据示例性实施例的图示栅极驱动器500和栅极线G1至Gn的详细框图。
在图2中，显示区300被图示为寄生电阻Rp和寄生电容Cp。这等效地表示出栅极线G1至Gn的寄生电阻Rp和耦接至栅极线G1至Gn的寄生电容Cp。
栅极驱动器500可以包括可相关地彼此连接的多个级SR1、SR2、SR3、SR4、……。级SR1、SR2、SR3、SR4、……中的每个级可以包括三个输入端IN1、IN2和IN3，一个时钟输入端CK，两个电压输入端Vin1和Vin2，输出栅极电压的栅极电压输出端OUT，传输信号输出端CRout，以及反相器信号输出端IVTout。
第一输入端IN1可以连接至前一级的传输信号输出端CRout，并且可以从前一级接收传输信号CR。例如，第二级SR2从第一级SR1的传输信号输出端CRout接收传输信号CR。由于第一级SR1没有前一级，所以第一级SR1可以通过第一级的第一输入端IN1接收扫描开始信号STVP。
第二输入端IN2可以连接至下一级的传输信号输出端CRout，并且可以从下一级接收传输信号CR。例如，第一级SR1从第二级SR2的传输信号输出端CRout接收传输信号CR。
连接至第n-1条栅极线Gn-1的级SRn-1(未示出)和连接至第n条栅极线Gn的级SRn(未示出)可以形成两个虚设级。SRn-1虚设级可以从下一级接收传输信号CR，并且可以向下一级传输传输信号CR。SRn虚设级可以从前一级接收传输信号CR，并且向前一级传输传输信号CR。
与其它级不同，虚设级SRn+1和SRn+2(未示出)可以生成虚设栅极电压，并且可以输出虚设栅极电压。更具体地，从其它级SR1至SRn输出的栅极电压可以通过栅极线传输，并且数据电压被施加给像素，从而显示图像。然而，虚设级SRn+1和SRn+2可以不连接至栅极线。即便虚设级SRn+1和SRn+2与栅极线连接，栅极线也可以不被用于图像的显示，因为它们与不显示图像的虚设像素(未示出)连接。
第三输入端IN3可以连接至前一级的反相器信号输出端IVTout，并且可以接收前一级的反相器信号IVT。例如，第二级SR2可以从第一级SR1从反相器信号输出端IVTout接收反相器信号IVT。由于第一级SR1之前不存在前一级，所以可以附加地生成对应信号然后将其输入第一级SR1，或者可以控制虚设级SRn+1和SRn+2(未示出)生成在时序上合适的信号，然后将该信号输入第一级SR1。换句话说，当在对应级中施加栅极导通电压时，可以向第一级SR1的第三输入端IN3施加输出控制信号OCS。输出控制信号OCS可以具有与低电压(Vss1或Vss2)的施加相同的时序。
可以向每一级SR1、SR2、SR3和SR4的时钟输入端CK输入时钟信号。可以将第一时钟信号CKV施加至奇数级(即，第一级SR1和第三级SR3)的时钟输入端CK，可以将第二时钟信号CKVB施加至偶数级(即，第二级SR2和第四级SR4)的时钟输入端CK。第一时钟信号CKV和第二时钟信号CKVB可以具有相反的相位。
可以向每一级(即，级SR1、SR2、SR3和SR4)的第一电压输入端Vin1施加与栅极截止电压对应的第一低电压Vss1。可以向每一级的第二电压输入端Vin2施加具有比第一低电压Vss1更低的电压的第二低电压Vss2。第一低电压Vss1和第二低电压Vss2的电压值可以根据示例性实施例而变化。作为一个示例，第一低电压Vss1使用-6V，而第二低电压Vss2使用-10V。换言之，第二低电压Vss2低于第一低电压Vss1。
将描述栅极驱动器500的操作。
第一级SR1可以通过时钟输入端CK接收第一时钟信号CKV。第一级SR1还可以通过第一输入端IN1接收扫描开始信号STVP。第一级SR1还可以分别通过第一电压输入端Vin1和第二电压输入端Vin2接收第一低电压Vss1和第二低电压Vss2。此外，第一级SR1可以通过第二输入端IN2接收从第二级SR2供应的传输信号CR，并且可以通过第三输入端IN3接收输出控制信号OCS。
第一级SR1可以根据接收到的信号CKV、STVP、Vss1、Vss2、CR和OCS通过栅极电压输出端OUT向第一栅极线G1输出栅极导通电压。此外，第一级SR1可以从传输信号输出端CRout输出传输信号CR，并且可以将传输信号CR传输至第二级SR2的第一输入端IN1。第一级SR1还可以从反相器信号输出端IVTout向第二级SR2的第三输入端IN3传输反相器信号IVT。
第二级SR2可以通过时钟输入端CK接收第二时钟信号CKVB。此外，第二级SR2可以通过第一输入端IN1接收第一级SR1的传输信号CR。第二级可以分别通过第一电压输入端Vin1和第二电压输入端Vin2接收第一低电压Vss1和第二低电压Vss2。第二级SR2还可以通过第二输入端IN2接收从第三级SR3的传输信号输出端CRout供应的传输信号CR。第二级SR2可以进一步通过第三输入端IN3接收从第一级SR1的反相器信号输出端IVTout供应的反相器信号IVT。
第二级SR2可以根据接收到的信号CKVB、Vss1、Vss2、CR和IVT通过栅极电压输出端OUT向第二栅极线G2输出栅极导通电压。此外，第二级SR2可以从第二级SR2的传输信号输出端CRout输出传输信号CR，然后向第三级SR3的第一输入端IN1和第一级SR1的第二输入端IN2传输传输信号CR。第二级SR2可以从反相器信号输出端IVTout输出反相器信号IVT，然后向第三级SR3的第三输入端IN3传输反相器信号IVT。
第三级SR3可以通过时钟输入端CK接收从外部源供应的第一时钟信号CKV。第三级SR3还可以通过第一输入端IN1从第二级SR2的传输信号输出端CRout接收传输信号CR。第三级SR3还可以分别通过第一电压输入端Vin1和第二电压输入端Vin2接收第一低电压Vss1和第二低电压Vss2。第三级SR3可以通过第二输入端IN2接收从第四级SR4的传输信号输出端CRout供应的传输信号CR。第三级SR3可以通过第三输入端IN3接收从第二级SR2的反相器信号输出端IVTout供应的反相器信号IVT。
第三级SR3可以通过栅极电压输出端OUT向第三栅极线G3输出栅极导通电压。第三级SR3可以通过传输信号输出端CRout输出传输信号CR，并且向第四级SR4的第一输入端IN1和第二级SR2的第二输入端IN2传输传输信号CR。此外，第三级SR3可以通过反相器信号输出端IVTout向第四级SR4的第三输入端IN3传输反相器信号IVT。
第四级SR4与第二级SR2类似。因此，为了简洁，将不描述第四级。
通过使用上述方法，第n级可以通过时钟输入端CK接收从外部源供应的第二时钟信号CKVB。第n级可以通过第一输入端IN1接收第n-1级SR(n-1)的传输信号CR。第n级可以分别通过第一电压输入端Vin1和第二电压输入端Vin2接收第一低电压Vss1和第二低电压Vss2。第n级可以通过第二输入端IN2接收从第n+1级SR(n+1)(即，虚设级)供应的传输信号CR。第n级可以通过第三输入端IN3接收从第n-1级SR(n-1)供应的反相器信号IVT。第n级可以通过栅极电压输出端OUT向第n条栅极线Gn输出栅极导通电压。第n级可以从传输信号输出端CRout输出传输信号CR，并且向第n+1级SR(n+1)(即，虚设级)的第一输入端IN1和第n-1级SR(n-1)的第二输入端IN2传输传输信号CR。第n级可以从反相器信号输出端IVTout向第n+1级SR(n+1)(即，虚设级)传输反相器信号IVT。
图3是根据图2的示例性实施例的栅极驱动器500中的一个级的放大电路图。
根据本示例性实施例的栅极驱动器500的每个级SR包括输入单元511、反相器512、传输信号生成器513、输出单元514、噪声去除器515以及下拉单元516。
输入单元511可以包括一个晶体管(即，第四晶体管Tr4)。第四晶体管Tr4的输入端和第一控制端可以以二极管形式连接至第一输入端IN1。第四晶体管Tr4的第二控制端可以连接至第一电压输入端Vin1或第二电压输入端Vin2。例如，图3图示第四晶体管Tr4的第二控制端连接至供应第二低电压Vss2的第二电压输入端Vin2。第四晶体管Tr4的输出端可以连接至节点Q(下称“第一节点”)。第四晶体管Tr4可以包括具有双栅极的薄膜晶体管，双栅极具有包括底栅的第一控制端和包括顶栅的第二控制端。当向第一输入端IN1输入高电压时，输入单元511用来向节点Q传输高电压。
反相器512可以包括四个晶体管(即，第十二晶体管Tr12、第七晶体管Tr7、第八晶体管Tr8和第十三晶体管Tr13)。
第十二晶体管Tr12可以以二极管形式连接，第十二晶体管Tr12具有连接至第十二晶体管Tr12的控制端和时钟输入端CK的第一端(即，输入端)。第十二晶体管Tr12可以具有与第七晶体管Tr7的控制端和第十三晶体管Tr13的输入端连接的第二端(即，输出端)。
第七晶体管Tr7的控制端可以与第十二晶体管Tr12的输出端连接。第七晶体管Tr7可以具有与时钟输入端CK和第十二晶体管Tr12的控制端连接的输入端。第七晶体管Tr7可以具有与节点I(还被称为反相器节点或第二节点)连接的输出端。
第八晶体管Tr8的控制端可以与当前级的传输信号输出端CRout连接。第八晶体管Tr8可以具有与节点I连接的输入端。第八晶体管Tr8可以具有与供应第二低电压Vss2的第二电压输入端Vin2连接的输出端。
第十三晶体管Tr13的输入端可以与第十二晶体管Tr12的输出端连接。第十三晶体管Tr13可以包括与当前级的传输信号输出端CRout和第八晶体管Tr8的控制端连接的控制端。第十三晶体管Tr13可以包括与供应第二低电压Vss2的第二电压输入端Vin2连接的输出端。
当施加高信号作为时钟信号时，高信号分别被第十二晶体管Tr12和第七晶体管Tr7传输至第八晶体管Tr8的输入端和第十三晶体管Tr13的输入端。因此，节点I具有高电压。当从当前级的传输信号输出端CRout输出传输信号CR时，所传输的高信号将节点I的电压降低至第二低电压Vss2。结果，反相器512的节点I具有与当前级的传输信号CR和栅极导通电压相反的电压电平。
传输信号生成器513可以包括一个晶体管(即，第十五晶体管Tr15)。第十五晶体管Tr15的输入端可以与时钟输入端CK连接。因此，第一时钟信号CKV或第二时钟信号CKVB可以被施加至传输信号生成器513。第十五晶体管Tr15可以具有连接至输入单元511的输出(即，节点Q)的控制端。第十五晶体管Tr15可以具有与输出传输信号CR的传输信号输出端CRout连接的输出端。这里，在第十五晶体管Tr15的控制端和输出端之间可能形成寄生电容器。第十五晶体管Tr15的输出端可以不仅与传输信号输出端CRout连接，还可以与噪声去除器515和下拉单元516连接，因此接收第二低电压Vss2。结果，当传输信号CR为低时，电压值具有第二低电压Vss2。
输出单元514可以包括一个晶体管(即，第一晶体管Tr1)和一个电容器(即，第一电容器C1)。第一晶体管Tr1的控制端可以连接至节点Q。第一晶体管Tr1可以包括通过时钟输入端CK接收第一时钟信号CKV或第二时钟信号CKVB的输入端。第一电容器C1可以形成在第一晶体管Tr1的控制端和输出端之间。第一晶体管Tr1可以包括与栅极电压输出端OUT连接的输出端。第一晶体管Tr1的输出端还可以与噪声去除器515和下拉单元516连接。第一晶体管Tr1的输出端还可以通过噪声去除器515和下拉单元516与供应第一低电压Vss1的第一电压输入端Vin1连接。结果，栅极截止电压的电压值具有第一低电压Vss1的值。
输出单元514可以根据节点Q的电压和第一时钟信号CKV输出栅极电压。由于节点Q的电压，在第一晶体管Tr1的输出端和控制端之间产生电压差。当该电压差被存储在第一电容器C1中以后由时钟信号施加高电压时，所充入的电压被升压，从而输出高电压作为栅极导通电压。
噪声去除器515可以是由节点I的输出控制的一部分。噪声去除器515可以包括五个晶体管(即，第三晶体管Tr3、第十晶体管Tr10、第10-1晶体管Tr10-1、第十一晶体管Tr11和第11-1晶体管Tr11-1)。第三晶体管Tr3的控制端可以与节点I连接。第三晶体管Tr3可以包括与栅极电压输出端OUT连接的输入端，以及与供应第一低电压Vss1的第一电压输入端Vin1连接的输出端。第三晶体管Tr3根据节点I的电压而将栅极电压输出端OUT的电压改变为第一低电压Vss1。第十晶体管Tr10和第10-1晶体管Tr10-1可以是一对晶体管。第十晶体管Tr10可以具有连接至第10-1晶体管Tr10-1的输入端的输出端。第十晶体管Tr10的控制端和第10-1晶体管Tr10-1的控制端可以作为同一端连接至节点I(下文中为“附加连接”)。第十晶体管Tr10的输入端可以连接至节点Q，并且第10-1晶体管Tr10-1的输出端可以与供应第二低电压Vss2的第二电压输入端Vin2连接。第十晶体管Tr10和第10-1晶体管Tr10-1根据节点I的电压将节点Q的电压改变为第二低电压Vss2。当使用一对附加连接的晶体管时，这两个晶体管接收从第二低电压和节点I的电压之间的电压差分压出的相同电压，使得在节点Q中不明显地生成泄漏电流。根据示例性实施例，第十晶体管Tr10和第10-1晶体管Tr10-1可以利用三个或更多个晶体管被附加连接的结构来形成。在附加形成的晶体管的情况中，输入端和输出端可以彼此连接，并且控制端可以连接至同一节点I。第十一晶体管Tr11的控制端可以与节点I连接。第十一晶体管Tr11可以包括与传输信号输出端CRout连接的输入端，以及与供应第二低电压Vss2的第二电压输入端Vin2连接的输出端。第十一晶体管Tr11根据节点I的电压将传输信号输出端CRout的电压改变为第二低电压Vss2。第11-1晶体管Tr11-1的控制端可以通过第三输入端IN3与前一级的节点I连接。第11-1晶体管Tr11-1可以包括与栅极电压输出端OUT连接的输入端和与第一电压输入端Vin1连接的输出端。第11-1晶体管Tr11-1可以根据前一级的节点I(即，反相器的输出)的电压将栅极电压输出端OUT的电压改变为第一低电压Vss1。这里，第三晶体管Tr3可以通过当前级的反相器输出将栅极电压输出端OUT的电压改变为第一低电压Vss1。第11-1晶体管Tr11-1可以通过前一级的反相器输出将栅极电压输出端OUT的电压改变为第一低电压Vss1。
作为由下一级的传输信号CR控制的一部分，下拉单元516可以包括四个晶体管(即，第二晶体管Tr2、第九晶体管Tr9、第9-1晶体管Tr9-1以及第十七晶体管Tr17)。第二晶体管Tr2的控制端可以连接至第二输入端IN2。第二晶体管Tr2可以包括与栅极电压输出端OUT连接的输入端，以及与供应第一低电压Vss1的第一电压输入端Vin1连接的输出端。第二晶体管Tr2根据下一级的传输信号CR将栅极电压输出端OUT的电压改变为第一低电压Vss1。第九晶体管Tr9和第9-1晶体管Tr9-1可以是一对晶体管。第九晶体管Tr9可以包括连接至第9-1晶体管Tr9-1的输入端的输出端。第九晶体管Tr9和第9-1晶体管Tr9-1可以是一对附加连接的晶体管。第九晶体管Tr9的输入端可以连接至节点Q，并且第9-1晶体管的输出端可以与供应第二低电压Vss2的第二电压输入端Vin2连接。如所描述的，当使用一对附加连接的晶体管时，这两个晶体管可以接收从第二低电压和下一级的传输信号CR(特别地，低电压的电压)之间的电压差分压出的相同电压，使得在节点Q中不明显地生成泄漏电流。根据示例性实施例，第九晶体管Tr9和第9-1晶体管Tr9-1可以利用三个或更多个晶体管被附加连接的结构来形成。在附加形成的晶体管的情况中，输入端和输出端可以彼此连接，并且控制端可以连接至相同的第二输入端IN2。第十七晶体管Tr17的控制端可以连接至第二输入端IN2。第十七晶体管Tr17可以包括与传输信号输出端CRout连接的输入端，以及与供应第二低电压Vss2的第二电压输入端Vin2连接的输出端。
栅极电压和传输信号CR可以具有各种电压值。然而，在本示例性实施例中，栅极导通电压是25V，栅极截止电压和第一低电压Vss1是-5V，传输信号CR的高电压是25V，并且传输信号CR的低电压和第二低电压Vss2是-10V。下面，将基于上述电压电平来描述操作。
当传输信号生成器513和输出单元514通过节点Q的电压来操作时，一个级SR可以输出传输信号CR的高电压和栅极导通电压。传输信号CR被前一级的传输信号CR和下一级的传输信号CR从高电压降低至第二低电压Vss2，并且栅极导通电压变为栅极截止电压。
一般来说，在使用氧化物半导体的薄膜晶体管中生成的泄漏电流是在使用非晶硅的薄膜晶体管中生成的泄漏电流的10倍。当生成泄漏电流时，薄膜晶体管的驱动特性劣化，并且功耗增加。因此，应当防止在使用氧化物半导体的薄膜晶体管中生成泄漏电流。
当在第一晶体管Tr1的控制端和输出端之间生成的电压差被存储在电容器C1中时，向第一晶体管Tr1的输入端施加高电平时钟信号。结果，在电容器C1中充入的电压通过耦接被升压。当节点Q的电压通过升压而增加时，第四晶体管Tr4的源极和漏极之间的电压差Vds以及第四晶体管Tr4的源极和栅极之间的电压差Vgs也增加，因为它们连接至节点Q。当源极和漏极之间的电压差Vds以及源极和栅极之间的电压差Vgs增加时，产生节点Q的泄漏电流。
根据示例性实施例，由于具有负电压值的第二低电压Vss2被施加至第四晶体管Tr4的第二控制端，所以抑制了第四晶体管Tr4的泄漏电流。在替代实施例中，可以将第一低电压Vss1施加至第四晶体管Tr4的第二控制端。
此外，由于第四晶体管Tr4的导通时间累积，所以当第四晶体管Tr4导通时，流经第四晶体管Tr4的电流减少。根据示例性实施例，将具有负电压值的第二低电压Vss2施加至第四晶体管Tr4的第二控制端。因此，可以抑制在第四晶体管Tr4导通时流经第四晶体管Tr4的电流的下降。
将参考图10、图11和图12描述上述示例性实施例的效果。
此外，将参照图4、图5、图6、图7、图8和图9详细地描述第四晶体管Tr4。
图4是根据示例性实施例的包括在一级中的薄膜晶体管的剖视图。
示例性实施例的薄膜晶体管包括形成在由诸如玻璃或塑料的材料制成的绝缘基板110上的栅电极124和电压导线126。
栅电极124和电压导线126可以包括低电阻金属材料。尽管未示出，但是可以形成与栅电极124连接的导线。此外，可以向栅电极124施加被施加至第一输入端IN1的信号。此外，可以通过电压导线126施加第一低电压Vss1或第二低电压Vss2。
栅绝缘层140可以形成在栅电极124和电压导线126上。栅绝缘层140可以包括无机绝缘材料，如氮化硅(SiNx)或氧化硅(SiOx)。栅绝缘层140可以部分地暴露电压导线126。
半导体图案154可以形成在栅绝缘层140上。半导体图案154可以重叠栅电极124。半导体图案154可以包括氧化物半导体材料。例如，半导体图案154可以包括氧化铟镓锌(IGZO)、氧化锌锡(ZTO)、氧化铟锡(IZO)。可以针对半导体图案154使用任何其它适合的材料。
源电极173和漏电极175可以形成在半导体图案154上。源电极173和漏电极175可以彼此分离。源电极173和漏电极175可以包括低电阻金属材料。例如，源电极173和漏电极175可以包括以下至少之一：铜(Cu)、铝(Al)、银(Ag)、钼(Mo)、铬(Cr)、金(Au)、铂(Pt)、钯(Pd)、钽(Ta)、钨(W)、钛(Ti)、镍(Ni)和所列出的金属的合金。此外，源电极173和漏电极175可以由单层或多层形成。更具体地，源电极173和漏电极175可以由通过不同材料制成的双层或三层形成。源电极173和漏电极175可以包括任何数量的层。
第一钝化层180x可以形成在源电极173、漏电极175和栅绝缘层140上。第一钝化层180x可以包括无机绝缘体，如氮化硅(SiNx)或氧化硅(SiOx)。
有机绝缘体80可以设置在第一钝化层180x的一部分上。有机绝缘体80可以基本上具有平坦表面。有机绝缘体80可以包括接触孔186。在与电压导线126对应的区域中，有机绝缘体80可以被去除。因此，在暴露电压导线126的接触孔186所形成的区域内，不布置有机绝缘体80。
第一电极131可以形成在有机绝缘体80上。第一电极131可以由诸如ITO或IZO的透明导电材料制成。
第一电极131可以通过接触孔186与布置在显示区的外围区域内的电压导线126连接。因此，第一电极131可以接收第一低电压Vss1或第二低电压Vss2。第一电极131可以从栅电极124向上延伸，并且可以形成在重叠栅电极124的区域内。
第二钝化层180y可以形成在第一电极131上。第二钝化层180y可以包括无机绝缘体，如氮化硅(SiNx)或氧化硅(SiOx)。
如前面描述的，与接收低电压Vss1或Vss2的电压导线126连接的第一电极131可以形成在薄膜晶体管的栅电极124上方。因此，第一电极131可以包括包含栅电极124、半导体图案154、源电极173和漏电极175的薄膜晶体管的顶栅电极。
参照图5、图6、图7和图8，将描述根据示例性实施例的用于形成薄膜晶体管阵列面板的方法。
图5、图6、图7和图8是根据图4的示例性实施例的薄膜晶体管的制造方法的过程剖视图。
如图5所示，可以在绝缘基板110上使用低电阻金属材料形成栅电极124和电压导线126。绝缘基板110可以包括玻璃或塑料。
接下来，可以在栅电极124和电压导线126上使用诸如氮化硅(SiNx)或氧化硅(SiOx)的无机绝缘材料形成栅绝缘层140。
接下来，可以在栅绝缘层140上使用诸如氧化铟镓锌(IGZO)、氧化锌锡(ZTO)、氧化铟锡(IZO)的氧化物半导体材料形成半导体材料层。可以在半导体材料层上使用低电阻金属材料形成金属材料层。可以对金属材料层和半导体材料层进行蚀刻，使得形成半导体图案154。
接下来，可以将金属材料层蚀刻为形成源电极173和漏电极175。源电极173和漏电极175可以形成为在栅电极124的侧端处彼此分离。
如图6所示，可以在源电极173、漏电极175和栅绝缘层140上形成第一钝化层180x。第一钝化层180x可以包括无机绝缘体，如氮化硅(SiNx)或氧化硅(SiOx)。
如图7所示，可以在第一钝化层180x的一部分上形成有机绝缘体80。有机绝缘体80可以在与电压导线126对应的位置形成有接触孔186。有机绝缘体80可以包括有机材料。有机绝缘体80可以是基本上平坦的。有机绝缘体80可以是滤色器。如果有机绝缘体80是滤色器，那么可以在有机绝缘体80上进一步形成覆盖层。在形成栅绝缘层140、第一钝化层180x和有机绝缘体80以后，接触孔186可以形成为部分地暴露电压导线126。
如图8所示，可以在有机绝缘体80上形成通过接触孔186接触电压导线126并且从栅电极124向上延伸的第一电极131。
图9是根据另一示例性实施例的包括在一级中的薄膜晶体管的剖视图。
如图中所示，与图4的薄膜晶体管不同，在图9的示例性实施例的薄膜晶体管中有机绝缘体80被省略。图6中描述的在第一钝化层180x成层以后形成有机绝缘体80的过程被省略。如图9所示，可以在栅绝缘层140和第一钝化层180x中形成部分地暴露电压导线126的接触孔186。可以在第一钝化层180x上形成通过接触孔186接触电压导线126的第一电极131，使得可以制造薄膜晶体管。
接下来，将参照图10、图11和图12描述包括在薄膜晶体管阵列面板中的薄膜晶体管导通时流动的电流的幅度。
图10和图11是图示相对于时间根据施加至根据示例性实施例的薄膜晶体管的第一电极131的电压的电流值的图。图12是图示根据施加至根据示例性实施例的薄膜晶体管的第一电极的变化的电压而确定的电流的图。
首先，如图10所示，向第一电极131施加0V的电压，向栅电极124施加20V的电压，并且分别向源电极173的侧端和漏电极175的侧端施加具有预定电压差的电压，以相对于时间测量流过薄膜晶体管的电流。在此情况下，向源电极173施加的电压高于向漏电极175施加的电压。
当流过薄膜晶体管的电流ID具有1的初始值时，流过薄膜晶体管的电流ID随时间流逝(100,200，……，5000)在相同状态下下降至小于1。
此外，当向源电极173施加的电压和向漏电极175施加的电压被相反地施加，然后测量流过薄膜晶体管的电流ID时，流过该薄膜晶体管的电流ID具有大约0.62的值。
在图11中，当向第一电极131施加-30V的电压，向栅电极124施加20V的电压，并且分别向源电极173的侧端和漏电极175的侧端施加具有预定电压差的电压时，相对于时间测量流过薄膜晶体管的电流。在此情况下，向源电极173施加的电压高于向漏电极175施加的电压。
当流过薄膜晶体管的电流ID具有1的初始值时，流过薄膜晶体管的电流ID随时间流逝(100，200，……，5000)在相同状态下下降至小于1。
此外，当向源电极173施加的电压和向漏电极175施加的电压被相反地施加，然后测量流过薄膜晶体管的电流ID时，流过薄膜晶体管的电流ID具有大约0.92的值。
因此，将图10的实验值和图11的实验值进行比较，当向根据示例性实施例的第一电极131施加-30V的负电压时，抑制了在薄膜晶体管导通时流动的电流ID的下降。
接下来，参考图12，当向栅电极124施加的电压增加时，随着向第一电极131施加的电压沿负方向增大，流过薄膜晶体管的泄漏电流减小。如图中所示，当向栅电极124施加0V的电压时，在向第一电极131施加的电压是-30V时测量的泄漏电流低于在向第一电极131施加的电压是0V时测量的泄漏电流。因此，根据本发明构思的示例性实施例，可以降低在薄膜晶体管的侧端流过的泄漏电流。
尽管本文已经描述了特定示例性实施例和实现方式，但是其它实施例和修改将根据本描述显而易见。因此，本发明构思不限于这样的实施例，而是受限于所提供的权利要求以及各种明显修改和等价布置的更宽范围。

Claims (16)

1.一种显示设备，包括：
显示区，包括栅极线和数据线；以及
栅极驱动器，连接至所述栅极线的一端，所述栅极驱动器包括集成在基板上并被配置为输出栅极电压的级，其中所述级包括输入单元和输出单元，
其中所述输出单元包括第一晶体管和第一电容器，
其中所述第一晶体管包括被配置为接收时钟信号的输入端、连接至所述输入单元的节点的控制端以及连接至被配置为输出所述栅极电压的栅极电压输出端的输出端，
其中所述输入单元包括第二晶体管，并且
其中所述第二晶体管包括输入端和连接至所述第二晶体管的所述输入端的第一控制端、被配置为接收来自低电压输入端的低电压的第二控制端以及连接至所述第一晶体管的所述控制端的输出端。
2.根据权利要求1所述的显示设备，其中来自所述低电压输入端的所述低电压低于由所述输出单元输出的所述栅极电压。
3.根据权利要求2所述的显示设备，其中所述级进一步包括下拉单元，所述下拉单元包括第一对晶体管，
其中所述第一对晶体管各自包括被配置为接收下一级的输出的控制端，并且
其中所述第一对晶体管包括连接至所述节点的输入端以及连接至所述低电压输入端的输出端。
4.根据权利要求3所述的显示设备，其中所述级进一步包括传输信号生成器，所述传输信号生成器包括第三晶体管，并且
其中所述第三晶体管包括被配置为接收所述时钟信号的输入端、连接至所述节点的控制端以及连接至被配置为输出传输信号的传输信号输出端的输出端。
5.根据权利要求4所述的显示设备，其中所述级进一步包括反相器单元，所述反相器单元包括连接至所述低电压输入端的第四晶体管和第六晶体管，
其中从所述反相器单元输出的反相器电压低于由所述输出单元输出的所述栅极电压。
6.根据权利要求5所述的显示设备，其中所述级进一步包括噪声去除单元，所述噪声去除单元包括第二对晶体管，
其中所述第二对晶体管各自包括被配置为接收所述反相器单元的所述反相器电压的控制端，并且
其中所述第二对晶体管包括连接至所述节点的输入端和连接至所述低电压输入端的输出端。
7.根据权利要求6所述的显示设备，其中所述下拉单元进一步包括第五晶体管，所述第五晶体管包括被配置为接收所述下一级的所述输出的控制端、连接至所述传输信号输出端的输入端以及连接至所述低电压输入端的输出端。
8.根据权利要求7所述的显示设备，其中所述级的晶体管中的至少一个包括氧化物半导体。
9.一种显示设备，包括：
栅极线；以及
栅极驱动器，连接至所述栅极线，并且包括被配置为向所述栅极线输出栅极电压的级，其中所述级包括输入单元和输出单元，
其中所述输出单元包括第一晶体管和第一电容器，
其中所述第一晶体管包括被配置为接收时钟信号的输入端、连接至所述输入单元的节点的控制端以及连接至被配置为输出所述栅极电压的栅极电压输出端的输出端，
其中所述输入单元包括第二晶体管，并且
其中所述第二晶体管包括输入端和连接至所述第二晶体管的所述输入端的第一控制端、被配置为接收来自低电压输入端的低电压的第二控制端以及连接至所述第一晶体管的所述控制端的输出端。
10.根据权利要求9所述的显示设备，其中来自所述低电压输入端的所述低电压低于由所述输出单元输出的所述栅极电压。
11.根据权利要求10所述的显示设备，其中所述级进一步包括下拉单元，所述下拉单元包括第一对晶体管，
其中所述第一对晶体管各自包括被配置为接收下一级的输出的控制端，并且
其中所述第一对晶体管包括连接至所述节点的输入端以及连接至所述低电压输入端的输出端。
12.根据权利要求11所述的显示设备，其中所述级进一步包括传输信号生成器，所述传输信号生成器包括第三晶体管，并且
其中所述第三晶体管包括被配置为接收所述时钟信号的输入端、连接至所述节点的控制端以及连接至被配置为输出传输信号的传输信号输出端的输出端。
13.根据权利要求12所述的显示设备，其中所述级进一步包括反相器单元，所述反相器单元包括连接至所述低电压输入端的第四晶体管和第六晶体管，
其中从所述反相器单元输出的反相器电压低于由所述输出单元输出的所述栅极电压。
14.根据权利要求13所述的显示设备，其中所述级进一步包括噪声去除单元，所述噪声去除单元包括第二对晶体管，
其中所述第二对晶体管各自包括被配置为接收所述反相器单元的所述反相器电压的控制端，并且
其中所述第二对晶体管包括连接至所述节点的输入端和连接至所述低电压输入端的输出端。
15.根据权利要求14所述的显示设备，其中所述下拉单元进一步包括第五晶体管，所述第五晶体管包括被配置为接收所述栅极驱动器的所述下一级的所述输出的控制端、连接至所述传输信号输出端的输入端以及连接至所述低电压输入端的输出端。
16.根据权利要求15所述的显示设备，其中所述级的晶体管中的至少一个包括氧化物半导体。
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