CN113589612A - Array substrate, manufacturing method and display panel - Google Patents
Array substrate, manufacturing method and display panel Download PDFInfo
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- CN113589612A CN113589612A CN202110770938.1A CN202110770938A CN113589612A CN 113589612 A CN113589612 A CN 113589612A CN 202110770938 A CN202110770938 A CN 202110770938A CN 113589612 A CN113589612 A CN 113589612A
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- 239000000758 substrate Substances 0.000 title claims abstract description 154
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 102
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 102
- 229910052751 metal Inorganic materials 0.000 claims abstract description 77
- 239000002184 metal Substances 0.000 claims abstract description 77
- 239000004065 semiconductor Substances 0.000 claims abstract description 55
- 238000005530 etching Methods 0.000 claims abstract description 23
- 239000004973 liquid crystal related substance Substances 0.000 claims description 34
- 238000000034 method Methods 0.000 claims description 24
- 230000005540 biological transmission Effects 0.000 claims description 10
- 125000006850 spacer group Chemical group 0.000 claims description 10
- 230000001681 protective effect Effects 0.000 claims description 3
- 238000005381 potential energy Methods 0.000 abstract description 4
- 230000002093 peripheral effect Effects 0.000 description 20
- 239000010949 copper Substances 0.000 description 17
- 229920002120 photoresistant polymer Polymers 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 9
- 229910052802 copper Inorganic materials 0.000 description 9
- 239000011159 matrix material Substances 0.000 description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 239000003086 colorant Substances 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- 239000010408 film Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 229910052750 molybdenum Inorganic materials 0.000 description 3
- 239000011733 molybdenum Substances 0.000 description 3
- DTSBBUTWIOVIBV-UHFFFAOYSA-N molybdenum niobium Chemical compound [Nb].[Mo] DTSBBUTWIOVIBV-UHFFFAOYSA-N 0.000 description 3
- 238000002294 plasma sputter deposition Methods 0.000 description 3
- 238000011946 reduction process Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 229920000515 polycarbonate Polymers 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 230000000717 retained effect Effects 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 150000004645 aluminates Chemical class 0.000 description 1
- QZPSXPBJTPJTSZ-UHFFFAOYSA-N aqua regia Chemical compound Cl.O[N+]([O-])=O QZPSXPBJTPJTSZ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- FAHBNUUHRFUEAI-UHFFFAOYSA-M hydroxidooxidoaluminium Chemical compound O[Al]=O FAHBNUUHRFUEAI-UHFFFAOYSA-M 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- KYKLWYKWCAYAJY-UHFFFAOYSA-N oxotin;zinc Chemical compound [Zn].[Sn]=O KYKLWYKWCAYAJY-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/13439—Electrodes characterised by their electrical, optical, physical properties; materials therefor; method of making
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136286—Wiring, e.g. gate line, drain line
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- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The invention discloses an array substrate, a manufacturing method and a display panel, wherein the array substrate comprises: a substrate; scanning lines and a grid arranged on the substrate; a first insulating layer covering the scan lines and the gate electrodes; a first transparent metal oxide layer disposed on the upper side of the first insulating layer, the first transparent metal oxide layer including a source electrode and a drain electrode; the second metal layer is arranged on the upper side of the first insulating layer and comprises a data line; a semiconductor layer disposed on upper sides of the source and drain electrodes, the semiconductor layer including an active layer connecting the source and drain electrodes; and a pixel electrode disposed on the first insulating layer. The source electrode and the drain electrode are made of transparent metal oxide layers, so that the potential energy difference between the source electrode and the active layer and the potential energy difference between the drain electrode and the active layer are reduced, ohmic contact is easily formed, and the electron mobility of the TFT is improved. And the active layer is arranged on the upper sides of the source electrode and the drain electrode, so that the active layer is prevented from being etched when the source electrode and the drain electrode are formed by etching, the active layer is prevented from being damaged, and the active layer is ensured to have better performance.
Description
Technical Field
The invention relates to the technical field of displays, in particular to an array substrate, a manufacturing method and a display panel.
Background
With the development of display technology, a thin and light display panel is popular with consumers, especially a thin and light display panel (LCD).
When the display device works, driving voltages are respectively applied to the Thin Film Transistor Array Substrate and the Color Film Substrate to control the rotation direction of liquid crystal molecules between the two substrates so as to refract backlight provided by a backlight module of the display device, thereby displaying a picture.
In the existing TFT, a source electrode and a drain electrode are usually formed by patterning the same metal film as a data line, the source electrode and the drain electrode are usually formed by using metal copper, and an active layer is usually formed by using a semiconductor. In the existing TFT, an active layer is generally arranged below a source electrode and a drain electrode, and the active layer is generally etched when a TFT channel is etched, so that the performance of the active layer is deteriorated, and the characteristic of the TFT is also deteriorated.
Disclosure of Invention
In order to overcome the disadvantages and shortcomings of the prior art, the present invention provides an array substrate, a method for fabricating the same, and a display panel, so as to solve the problems of the prior art that the electron mobility at the TFT is low and the active layer is etched when the TFT channel is etched.
The purpose of the invention is realized by the following technical scheme:
the invention provides an array substrate, comprising:
a substrate;
the first metal layer is arranged on the substrate and comprises a scanning line and a grid electrode;
a first insulating layer covering the scan lines and the gate electrodes;
a first transparent metal oxide layer disposed on an upper side of the first insulating layer, the first transparent metal oxide layer including a source electrode and a drain electrode;
the second metal layer is arranged on the upper side of the first insulating layer and comprises a data line, and the data line is in conductive connection with the source electrode;
a semiconductor layer disposed on upper sides of the source electrode and the drain electrode, the semiconductor layer including an active layer connecting the source electrode and the drain electrode;
and the pixel electrode is arranged on the upper side of the first insulating layer and is electrically connected with the drain electrode.
Further, the first transparent metal oxide layer further includes the pixel electrode; the array substrate further comprises a second insulating layer covering the semiconductor layer and a second transparent metal oxide layer arranged on the second insulating layer, wherein the second transparent metal oxide layer comprises a common electrode.
Further, the array substrate further comprises a flat layer, a second transparent metal oxide layer, an insulating spacing layer and a third transparent metal oxide layer which are sequentially arranged, the flat layer covers the semiconductor layer and is far away from one side of the substrate, the second transparent metal oxide layer comprises a common electrode, and the third transparent metal oxide layer comprises the pixel electrode.
Further, the second metal layer is arranged on the upper surface of the first transparent metal oxide layer and is in contact with the upper surface of the first transparent metal oxide layer, the second metal layer further comprises a first shading part and a second shading part, the first shading part is arranged on the upper surface of the source electrode and is in contact with the upper surface of the source electrode, the second shading part is arranged on the upper surface of the drain electrode and is in contact with the upper surface of the drain electrode, and the projections of the first shading part and the second shading part on the substrate are overlapped with the projection of the grid electrode on the substrate.
Further, the semiconductor layer is disposed on the upper surface of the second metal layer and contacts with the upper surface of the second metal layer, the active layer covers the first light shielding portion, the second light shielding portion, the source electrode, and the drain electrode and contacts with the first light shielding portion, the second light shielding portion, the source electrode, and the drain electrode, and the semiconductor layer further includes a protective portion covering the upper surface of the second metal layer.
The invention also provides a manufacturing method of the array substrate, which is used for manufacturing the array substrate, and the manufacturing method comprises the following steps:
providing a substrate;
forming a first metal layer on the substrate, etching the first metal layer and forming patterned scanning lines and a grid electrode;
forming a first insulating layer covering the scan lines and the gate electrodes on the substrate;
forming a first transparent metal oxide layer on the upper side of the first insulating layer, etching the first transparent metal oxide layer and forming patterned source and drain electrodes;
forming a second metal layer on the upper side of the first insulating layer, etching the second metal layer and forming a patterned data line, wherein the data line is in conductive connection with the source electrode;
forming a semiconductor layer on the upper sides of the source electrode and the drain electrode, etching the semiconductor layer and forming a patterned active layer, wherein the active layer is electrically connected with the source electrode and the drain electrode;
and forming a pixel electrode on the upper side of the first insulating layer, wherein the pixel electrode is electrically connected with the drain electrode.
Further, the pixel electrode is also formed when the first transparent metal oxide layer is etched; the manufacturing method further comprises the following steps:
and forming a second insulating layer covering the semiconductor layer on the substrate, forming a second transparent metal oxide layer on the second insulating layer, etching the second transparent metal oxide layer and forming a patterned common electrode.
Further, the manufacturing method further comprises the following steps:
forming a flat layer covering the semiconductor layer on the substrate, forming a second transparent metal oxide layer on the flat layer, etching the second transparent metal oxide layer and forming a patterned common electrode;
forming an insulating spacer layer covering the second transparent metal oxide layer on the substrate, etching the flat layer and the insulating spacer layer, and forming a contact hole corresponding to the drain electrode;
and forming a third transparent metal oxide layer on the insulating spacing layer, etching the third transparent metal oxide layer and forming the patterned pixel electrode, wherein the pixel electrode is connected with the drain electrode through the contact hole.
Further, the manufacturing method further comprises the following steps:
the second metal layer is arranged on the upper surface of the first transparent metal oxide layer and is in contact with the upper surface of the first transparent metal oxide layer, a first light shielding part and a second light shielding part are further formed when the second metal layer is etched, the first light shielding part is positioned on the upper surface of the source electrode and is in contact with the upper surface of the source electrode, the second light shielding part is arranged on the upper surface of the drain electrode and is in contact with the upper surface of the drain electrode, and the projections of the first light shielding part and the second light shielding part on the substrate are overlapped with the projection part of the grid electrode on the substrate;
the semiconductor layer is arranged on the upper surface of the second metal layer and is in contact with the upper surface of the second metal layer, the active layer covers the first light shielding part, the second light shielding part, the source electrode and the drain electrode and is in contact with the first light shielding part, the second light shielding part, the source electrode and the drain electrode, and a protection part covering the second metal layer is further formed when the semiconductor layer is etched.
The invention also provides a display panel, which comprises the array substrate, an opposite substrate arranged opposite to the array substrate and a liquid crystal layer arranged between the array substrate and the opposite substrate, wherein the opposite substrate is provided with an upper polaroid, the array substrate is provided with a lower polaroid, and the transmission axis of the upper polaroid is vertical to the transmission axis of the lower polaroid.
The invention has the beneficial effects that: the source electrode and the drain electrode are made of transparent metal oxide layers, so that the potential energy difference between the source electrode and the active layer and the potential energy difference between the drain electrode and the active layer are reduced, ohmic contact is easy to form, and the electron mobility at the position of the TFT is improved; and then the active layer is arranged on the upper sides of the source electrode and the drain electrode, namely the source electrode and the drain electrode are manufactured and formed firstly, and then the active layer is formed.
Drawings
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the invention;
FIGS. 2a-2g are schematic cross-sectional views illustrating a method for fabricating an array substrate according to an embodiment of the invention;
FIGS. 3a-3d are schematic diagrams of a planar manufacturing process of a method for manufacturing an array substrate according to an embodiment of the invention;
FIG. 4 is a schematic cross-sectional view illustrating a display panel according to an embodiment of the invention;
FIG. 5 is a schematic cross-sectional view of an array substrate according to a second embodiment of the present invention;
FIGS. 6a-6c are schematic cross-sectional views illustrating a manufacturing method of an array substrate according to a second embodiment of the present invention;
FIG. 7 is a schematic plan view illustrating a manufacturing process of the array substrate according to the second embodiment of the present invention;
FIG. 8 is a schematic cross-sectional view of an array substrate according to a third embodiment of the present invention;
fig. 9 is a schematic cross-sectional view of a display panel according to a third embodiment of the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention adopted to achieve the predetermined objects, the following detailed description of the embodiments, structures, features and effects of the array substrate and the manufacturing method, the display panel according to the present invention with reference to the accompanying drawings and the preferred embodiments is as follows:
[ example one ]
Fig. 1 is a schematic cross-sectional view of an array substrate according to a first embodiment of the present invention, fig. 2a to 2g are schematic cross-sectional manufacturing process of a manufacturing method of the array substrate according to the first embodiment of the present invention, fig. 3a to 3d are schematic plan-view manufacturing process of the manufacturing method of the array substrate according to the first embodiment of the present invention, and fig. 4 is a schematic cross-sectional structure of a display panel according to the first embodiment of the present invention.
As shown in fig. 1, an array substrate according to a first embodiment of the present invention includes:
A first metal layer 11 (fig. 3a) disposed on the substrate 10, wherein the first metal layer 11 includes a scan line 111 (fig. 3a) and a gate 112, and the scan line 111 and the gate 112 are electrically connected. The first metal layer 11 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al), or the like.
A first insulating layer 101 covering the scan line 111 and the gate electrode 112, the first insulating layer 101 being a gate insulating layer, the entire surface of the first insulating layer 101 being disposed on the substrate 10 and covering the gate electrode 112 and the scan line 111, the first insulating layer 101 being made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination thereof.
And a first transparent metal oxide layer 12 disposed on the upper side of the first insulating layer 101, wherein the first transparent metal oxide layer 12 includes a source electrode 121 and a drain electrode 122, and the first transparent metal oxide layer 12 is made of a transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).
And a second metal layer 13 disposed on the upper side of the first insulating layer 101, wherein the second metal layer 13 includes a data line 131, and the data line 131 is electrically connected to the source electrode 121. The second metal layer 13 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), etc. It is to be understood that the second metal layer 13 in this embodiment does not include the source electrode 121 and the drain electrode 122, and preferably, a projection of the second metal layer 13 on the substrate 10 does not overlap a projection of the gate electrode 112 on the substrate 10, that is, the second metal layer 13 is spaced apart from the TFT, so as to prevent ions in the second metal layer 13 from diffusing to the TFT channel, and further improve electron mobility at the TFT.
And a semiconductor layer 14 disposed on the upper sides of the source and drain electrodes 121 and 122, the semiconductor layer 14 including an active layer 141 connecting the source and drain electrodes 121 and 122. The semiconductor layer 14 is made of a metal Oxide, such as Indium Gallium Zinc Oxide (IGZO), Indium Gallium Zinc Tin Oxide (IGZTO), LnIZO, or ITZO.
And a pixel electrode 123 disposed on the first insulating layer 101, wherein the pixel electrode 123 is electrically connected to the drain electrode 122.
In this embodiment, the semiconductor layer 14 is disposed on the upper side of the first transparent metal oxide layer 12 and contacts the upper surface of the first transparent metal oxide layer 12, and the active layer 141 covers the source electrode 121 and the drain electrode 122. That is, in the present embodiment, the source electrode 121 and the drain electrode 122 are first fabricated, and then the active layer 141 is fabricated on the upper sides of the source electrode 121 and the drain electrode 122, so that when the first transparent metal oxide layer 12 is etched and the source electrode 121 and the drain electrode 122 are fabricated, the active layer 141 is prevented from being etched, and thus the active layer 141 is prevented from being damaged, which results in poor performance of the active layer 141.
Further, the semiconductor layer 14 further includes a protective portion 142 covering the surface of the second metal layer 13. That is, the data line 131 is fabricated first, and then the semiconductor layer 14 is fabricated, when the semiconductor layer 14 is etched, the semiconductor layer 14 corresponding to the second metal layer 13 region is retained and the protection portion 142 covering the second metal layer 13 is formed, so as to protect the second metal layer 13, and prevent the data line 131 from being damaged when the semiconductor layer 14 is etched or a subsequent process is fabricated, so as to affect the performance of the data line 131 and the peripheral trace 132.
In this embodiment, the first transparent metal oxide layer 12 further includes a pixel electrode 123. That is, the pixel electrode 123, the source electrode 121, and the drain electrode 122 are formed by the same process, and the pixel electrode 123 and the drain electrode 122 can be in direct contact without forming a contact hole, thereby reducing the flow of the whole manufacturing process and improving the aperture opening ratio of the pixel. Of course, in other embodiments, the pixel electrode 123 and the source electrode 121 and the drain electrode 122 may be formed by different processes, and the pixel electrode 123 may be additionally formed by a layer of transparent metal oxide. For example, after the planarization layer 103 is applied, a pixel electrode 123 is formed by a layer of transparent metal oxide, and the pixel electrode 123 is electrically connected to the drain electrode 122 through a contact hole, as shown in fig. 8.
In this embodiment, the array substrate further includes a second insulating layer 102 covering the semiconductor layer 14 and a second transparent metal oxide layer 15 disposed on the second insulating layer 102, and the second transparent metal oxide layer 15 includes a common electrode 151. The second insulating layer 102 is made of silicon oxide (SiOx), silicon nitride (SiNx) or a combination thereof, and the second transparent metal oxide layer 15 is made of transparent metal oxide such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO). In this embodiment, the pixel electrode 123 is located below the common electrode 151, the pixel electrode 123 is a planar electrode corresponding to a sub-pixel, and the common electrode 151 is a planar electrode having a whole surface and has a slit in a region corresponding to the sub-pixel to form a Fringe Field Switching (FFS) mode. Of course, in other embodiments, the pixel electrode 123 is located on the upper side of the common electrode 151, or the common electrode 151 may be disposed on the opposite substrate 20 instead of the common electrode 151, so as to form a TN display mode or a VA display mode. Or the common electrode 151 may be provided as a block electrode corresponding to the area of the sub-pixel and having a slit, and then a common electrode line electrically connects all the common electrodes 151 together and applies the same common signal.
Further, the second metal layer 13 further includes a peripheral trace 132 located in the non-display region, and the second transparent metal oxide layer 15 further includes a bridge electrode 152 connected to the peripheral trace 132. The peripheral trace 132 may be, for example, some metal wires (signal input wires) in the bonding region, and the protection portion 142 covering the peripheral trace 132 needs to be subjected to a reduction process at the bridge hole, for example, a hydrogen injection process or a plasma sputtering process, so that the semiconductor is converted into a conductor, which is beneficial to reduce the contact impedance between the bridge hole and the bridge electrode 152.
The embodiment also provides a manufacturing method of the array substrate, and the manufacturing method is used for manufacturing the array substrate. As shown in fig. 2a-2g and 3a-3d, the manufacturing method comprises:
as shown in fig. 2a and 3a, a substrate 10 is provided, and the substrate 10 may be made of glass, quartz, acrylic or polycarbonate.
A first metal layer 11 is formed on a substrate 10 (fig. 3a), the first metal layer 11 is etched and patterned to form a scan line 111 (fig. 3a) and a gate electrode 112, the scan line 111 and the gate electrode 112 are electrically connected. The first metal layer 11 may be made of copper and molybdenum niobium (Cu/MoNb), or copper and molybdenum (Cu/Mo), or copper and aluminum (Cu/Al).
A first insulating layer 101 covering the scan line 111 and the gate electrode 112 is formed on the substrate 10, the first insulating layer 101 is a gate insulating layer, the entire surface of the first insulating layer 101 is disposed on the substrate 10 and covers the gate electrode 112 and the scan line 111, and the first insulating layer 101 is made of silicon oxide (SiOx), silicon nitride (SiNx), or a combination thereof.
As shown in fig. 2b to 2d and 3b, in the present embodiment, a first transparent metal oxide layer 12 and a second metal layer 13 are sequentially formed on the upper side of the first insulating layer 101, the first transparent metal oxide layer 12 is in contact with the upper surface of the first insulating layer 101, and the first transparent metal oxide layer 12 and the second metal layer 13 are etched by using a halftone mask process. The half-tone mask process specifically includes covering a photoresist on the upper surface of the second metal layer 13, and exposing and developing the photoresist by using a half-tone mask (half-tone mask), so that the photoresist forms a photoresist full-remaining region, a photoresist half-remaining region, and a photoresist non-remaining region (i.e., no photoresist). The non-reserved region corresponds to a TFT channel and other regions where the first transparent metal oxide layer 12 and the second metal layer 13 need to be etched away, the full-reserved region corresponds to a region where the first transparent metal oxide layer 12 and the second metal layer 13 such as the data line 131 and the peripheral trace 132 are reserved, and the half-reserved region corresponds to a region where only the first transparent metal oxide layer 12 is reserved and the second metal layer 13 is not reserved, such as the source 121, the drain 122, and the pixel electrode 123. After exposing and developing the photoresist by using a half-tone mask, the second metal layer 13 and the first transparent metal oxide layer 12 are etched by using a metal etching solution and a transparent metal oxide etching solution, respectively, for example, the second metal layer 13 and the first transparent metal oxide layer 12 are etched by using aluminate and aqua regia, so that the source electrode 121, the drain electrode 122 and the pixel electrode 123 are formed on the first transparent metal oxide layer 12, as shown in fig. 2 c. And then ashing the photoresist to remove the photoresist half-reserved area, etching the second metal layer 13 by using a metal etching solution (aluminic acid), and finally removing the photoresist, so that the second metal layer 13 forms a data line 131 and a peripheral wiring 132, wherein the data line 131 is directly in conductive connection with the source electrode 121. The halftone mask process can reduce the flow of the manufacturing process, and as for the halftone mask process, reference may be made to the prior art, which is not described in detail herein. Of course, in other embodiments, the first transparent metal oxide layer 12 and the second metal layer 13 may also be etched by using two mask processes, which is not limited thereto.
Further, after the pixel electrode 123 is formed, the pixel electrode 123 needs to be subjected to annealing and annealing treatment, so that the amorphous transparent metal oxide is converted into a polycrystalline transparent metal oxide, thereby increasing the conductivity of the pixel electrode 123.
As shown in fig. 2e and 3c, the semiconductor layer 14 is formed on the upper side of the first insulating layer 101, the semiconductor layer 14 is etched and a patterned active layer 141 is formed, and the active layer 141 is electrically connected to the source electrode 121 and the drain electrode 122.
In this embodiment, the semiconductor layer 14 is disposed on the upper surface of the first transparent metal oxide layer 12 and contacts with the upper surface of the first transparent metal oxide layer 12, and the semiconductor layer 14 is further disposed on the upper surface of the second metal layer 13 and contacts with the upper surface of the second metal layer 13, that is, after the source electrode 121, the drain electrode 122, the pixel electrode 123, the data line 131 and the peripheral trace 132 are fabricated, the semiconductor layer 14 is covered immediately, and then a protection portion 142 covering the second metal layer 13 is formed when the semiconductor layer 14 is etched, that is, the protection portion 142 covers all of the second metal layer 13, for example, the protection portion 142 covers the data line 131 and the peripheral trace 132, and the active layer 141 covers the regions of the source electrode 121 and the drain electrode 122. By forming the source electrode 121 and the drain electrode 122 first and then forming the active layer 141 on the upper sides of the source electrode 121 and the drain electrode 122, when the first transparent metal oxide layer 12 is etched and the source electrode 121 and the drain electrode 122 are formed, the active layer 141 can be prevented from being etched, so that damage to the active layer 141 is prevented, and the performance of the active layer 141 is ensured. And the data line 131 is fabricated first, then the semiconductor layer 14 is fabricated, when the semiconductor layer 14 is etched, the semiconductor layer 14 in the second metal layer 13 region is retained and the protection portion 142 is formed, so as to protect the second metal layer 13, thereby avoiding damage to the data line 131 and the peripheral trace 132 when the semiconductor layer 14 is etched or a subsequent process is fabricated, so as to affect the performance of the data line 131. Of course, in other embodiments, the active layer 141 may be fabricated first, and then the data line 131 and the peripheral trace 132 may be fabricated.
As shown in fig. 2f-2g and 3d, a second insulating layer 102 covering the semiconductor layer 14 is formed on the substrate 10 and a second transparent metal oxide layer 15 is formed on the second insulating layer 102, the second transparent metal oxide layer 15 is etched and a patterned common electrode 151 is formed. The common electrode 151 is a comb-shaped electrode having slits in a region corresponding to the pixel electrode 123. In this embodiment, before covering the second transparent metal oxide layer 15, an area of the second insulating layer 102 corresponding to the peripheral trace 132 is etched to form a bridging hole, the second transparent metal oxide layer 15 forms a bridging electrode 152 in the peripheral area (non-display area), and the bridging electrode 152 covers the bridging holes of the peripheral traces 132 and electrically connects the peripheral traces 132.
Further, before covering the second transparent metal oxide layer 15, the semiconductor layer 14 in the bridging hole needs to be subjected to a reduction process, such as a hydrogen injection process or a plasma sputtering process, so that the semiconductor is converted into a conductor, which is beneficial to reducing the contact resistance between the bridging hole and the bridging electrode 152.
As shown in fig. 4, the display panel includes the array substrate, the opposite substrate 20 opposite to the array substrate, and the liquid crystal layer 30 disposed between the array substrate and the opposite substrate 20, wherein the opposite substrate 20 is provided with an upper polarizer 41, the array substrate is provided with a lower polarizer 42, and a transmission axis of the upper polarizer 41 is perpendicular to a transmission axis of the lower polarizer 42. In the liquid crystal layer 30, positive liquid crystal molecules (liquid crystal molecules having positive dielectric anisotropy) are used, and in an initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules 131 close to the array substrate. It is understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.
In this embodiment, the opposite substrate 20 is a color film substrate, a black matrix 21 and a color resistance layer 22 are disposed on the opposite substrate 20, the black matrix 21 corresponds to the scan line 111, the data line 131, the thin film transistor and the peripheral non-display area, and the black matrix 21 separates the color resistance layers 22. The color resist layer 22 includes color resist materials of three colors of red (R), green (G), and blue (B), and sub-pixels of the three colors of red (R), green (G), and blue (B) are correspondingly formed.
[ example two ]
Fig. 5 is a schematic cross-sectional view of an array substrate according to a second embodiment of the present invention, fig. 6a to 6c are schematic cross-sectional manufacturing process diagrams of a manufacturing method of the array substrate according to the second embodiment of the present invention, and fig. 7 is one of schematic plan manufacturing process diagrams of the manufacturing method of the array substrate according to the second embodiment of the present invention. As shown in fig. 5, the array substrate and the manufacturing method thereof, and the display panel provided by the second embodiment of the present invention are substantially the same as the array substrate and the manufacturing method thereof, and the display panel in the first embodiment (fig. 1 to fig. 4), except that in this embodiment, the second metal layer 13 further includes a first light-shielding portion 133 and a second light-shielding portion 134, the first light-shielding portion 133 is disposed on the upper surface of the source 121 and contacts with the upper surface of the source 121, the second light-shielding portion 134 is disposed on the upper surface of the drain 122 and contacts with the upper surface of the drain 122, and projections of the first light-shielding portion 133 and the second light-shielding portion 134 on the substrate 10 overlap with projections of the gate 112 on the substrate 10. Since the electrode 121 and the drain electrode 122 are made of transparent metal oxide, when a backlight passes through the source electrode 121 and the drain electrode 122 and irradiates the active layer 141, the active layer 141 is affected by light and generates a dark current, which affects the performance of the TFT. Therefore, in the present embodiment, the light shielding portions are disposed on the upper surfaces of the source electrode 121 and the drain electrode 122, so that the interference of the backlight on the active layer 141 is avoided.
Although the light shielding portion covers the upper surfaces of the source and drain electrodes 121 and 122, the active layer 141 needs to be in contact with the source and drain electrodes 121 and 122 to ensure high electron mobility of the TFT. For example, the active layer 141 may contact sidewalls of the source and drain electrodes 121 and 122 at the TFT channel, or the light shielding portion may expose a portion of upper surfaces of the source and drain electrodes 121 and 122 at a position near the TFT channel.
The embodiment also provides a manufacturing method of the array substrate, and the manufacturing method is used for manufacturing the array substrate. The manufacturing method in this embodiment is basically the same as that in the first embodiment, except that:
as shown in fig. 6a to 6c and fig. 7, when the second metal layer 13 is etched in the present embodiment, a data line 131, a peripheral trace 132, a first light-shielding portion 133 and a second light-shielding portion 134 are formed, and the first light-shielding portion 133 and the second light-shielding portion 134 respectively correspond to the regions of the source electrode 121 and the drain electrode 122, wherein the first light-shielding portion 133 is electrically connected to the data line 131, and other manufacturing process flows can refer to the first embodiment.
In this embodiment, referring to fig. 4, the display panel includes the array substrate, the opposite substrate 20 opposite to the array substrate, and the liquid crystal layer 30 disposed between the array substrate and the opposite substrate 20, wherein the opposite substrate 20 is provided with an upper polarizer 41, the array substrate is provided with a lower polarizer 42, and a transmission axis of the upper polarizer 41 is perpendicular to a transmission axis of the lower polarizer 42. In the liquid crystal layer 30, positive liquid crystal molecules (liquid crystal molecules having positive dielectric anisotropy) are used, and in an initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules 131 close to the array substrate. It is understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.
In this embodiment, the opposite substrate 20 is a color film substrate, a black matrix 21 and a color resistance layer 22 are disposed on the opposite substrate 20, the black matrix 21 corresponds to the scan line 111, the data line 131, the thin film transistor and the peripheral non-display area, and the black matrix 21 separates the color resistance layers 22. The color resist layer 22 includes color resist materials of three colors of red (R), green (G), and blue (B), and sub-pixels of the three colors of red (R), green (G), and blue (B) are correspondingly formed.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
[ third example ]
Fig. 8 is a schematic cross-sectional view of an array substrate in a third embodiment of the present invention, and fig. 9 is a schematic cross-sectional structure of a display panel in the third embodiment of the present invention. As shown in fig. 8 and 9, the array substrate and the manufacturing method thereof and the display panel according to the third embodiment of the present invention are substantially the same as the array substrate and the manufacturing method thereof and the display panel according to the first embodiment (fig. 1 to 4), except that in this embodiment, the first transparent metal oxide layer 12 does not include the pixel electrode 123. Specifically, the array substrate further includes a flat layer 103, a second transparent metal oxide layer 15, an insulating spacer layer 104, and a third transparent metal oxide layer 16, which are sequentially disposed, the flat layer 103 covers a side of the semiconductor layer 14 away from the substrate 10, the second transparent metal oxide layer 15 includes a common electrode 151, and the third transparent metal oxide layer 16 includes a pixel electrode 123. That is, in this embodiment, a layer of transparent metal oxide is additionally formed to form the pixel electrode 123, and the planarization layer 103 is further provided to raise the common electrode 151 and the pixel electrode 123, so that the electric field formed between the common electrode 151 and the pixel electrode 123 can drive the liquid crystal molecules more easily, thereby reducing the driving power consumption.
In this embodiment, the second insulating layer 102 is disposed between the planarization layer 103 and the substrate 10, that is, the second insulating layer 102 covering the semiconductor layer 14 is first fabricated, and then the planarization layer 103 covering the second insulating layer 102 is fabricated. Of course, in other embodiments, the flat layer 103 may be directly covered without disposing the second insulating layer 102.
In this embodiment, the common electrode 151 is located on the upper side of the pixel electrode 123, the common electrode 151 is an electrode with a whole surface structure, and the pixel electrode 123 is a comb-shaped structure with a slit.
The embodiment also provides a manufacturing method of the array substrate, and the manufacturing method is used for manufacturing the array substrate. The manufacturing method in this embodiment is basically the same as that in the first embodiment, except that:
referring to fig. 2c-2d and fig. 3b, in the present embodiment, when the first transparent metal oxide layer 12 is etched, the source electrode 121 and the drain electrode 122 are formed, and the pixel electrode 123 is not formed. And then covering the flat layer 103 after covering the second insulating layer 102, and etching the flat layer 103 and the second insulating layer 102 and forming a bridge hole in the peripheral non-display region. And then covering the second transparent metal oxide layer 15, etching the second transparent metal oxide layer 15 and forming a common electrode 151 and a bridge electrode 152. Before covering the second transparent metal oxide layer 15, the semiconductor layer 14 in the bridging hole needs to be subjected to a reduction process, such as a hydrogen injection process or a plasma sputtering process, so that the semiconductor is converted into a conductor, which is beneficial to reducing the contact resistance between the bridging electrode 152 and the bridging hole.
Further, an insulating spacer layer 104 is covered on the upper surface of the second transparent metal oxide layer 15, and the insulating spacer layer 104, the planarization layer 103, and the second insulating layer 102 are etched to form a contact hole corresponding to the drain electrode 122. Then, the third transparent metal oxide layer 16 is covered, the third transparent metal oxide layer 16 is etched and a pixel electrode 123 is formed, and the pixel electrode 123 is in conductive contact with the drain electrode 122 through the contact hole.
Of course, in other embodiments, the insulating spacer layer 104, the planarization layer 103, and the second insulating layer 102 may be etched after covering the insulating spacer layer 104 and together form a contact hole and a bridge hole, and the bridge electrode 152 is formed of the third transparent metal oxide layer 16.
As shown in fig. 9, the display panel includes the above-mentioned array substrate, an opposite substrate 20 opposite to the array substrate, and a liquid crystal layer 30 disposed between the array substrate and the opposite substrate 20, wherein an upper polarizer 41 is disposed on the opposite substrate 20, a lower polarizer 42 is disposed on the array substrate, and a transmission axis of the upper polarizer 41 is perpendicular to a transmission axis of the lower polarizer 42. In the liquid crystal layer 30, positive liquid crystal molecules (liquid crystal molecules having positive dielectric anisotropy) are used, and in an initial state, the positive liquid crystal molecules are in a lying posture, and the alignment direction of the positive liquid crystal molecules close to the counter substrate 20 is parallel to the alignment direction of the positive liquid crystal molecules 131 close to the array substrate. It is understood that the array substrate and the opposite substrate 20 are further provided with an alignment layer at a layer facing the liquid crystal layer 30, thereby aligning the positive liquid crystal molecules in the liquid crystal layer 30.
In this embodiment, the opposite substrate 20 is a color film substrate, a black matrix 21 and a color resistance layer 22 are disposed on the opposite substrate 20, the black matrix 21 corresponds to the scan line 111, the data line 131, the thin film transistor and the peripheral non-display area, and the black matrix 21 separates the color resistance layers 22. The color resist layer 22 includes color resist materials of three colors of red (R), green (G), and blue (B), and sub-pixels of the three colors of red (R), green (G), and blue (B) are correspondingly formed.
It should be understood by those skilled in the art that the rest of the structure and the operation principle of the present embodiment are the same as those of the first embodiment, and are not described herein again.
In this document, the terms of upper, lower, left, right, front, rear and the like are used to define the positions of structures in the drawings and the positions of the structures relative to each other, only for the sake of clarity and convenience of technical solutions. It is to be understood that the use of the directional terms should not be taken to limit the scope of the claims. It is also to be understood that the terms "first" and "second," etc., are used herein for descriptive purposes only and are not to be construed as limiting in number or order.
Although the present invention has been described with reference to the preferred embodiments, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate (10);
a first metal layer (11) arranged on the substrate (10), wherein the first metal layer (11) comprises a scanning line (111) and a grid electrode (112);
a first insulating layer (101) covering the scan line (111) and the gate electrode (112);
a first transparent metal oxide layer (12) provided on an upper side of the first insulating layer (101), the first transparent metal oxide layer (12) including a source electrode (121) and a drain electrode (122);
a second metal layer (13) arranged on the upper side of the first insulating layer (101), wherein the second metal layer (13) comprises a data line (131), and the data line (131) is electrically connected with the source electrode (121);
a semiconductor layer (14) provided on the upper side of the source electrode (121) and the drain electrode (122), the semiconductor layer (14) including an active layer (141) connecting the source electrode (121) and the drain electrode (122);
and the pixel electrode (123) is arranged on the upper side of the first insulating layer (101), and the pixel electrode (123) is electrically connected with the drain electrode (122).
2. The array substrate of claim 1, wherein the first transparent metal oxide layer (12) further comprises the pixel electrode (123); the array substrate further comprises a second insulating layer (102) covering the semiconductor layer (14) and a second transparent metal oxide layer (15) arranged on the second insulating layer (102), wherein the second transparent metal oxide layer (15) comprises a common electrode (151).
3. The array substrate according to claim 1, further comprising a flat layer (103), a second transparent metal oxide layer (15), an insulating spacer layer (104) and a third transparent metal oxide layer (16) which are sequentially arranged, wherein the flat layer (103) covers a side of the semiconductor layer (14) far away from the substrate (10), the second transparent metal oxide layer (15) comprises a common electrode (151), and the third transparent metal oxide layer (16) comprises the pixel electrode (123).
4. The array substrate according to claim 1, wherein the second metal layer (13) is disposed on the upper surface of the first transparent metal oxide layer (12) and contacts with the upper surface of the first transparent metal oxide layer (12), the second metal layer (13) further comprises a first light shielding portion (133) and a second light shielding portion (134), the first light shielding portion (133) is disposed on the upper surface of the source electrode (121) and contacts with the upper surface of the source electrode (121), the second light shielding portion (134) is disposed on the upper surface of the drain electrode (122) and contacts with the upper surface of the drain electrode (122), and projections of the first light shielding portion (133) and the second light shielding portion (134) on the substrate (10) overlap with projections of the gate electrode (112) on the substrate (10).
5. The array substrate according to claim 4, wherein the semiconductor layer (14) is disposed on the upper surface of the second metal layer (13) and contacts with the upper surface of the second metal layer (13), the active layer (141) covers the first light-shielding portion (133), the second light-shielding portion (134), the source electrode (121), and the drain electrode (122) and contacts with the first light-shielding portion (133), the second light-shielding portion (134), the source electrode (121), and the drain electrode (122), and the semiconductor layer (14) further includes a protection portion (142) covering the upper surface of the second metal layer (13).
6. A method for manufacturing an array substrate, wherein the method is used for manufacturing the array substrate according to any one of claims 1 to 5, and the method comprises:
providing a substrate (10);
forming a first metal layer (11) on the substrate (10), etching the first metal layer (11) and forming a patterned scanning line (111) and a gate electrode (112);
forming a first insulating layer (101) covering the scan line (111) and the gate electrode (112) on the substrate (10);
forming a first transparent metal oxide layer (12) on the upper side of the first insulating layer (101), etching the first transparent metal oxide layer (12) and forming a patterned source electrode (121) and a patterned drain electrode (122);
forming a second metal layer (13) on the upper side of the first insulating layer (101), etching the second metal layer (13) and forming a patterned data line (131), wherein the data line (131) is electrically connected with the source electrode (121);
forming a semiconductor layer (14) on the upper sides of the source electrode (121) and the drain electrode (122), etching the semiconductor layer (14) and forming a patterned active layer (141), wherein the active layer (141) is electrically connected with the source electrode (121) and the drain electrode (122);
and forming a pixel electrode (123) on the upper side of the first insulating layer (101), wherein the pixel electrode (123) is electrically connected with the drain electrode (122).
7. The method for manufacturing the array substrate according to claim 6, wherein the pixel electrode (123) is further formed when the first transparent metal oxide layer (12) is etched; the manufacturing method further comprises the following steps:
forming a second insulating layer (102) covering the semiconductor layer (14) on the substrate (10) and forming a second transparent metal oxide layer (15) on the second insulating layer (102), etching the second transparent metal oxide layer (15) and forming a patterned common electrode (151).
8. The method for manufacturing the array substrate according to claim 6, further comprising:
forming a flat layer (103) covering the semiconductor layer (14) on the substrate (10) and a second transparent metal oxide layer (15) on the flat layer (103), etching the second transparent metal oxide layer (15) and forming a patterned common electrode (151);
forming an insulating spacer layer (104) covering the second transparent metal oxide layer (15) on the substrate (10), etching the planarization layer (103) and the insulating spacer layer (104) and forming a contact hole corresponding to the drain electrode (122);
and forming a third transparent metal oxide layer (16) on the insulating spacing layer (104), etching the third transparent metal oxide layer (16) and forming the patterned pixel electrode (123), wherein the pixel electrode (123) is connected with the drain electrode (122) through the contact hole.
9. The method for manufacturing the array substrate according to claim 6, further comprising:
the second metal layer (13) is arranged on the upper surface of the first transparent metal oxide layer (12) and is in contact with the upper surface of the first transparent metal oxide layer (12), a first light shielding part (133) and a second light shielding part (134) are further formed when the second metal layer (13) is etched, the first light shielding part (133) is positioned on the upper surface of the source electrode (121) and is in contact with the upper surface of the source electrode (121), the second light shielding part (134) is arranged on the upper surface of the drain electrode (122) and is in contact with the upper surface of the drain electrode (122), and the projections of the first light shielding part (133) and the second light shielding part (134) on the substrate (10) are overlapped with the projection part of the grid electrode (112) on the substrate (10);
the semiconductor layer (14) is arranged on the upper surface of the second metal layer (13) and is in contact with the upper surface of the second metal layer (13), the active layer (141) covers the first light shielding portion (133), the second light shielding portion (134), the source electrode (121) and the drain electrode (122) and is in contact with the first light shielding portion (133), the second light shielding portion (134), the source electrode (121) and the drain electrode (122), and a protective portion (142) covering the second metal layer (13) is further formed when the semiconductor layer (14) is etched.
10. A display panel comprising the array substrate of any one of claims 1 to 5, an opposite substrate (20) disposed opposite to the array substrate, and a liquid crystal layer (30) disposed between the array substrate and the opposite substrate (20), wherein an upper polarizer (41) is disposed on the opposite substrate (20), a lower polarizer (42) is disposed on the array substrate, and a transmission axis of the upper polarizer (41) is perpendicular to a transmission axis of the lower polarizer (42).
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| CN103456793A (en) * | 2012-06-04 | 2013-12-18 | 三星显示有限公司 | Thin film transistor, thin film transistor array panel and manufacturing method thereof |
| CN103984171A (en) * | 2013-02-22 | 2014-08-13 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN110190028A (en) * | 2019-06-10 | 2019-08-30 | 北海惠科光电技术有限公司 | Thin-film transistor array base-plate preparation method |
| CN111180471A (en) * | 2020-03-02 | 2020-05-19 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103456793A (en) * | 2012-06-04 | 2013-12-18 | 三星显示有限公司 | Thin film transistor, thin film transistor array panel and manufacturing method thereof |
| CN103984171A (en) * | 2013-02-22 | 2014-08-13 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN110190028A (en) * | 2019-06-10 | 2019-08-30 | 北海惠科光电技术有限公司 | Thin-film transistor array base-plate preparation method |
| CN111180471A (en) * | 2020-03-02 | 2020-05-19 | 南京中电熊猫平板显示科技有限公司 | Array substrate and manufacturing method thereof |
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