CN113584596A - Annealing method for improving flatness of silicon carbide wafer - Google Patents
Annealing method for improving flatness of silicon carbide wafer Download PDFInfo
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- CN113584596A CN113584596A CN202110712354.9A CN202110712354A CN113584596A CN 113584596 A CN113584596 A CN 113584596A CN 202110712354 A CN202110712354 A CN 202110712354A CN 113584596 A CN113584596 A CN 113584596A
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- C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
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Abstract
The invention relates to the technical field of semiconductor processing, and particularly discloses an annealing method for improving the flatness of a silicon carbide wafer, which comprises the following steps: s1, placing the silicon carbide wafer in an annealing furnace; s2, vacuumizing the annealing furnace, introducing protective gas, and keeping the pressure in the annealing furnace stable; s3, slowly and uniformly raising the temperature in the annealing furnace to the annealing temperature, and controlling the temperature gradient in the annealing furnace to be smaller than a first temperature gradient value; s4, applying pressure to the silicon carbide wafer and keeping the silicon carbide wafer; s5, removing the pressure on the silicon carbide wafer, and continuing to perform heat preservation; and S6, slowly and uniformly cooling the temperature in the annealing furnace to room temperature, and controlling the temperature gradient in the annealing furnace to be smaller than a first temperature gradient value. The annealing method of the invention can reduce the internal stress of the silicon carbide wafer, reduce the BOW (BOW) and WARP (WARP) of the silicon carbide wafer, improve the quality of the silicon carbide wafer, provide convenience for subsequent processing and improve the yield.
Description
Technical Field
The invention relates to the technical field of semiconductor processing, and particularly discloses an annealing method for improving the flatness of a silicon carbide wafer.
Background
The most mature method for growing the silicon carbide single crystal at present is a Physical Vapor Transport (PVT) method, and the growth mechanism of the method is as follows: sublimating and decomposing the carbon powder and the silicon powder into Si atoms and Si at a high temperature of over 2000 DEG C2C molecule and SiC2And gas phase substances such as molecules and the like are conveyed to the silicon carbide seed crystal with lower temperature under the driving of the temperature gradient to form the silicon carbide crystal. The silicon carbide crystal with a specific crystal form can be grown by controlling the process parameters of temperature field, air flow and the like of PVT. The silicon carbide single crystal material mainly comprises a conduction type substrate and a semi-insulating substrate. The problem of high-quality and large-size silicon carbide single crystal materials is the first solution to the development of silicon carbide technology, and the key development direction is to continuously increase the size of a wafer and reduce the defect density.
When the crystal growth is performed by using the PVT method, a large shear thermal stress exists inside the crystal due to a change in thermal field temperature during the growth. After the ingot is subjected to subsequent mechanical processing such as edge flattening, rounding, cutting and the like, thermal stress is generated in the crystal, flatness parameters such as BOW (BOW) and WARP (WARP) of the crystal are deteriorated, and if the stress cannot be released, the crystal is easy to generate accidents such as wafer warping and cracking and the like which affect the yield rate in the subsequent processing processes such as grinding, polishing and the like. Meanwhile, the silicon carbide crystal has high requirements on flatness parameters such as BOW (BOW), WARP (WARP) and the like, and is almost difficult to correct in the subsequent grinding and polishing process, so that the BOW (BOW) and the WARP (WARP) of the wafer need to be managed and controlled in time in the early processing.
Therefore, the feasibility of subsequent processing of silicon carbide wafers is of great importance in order to reduce internal stress and improve the flatness of the wafers. The prior art method is only limited to reducing the internal stress of the wafer and does not consider the requirement of material flatness.
Disclosure of Invention
The invention mainly aims to provide an annealing method for improving the flatness of a silicon carbide wafer, which can reduce the internal stress of the silicon carbide wafer, reduce the BOW (BOW) and the WARP (WARP) of the silicon carbide wafer, improve the quality of the silicon carbide wafer, facilitate subsequent processing and improve the yield.
In order to achieve the purpose, the invention provides an annealing method for improving the flatness of a silicon carbide wafer, which comprises the following steps:
s1, placing the silicon carbide wafer in an annealing furnace;
s2, vacuumizing the annealing furnace, introducing protective gas, and keeping the pressure in the annealing furnace stable;
s3, slowly and uniformly raising the temperature in the annealing furnace to the annealing temperature, and controlling the temperature gradient in the annealing furnace to be smaller than a first temperature gradient value;
s4, applying pressure to the silicon carbide wafer and keeping the silicon carbide wafer;
s5, removing the pressure on the silicon carbide wafer, and continuing to perform heat preservation;
and S6, slowly and uniformly cooling the temperature in the annealing furnace to room temperature, and controlling the temperature gradient in the annealing furnace to be smaller than a first temperature gradient value.
In addition, the annealing method for improving the flatness of the silicon carbide wafer according to the present invention may have the following additional features.
According to an embodiment of the present invention, step S1 includes: and stacking the silicon carbide wafers on a graphite flat plate, separating two adjacent silicon carbide wafers by using carbon paper, and placing the stacked silicon carbide wafers and the graphite flat plate in an annealing furnace.
According to one embodiment of the invention, the deviation of the total thickness of the graphite flat plate is less than 10 microns, the linear thickness variation is less than 2 microns, and the surface roughness of the contact surface of the graphite flat plate and the silicon carbide wafer is less than 1 micron.
According to one embodiment of the invention, the area of the graphite flat plate is larger than the area of the silicon carbide wafer, and the thickness of the carbon paper is at least 50 micrometers.
According to one embodiment of the invention, the annealing furnace is vacuumized in step S2 until the vacuum degree is not less than 100 mbar.
According to one embodiment of the invention, the protective gas in the step S2 is selected from nitrogen or argon, and after the gas is introduced, the pressure in the annealing furnace is kept at 0.9-1.1 standard atmospheric pressure.
According to one embodiment of the invention, the temperature rising rate of the slow and uniform temperature rising in the step S3 is 1-5 ℃/min.
According to an embodiment of the invention, when the temperature in the annealing furnace is higher than 900 ℃, the temperature rise rate of the slow and uniform temperature rise is controlled to be 1-2 ℃/min, the annealing temperature is 1200-.
According to one embodiment of the invention, step S4 includes applying pressure to the silicon carbide wafer for 3-5 hours using a graphite load weight, wherein the graphite load weight has a total thickness variation of less than 10 microns and a linear thickness variation of less than 2 microns, the surface roughness of the contact surface of the graphite load weight and the silicon carbide wafer is less than 1 micron, and the area of the graphite load weight is larger than that of the silicon carbide wafer.
According to an embodiment of the invention, the temperature rising rate of the slow and uniform temperature rising in the step S6 is 1-5 ℃/min, when the temperature in the annealing furnace is higher than 900 ℃, the temperature rising rate of the slow and uniform temperature rising is controlled to be 1-2 ℃/min, the room temperature is 20-50 ℃, and the first temperature gradient value is 5 ℃/cm.
Compared with the prior art, the invention has the following beneficial effects:
the annealing method of the invention can reduce the internal stress of the silicon carbide wafer, reduce the BOW (BOW) and WARP (WARP) of the silicon carbide wafer, improve the quality of the silicon carbide wafer, provide convenience for subsequent processing and improve the yield.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a flow chart of an annealing process for enhancing the planarity of a silicon carbide wafer in accordance with an embodiment of the present invention;
FIG. 2 is a graph of BOW (BOW) and WARP (WARP) measurements before annealing of a wafer in accordance with an embodiment of the present invention;
FIG. 3 is a graph of BOW (BOW) and WARP (WARP) measurements after annealing of a wafer A in accordance with one embodiment of the present invention;
FIG. 4 is a graph of BOW (BOW) and WARP (WARP) measurements before annealing of a B wafer in accordance with an embodiment of the present invention;
FIG. 5 is a graph of BOW (BOW) and WARP (WARP) measurements after annealing of a B wafer in accordance with an embodiment of the present invention;
FIG. 6 is a graph of BOW (BOW) and WARP (WARP) measurements before annealing of a C wafer in accordance with an embodiment of the present invention;
FIG. 7 is a graph of BOW (BOW) and WARP (WARP) measurements after annealing of a C wafer in accordance with an embodiment of the present invention;
FIG. 8 is a graph of BOW (BOW) and WARP (WARP) measurements before annealing a D wafer in accordance with one embodiment of the present invention;
FIG. 9 is a graph of BOW (BOW) and WARP (WARP) measurements after annealing of a D wafer in accordance with one embodiment of the present invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
As shown in fig. 1, an embodiment of the present invention provides an annealing method for improving flatness of a silicon carbide wafer, comprising the steps of:
s1 wafer stacking: stacking 4 6-inch N-type silicon carbide wafers (numbered A, B, C, D from bottom to top) on a graphite flat plate, wherein the flatness of the graphite flat plate requires that TTV is less than 10 micrometers, LTV is less than 2 micrometers, the surface roughness of the contact surface of the graphite flat plate and the wafer is less than 1 micrometer, the area of the graphite flat plate is larger than that of the wafer, the wafers are separated by carbon paper with the thickness of 100 micrometers, and the orderly and flatly stacked wafers and the graphite flat plate are placed in an annealing furnace;
and S2 gas protection: vacuumizing the annealing furnace to a certain vacuum degree, wherein the vacuum degree is less than 50mbar, introducing nitrogen as protective gas, and keeping the pressure in the annealing furnace to be stable at about one atmosphere;
s3, slowly heating: the temperature in the furnace is slowly and uniformly raised to 900 ℃ at the temperature rise rate of 5 ℃/min, and then the temperature rise rate is modified to 1 ℃/min to continue raising the temperature to the annealing temperature of 1450 ℃. In the process, the temperature gradient in the furnace is controlled within 3 ℃/cm;
s4, pressure application and heat preservation: when the temperature reaches the annealing temperature, a graphite load weight is applied to the wafer, the weight of the graphite load weight is 20Kg, the flatness of the graphite load weight requires that the total thickness deviation (TTV for short) is less than 10 microns, the linear thickness variation (LTV for short) is less than 2 microns, the surface roughness of the contact surface with the wafer is less than 1 micron, and the area of the graphite load weight is larger than that of the wafer. This state was maintained for 4 hours;
s5 removing pressure: removing the graphite load weight, and continuously preserving the heat for 2 hours;
s6, slowly cooling: the temperature in the furnace is slowly and uniformly reduced to 900 ℃ at the cooling rate of 1 ℃/min, and then the temperature is continuously reduced to 20 ℃ at the room temperature by modifying the cooling rate to be 3 ℃/min. In the process, the temperature gradient in the furnace is controlled within 3 ℃/cm.
The annealed A, B, C, D four silicon carbide wafers were removed and the annealed BOW and WARP of the A, B, C, D four silicon carbide wafers were measured as shown in fig. 2-9. And compared to the BOW, WARP, of A, B, C, D four silicon carbide wafers before annealing, as shown in table 1:
TABLE 1 BOW (BOW), WARP (WARP) before and after annealing of four silicon carbide wafers
As can be seen from Table 1, when the silicon carbide wafer is annealed and pressure is applied to the silicon carbide wafer, good trimming effects can be achieved on BOW (BOW) and WARP (WARP) of the silicon carbide wafer, and the quality and yield of the silicon carbide wafer are improved.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.
Claims (10)
1. An annealing method for improving the flatness of a silicon carbide wafer is characterized by comprising the following steps:
s1, placing the silicon carbide wafer in an annealing furnace;
s2, vacuumizing the annealing furnace, introducing protective gas, and keeping the pressure in the annealing furnace stable;
s3, slowly and uniformly raising the temperature in the annealing furnace to the annealing temperature, and controlling the temperature gradient in the annealing furnace to be smaller than a first temperature gradient value;
s4, applying pressure to the silicon carbide wafer and keeping the silicon carbide wafer;
s5, removing the pressure on the silicon carbide wafer, and continuing to perform heat preservation;
and S6, slowly and uniformly cooling the temperature in the annealing furnace to room temperature, and controlling the temperature gradient in the annealing furnace to be smaller than a first temperature gradient value.
2. The annealing method for improving the flatness of a silicon carbide wafer according to claim 1, wherein the step S1 includes: and stacking the silicon carbide wafers on a graphite flat plate, separating two adjacent silicon carbide wafers by using carbon paper, and placing the stacked silicon carbide wafers and the graphite flat plate in an annealing furnace.
3. The annealing method for improving the flatness of a silicon carbide wafer according to claim 2, wherein the graphite flat plate has a total thickness variation of less than 10 μm and a linear thickness variation of less than 2 μm, and the surface roughness of the contact surface of the graphite flat plate with the silicon carbide wafer is less than 1 μm.
4. The annealing method for improving the flatness of a silicon carbide wafer according to claim 3, wherein the area of the graphite flat plate is larger than that of the silicon carbide wafer, and the thickness of the carbon paper is at least 50 μm.
5. The annealing method for improving the flatness of a silicon carbide wafer according to claim 1, wherein the annealing furnace is vacuumed up to a degree of vacuum of not less than 100mbar in step S2.
6. The annealing method for improving the flatness of a silicon carbide wafer according to claim 1, wherein the protective gas in the step S2 is selected from nitrogen gas or argon gas, and after the gas is introduced, the pressure in said annealing furnace is maintained at 0.9 to 1.1 atm.
7. The annealing method for improving the flatness of a silicon carbide wafer according to claim 1, wherein the temperature rise rate of the slow uniform temperature rise of step S3 is 1-5 ℃/min.
8. The annealing method for improving the flatness of a silicon carbide wafer according to claim 7, wherein when the temperature in the annealing furnace is higher than 900 ℃, the temperature rise rate of the slow and uniform temperature rise is controlled to be 1-2 ℃/min, the annealing temperature is 1200 ℃ and 1600 ℃, and the first temperature gradient value is 5 ℃/cm.
9. The annealing method for improving the flatness of a silicon carbide wafer according to claim 1, wherein the step S4 includes applying pressure to the silicon carbide wafer for 3-5 hours by using a graphite load weight, wherein the graphite load weight has a total thickness deviation of less than 10 micrometers and a linear thickness variation of less than 2 micrometers, the surface roughness of the contact surface of the graphite load weight with the silicon carbide wafer is less than 1 micrometer, and the area of the graphite load weight is larger than that of the silicon carbide wafer.
10. The annealing method for improving the flatness of a silicon carbide wafer according to claim 1, wherein the temperature rising rate of the slow uniform temperature rising of step S6 is 1-5 ℃/min, and when the temperature in the annealing furnace is higher than 900 ℃, the temperature rising rate of the slow uniform temperature rising is controlled to be 1-2 ℃/min, the room temperature is 20-50 ℃, and the first temperature gradient value is 5 ℃/cm.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114293263A (en) * | 2021-12-30 | 2022-04-08 | 广东省科学院半导体研究所 | Protection device and method for preventing surface decomposition and impurity incorporation under high-temperature thermal annealing |
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| KR20130034179A (en) * | 2011-09-28 | 2013-04-05 | 주식회사 티씨케이 | Manufacturing method for sic substrate |
| CN103114336A (en) * | 2013-03-12 | 2013-05-22 | 中国科学院上海硅酸盐研究所 | Method for annealing silicon carbide wafer |
| CN105734673A (en) * | 2016-04-26 | 2016-07-06 | 北京世纪金光半导体有限公司 | Method for obtaining high machining precision of large silicon carbide single crystal wafer |
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| JP2000226299A (en) * | 1999-02-04 | 2000-08-15 | Denso Corp | Production of single crystal silicon carbide thin film and single crystal silicon carbide thin film |
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| CN103114336A (en) * | 2013-03-12 | 2013-05-22 | 中国科学院上海硅酸盐研究所 | Method for annealing silicon carbide wafer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114293263A (en) * | 2021-12-30 | 2022-04-08 | 广东省科学院半导体研究所 | Protection device and method for preventing surface decomposition and impurity incorporation under high-temperature thermal annealing |
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