CN113574656A - 一种数据处理装置及方法 - Google Patents

一种数据处理装置及方法 Download PDF

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Publication number
CN113574656A
CN113574656A CN202080001141.9A CN202080001141A CN113574656A CN 113574656 A CN113574656 A CN 113574656A CN 202080001141 A CN202080001141 A CN 202080001141A CN 113574656 A CN113574656 A CN 113574656A
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China
Prior art keywords
chip
processing unit
dedicated
data processing
dedicated processing
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Pending
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CN202080001141.9A
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English (en)
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檀珠峰
李宗岩
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of CN113574656A publication Critical patent/CN113574656A/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/409—Mechanical coupling
    • G06F13/4095—Mechanical coupling in incremental bus architectures, e.g. bus stacks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/485—Task life-cycle, e.g. stopping, restarting, resuming execution
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5044—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering hardware capabilities
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Microcomputers (AREA)
  • Power Sources (AREA)

Abstract

本申请实施例公开了一种数据处理装置及相关方法，其中，一种数据处理装置，可包括堆叠封装的第一芯片和第二芯片；所述第一芯片包括通用处理器、总线和至少一个第一专用处理单元DPU，所述通用处理器和所述至少一个第一专用处理单元连接至所述总线，所述通用处理器用于产生数据处理任务；所述第二芯片包括第二专用处理单元，所述至少一个第一专用处理单元中的一个或多个第一专用处理单元和所述第二专用处理单元中的至少一个能够基于所述计算功能处理所述数据处理任务的至少一部分；其中，所述第一芯片和所述第二芯片通过芯片间互连线相互连接。该数据处理装置可以在不增加产品体积的情况下，满足用户越来越高的功耗和运算需求。

Description

PCT国内申请，说明书已公开。

Claims (13)

  1. PCT国内申请，权利要求书已公开。
CN202080001141.9A 2020-02-28 2020-02-28 一种数据处理装置及方法 Pending CN113574656A (zh)

Applications Claiming Priority (1)

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PCT/CN2020/077290 WO2021168837A1 (zh) 2020-02-28 2020-02-28 一种数据处理装置及方法

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CN113574656A true CN113574656A (zh) 2021-10-29

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US (1) US20220405228A1 (zh)
EP (1) EP4086948A4 (zh)
CN (1) CN113574656A (zh)
WO (1) WO2021168837A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023098031A1 (zh) * 2021-11-30 2023-06-08 华为技术有限公司 数据访问方法及计算设备
WO2023123395A1 (zh) * 2021-12-31 2023-07-06 华为技术有限公司 一种计算任务处理装置、方法及电子设备

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN115934632B (zh) * 2023-02-09 2023-05-16 南京芯驰半导体科技有限公司 数据处理方法、装置、电子设备及存储介质

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9065722B2 (en) * 2012-12-23 2015-06-23 Advanced Micro Devices, Inc. Die-stacked device with partitioned multi-hop network
US11295506B2 (en) * 2015-09-16 2022-04-05 Tmrw Foundation Ip S. À R.L. Chip with game engine and ray trace engine
CN106209121B (zh) * 2016-07-15 2019-04-09 中国科学院微电子研究所 一种多模多核的通信基带SoC芯片
US10317459B2 (en) * 2017-04-03 2019-06-11 Nvidia Corporation Multi-chip package with selection logic and debug ports for testing inter-chip communications
US10261903B2 (en) * 2017-04-17 2019-04-16 Intel Corporation Extend GPU/CPU coherency to multi-GPU cores
KR102455427B1 (ko) * 2017-12-20 2022-10-17 삼성전자주식회사 반도체 패키지 및 이의 제조 방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023098031A1 (zh) * 2021-11-30 2023-06-08 华为技术有限公司 数据访问方法及计算设备
WO2023123395A1 (zh) * 2021-12-31 2023-07-06 华为技术有限公司 一种计算任务处理装置、方法及电子设备

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US20220405228A1 (en) 2022-12-22
EP4086948A1 (en) 2022-11-09
WO2021168837A1 (zh) 2021-09-02
EP4086948A4 (en) 2023-01-11

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