CN113555293B - Method for testing temperature stress field of silicon substrate type transceiver component - Google Patents
Method for testing temperature stress field of silicon substrate type transceiver component Download PDFInfo
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- CN113555293B CN113555293B CN202110826137.2A CN202110826137A CN113555293B CN 113555293 B CN113555293 B CN 113555293B CN 202110826137 A CN202110826137 A CN 202110826137A CN 113555293 B CN113555293 B CN 113555293B
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
Abstract
The invention relates to the field of semiconductor testing, in particular to a method for testing a temperature stress field of a silicon substrate type transceiver component, which comprises the following steps: manufacturing a lower insulating layer, manufacturing a stress sensing unit, manufacturing an upper insulating layer, wiring, stacking interconnection, stress testing, and outputting temperature and stress values. The invention has the advantages that: compared with the prior art, the temperature inside the packaged or assembled component can be tested, the high-precision measurement of the stress field inside or on the surface of the component can be realized, and the precision of the stress distribution result is higher.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a method for testing a temperature stress field of a silicon substrate type receiving and transmitting component, which is specially used for testing the three-dimensional temperature stress field of a large-size high-power-consumption vertically stacked silicon substrate type receiving and transmitting component.
Background
In the prior art, as disclosed in chinese patent publication No. CN111276475B, a three-dimensional heterogeneous integrated rf front-end microsystem is disclosed, where the microsystem adopts a stacked structure of multiple layers of silicon adapter plates, and multiple power reconfigurable transceiver chips are embedded in one or more layers of silicon adapter plates; the power management chip is embedded in a layer of silicon adapter plate provided with a power reconfigurable transceiver chip; the ultra-wideband mixer chip and the radio frequency switch matrix chip are embedded in the same layer of silicon adapter plate; each adjustable filter chip is arranged between two layers of silicon adapter plates through integrated processing to form a sandwich structure, and the sandwich structure is arranged on the outer side of the layer where the ultra-wideband frequency mixer chip is arranged or between the layer where the ultra-wideband frequency mixer chip is arranged and the layer where the power management chip is arranged; each power reconfigurable transceiver chip is connected with the radio frequency switch matrix chip through an adjustable filter chip; the radio frequency switch matrix chip is connected with the ultra-wideband mixer chip; the power management chip is used for providing control signals and power supply. The above-described patent technology describes a typical rf front-end microsystem in the prior art that employs a multilayer silicon interposer stack structure.
The transceiver component is an important component of the radar radio frequency front end, the silicon chip transceiver component of the vertical stacking framework is based on silicon-based advanced packaging, the packaging density is high, the size is small, the integration level of the radar complete machine can be greatly improved, the typical structure is shown in fig. 1, a box body consisting of a single-layer or multi-layer silicon substrate and a silicon cap and functional chips in the box body are formed, the transceiver component specifically comprises a second-layer silicon cap 1, a second-layer silicon substrate 2, a first-layer silicon cap 3, a first-layer silicon substrate 4, a second-layer functional chip 5, second-layer solder balls 6, a first-layer functional chip 7, a first-layer solder ball 8 and an assembly substrate 9, the first-layer silicon substrate 4 is arranged above the assembly substrate 9, the first-layer silicon substrate 4 is connected with the assembly substrate 9 through the first-layer solder ball 8, the first-layer silicon cap 3 is arranged above the first-layer silicon substrate 4, the first-layer functional chip 7 is arranged between the first-layer silicon substrate 4 and the first-layer silicon cap 3, the second-layer silicon cap 3 is arranged above the first-layer silicon cap 2, the second-layer silicon cap 2 is arranged above the first-layer silicon cap 3, the second-layer silicon cap 2 is connected with the second-layer silicon substrate 2 through the second-layer silicon substrate 2, and the second-layer 1 is arranged between the second-layer silicon cap 2 and the second-layer substrate 2.
The vertical stacking silicon substrate type receiving and transmitting component is large in area, which is more than 10mm in size and 10mm in size, integrates materials with different thermal expansion coefficients such as silicon, gallium arsenide, gallium nitride, organic media, metal and the like, and is easy to generate thermal mismatch when being assembled through processes such as reflow soldering, thermal bonding and the like or being assembled with other structures such as a substrate in a subsequent high density, so that large residual stress is formed, and the service life of the component is influenced. Considering that the chip-type transceiver component is generally higher in power and large in heat power consumption in a working state, whether the junction temperature of the chip in the component is in a reasonable interval or not, unbalanced temperature distribution inside and outside and thermal stress generated by different materials can also reduce the service life of the component, and the chip-type transceiver component is a key factor for limiting the reliability of a system. Therefore, when the structure and the process of the component are optimally designed based on manufacturability and reliability, three-dimensional temperature and stress distribution of the component in different states of different design schemes need to be compared. The accurate real-time three-dimensional temperature and stress distribution measurement method is particularly important to the design of the silicon substrate type transceiver component of the vertical stacking framework.
At present, a thermal imager can be used for monitoring the temperature distribution of a chip in real time, which is the most common temperature measurement means at present, but the method can only test the surface of the chip and cannot measure the inside of a packaged or assembled component. The conventional stress test is based on a resistance strain gauge, the strain gauge is required to be adhered to a surface to be tested through glue, and then a signal is led out through a lead, so that the strain gauge is usually large, even a square area of 10mm is only provided with one strain test unit, and the strain gauge cannot be integrated in a silicon substrate type receiving and transmitting component, so that high-precision measurement of the stress field in the component or on the surface cannot be realized. The moire fringe method is an indirect measurement method, is limited by the precision of a finite element model, and has a certain difference from the actual result of the calculation of the stress distribution.
Therefore, in order to optimally design a component based on temperature and stress distribution, it is necessary to develop a test method for a vertically stacked component, and analyze the three-dimensional distribution temperature and stress field of the multi-layer stacked structure inside the component in an assembled or operating state.
Based on the above drawbacks, the present inventors have made long-term studies and practices to obtain the present invention.
Disclosure of Invention
The technical problems to be solved by the invention are as follows:
in the prior art, when the temperature stress field of the silicon substrate type transceiver component is tested, the internal temperature of the packaged or assembled component cannot be tested, the high-precision measurement of the internal or surface stress field of the component cannot be realized, and the technical problem of low precision of the stress distribution calculation result is solved.
The invention solves the technical problems by the following technical means: a method for testing a temperature stress field of a silicon substrate type transceiver component comprises the following steps:
s1, manufacturing a lower insulating layer
Manufacturing a lower insulating layer in a substrate to-be-tested area of each component of the silicon substrate type transceiver component;
s2, manufacturing a heating unit and a temperature sensing unit
Manufacturing a heating unit and a temperature sensing unit on a lower insulating layer of an active heating area such as a chip and the like, and manufacturing a temperature sensing unit on a lower insulating layer of a non-active heating area such as a silicon cap, a silicon substrate and the like;
s3, manufacturing stress sensing unit
Manufacturing a stress sensing unit on a lower insulating layer of an active heating area such as a chip and a lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate;
s4, manufacturing an upper insulating layer and a lead
Sequentially manufacturing an upper insulating layer and a lead on the heating unit, the temperature sensing unit and the stress sensing unit;
s5, stacking interconnect
Stacking and interconnecting all components of the silicon substrate type transceiver component to form the silicon substrate type transceiver component, and leading out or leading in signal output and power input of the heating unit, the temperature sensing unit and the stress sensing unit through leads;
s6, stress test
The stacked and interconnected silicon substrate transceiver components are subjected to stress test in a room temperature natural state, so that residual stress of the assembled components is obtained;
s7, temperature and stress value output
And controlling the heating of the silicon substrate type receiving and transmitting component, and testing to obtain the output of the temperature sensing unit and the stress sensing unit, thereby obtaining the temperature and the stress value of the working state of the component.
The method for testing the temperature stress field of the silicon substrate type transceiver component, disclosed by the invention, has the advantages that the key size is small, the integration level is high, the capability boundary of the existing testing means is broken through, the temperature and stress distribution of the component in the working state can be measured in real time based on the high precision of the simulation component, the structural stress singular point and the junction temperature of the key functional chip can be found, and the basis is provided for the design of the component. The method comprises the steps of manufacturing a heating unit, a temperature sensing unit, a stress sensing unit and the like on the surface of each layer of to-be-tested area of the vertical stacking assembly. And then can play initiative heating, temperature and stress sensing's effect simultaneously to can be with heating unit, temperature sensing unit and stress sensing unit etc. integrate on various substrates, realize the test and the integration of the arbitrary district that waits to test of each layer inside the subassembly. Compared with the prior art, the temperature inside the packaged or assembled component can be tested, the high-precision measurement of the stress field inside or on the surface of the component can be realized, and the precision of the stress distribution result is higher.
Preferably, the method further comprises the following steps:
and (3) manufacturing parts: manufacturing components according to the same structure, materials and process as those of the components of the silicon substrate type transceiver component to be tested, wherein the manufactured components comprise a silicon cap, a silicon substrate and a chip;
the step of making the component is preceded by step s1.
The method replaces an actual assembly with an analog assembly manufactured based on the same structure, material and process, comprehensively simulates the power consumption, structure and material of the actual assembly, and realizes the test and integration of any to-be-tested area of each layer in the assembly. The temperature and stress distribution of the module in the working state can be measured based on the real-time high precision of the analog module, the structural stress singular point and the junction temperature of the key functional chip can be found, and a basis is provided for the module design.
Preferably, the substrate in the step s1 is made of silicon or gallium arsenide.
Optimally, the heating unit and the temperature sensing unit are made of metal platinum films, and the heating unit and the temperature sensing unit are both in a snake-shaped structure.
Preferably, the stress sensing units are made of films made of copper-nickel alloy or nickel-chromium alloy, each stress sensing unit comprises two perpendicular films, and the two films in each stress sensing unit are identical in structure and are all in a serpentine structure.
The heating unit, the temperature sensing unit and the stress sensing unit manufactured based on the semiconductor film technology have small critical dimensions and high integration level, and are convenient for realizing high-precision measurement of the temperature stress field in the assembly or on the surface.
The two vertical films of each stress sensing unit, namely the two snake-shaped resistors which are orthogonally distributed, can respectively measure the horizontal stress in the two corresponding orthogonal directions, so as to reflect the actual stress of the region to be tested, and the test result is more accurate.
Preferably, the method further comprises the following steps:
stress sensing calibration: calibrating the stress sensing unit by using a four-point bending method at different temperatures to obtain the resistance stress relation of the stress sensing unit: r=r 0 (1+ασ) (1+βT) wherein R 0 Is the resistance at room temperature, T is the working temperature, sigma is the stress, and alpha and beta areThe constant coefficient, the actual temperature value calculated is the temperature reference of the pressure calibration, the root mean square value of the stress measured by two films distributed vertically of the same stress sensing unit is the actual stress of the stress sensing unit;
the stress sensing calibration step is performed between steps s4 and s 5.
The stress sensing unit is calibrated and compensated, and the measurement accuracy is high, so that high-fidelity three-dimensional reproduction of the stress field can be realized.
Preferably, the method further comprises the following steps:
and (3) heating calibration: the heating of the heating unit is calibrated under the thermal infrared imager so that the heating unit is the same as the heating of the actual chip;
the heat calibration step is performed between steps s4 and s 5.
The heating calibration can ensure that the heating condition of the heating unit is the same as the heating condition of the chip in actual use as far as possible, so that the heating condition of the actual chip is accurately simulated, and the actual parameters are fed back better.
Preferably, the method further comprises the following steps:
standard signal output: leading out the lead wires, respectively forming a Wheatstone bridge with external standard resistors through a multi-channel signal switching module, and carrying out signal amplification through a high-impedance amplification module to obtain standard signal output;
the standard signal outputting step is performed between steps s4 and s 5.
Preferably, the method further comprises the following steps:
temperature sensing calibration: calibrating the temperature sensing unit in a standard incubator to obtain the resistance temperature relation of the temperature sensing unit: r=r 0 (1+αT) wherein R 0 The resistance is at room temperature, T is the working temperature, and alpha is a constant coefficient;
the temperature sensing calibration step is performed between steps s4 and s 5.
The temperature sensing unit is calibrated and compensated, and the measurement accuracy is high, so that high-fidelity three-dimensional reproduction of a temperature field can be realized.
The optimization device also comprises a class I test unit and a class II test unit;
the I-type test unit comprises a heating unit, a temperature sensing unit and a stress sensing unit, and the I-type test unit array is distributed on a lower insulating layer of an active heating area such as a chip;
the II-type test unit comprises a temperature sensing unit and a stress sensing unit, and the II-type test unit array is distributed on a lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate.
The active heating areas such as the chip and the like can generate heat in actual operation, so that the heating units, the temperature sensing units and the stress sensing units are required to be arranged at the same time, the non-active heating areas such as the silicon cap and the silicon substrate and the like do not generate heat in actual operation, and only the temperature sensing units and the stress sensing units are required to be arranged, so that the defined I-type test unit array is distributed on the lower insulating layer of the active heating areas such as the chip and the like; the II-type test unit array is distributed on the lower insulating layer of the non-active heating area such as the silicon cap, the silicon substrate and the like, so that the whole coverage of the area to be tested is realized, and the three-dimensional reproduction of the temperature and the stress field is realized.
The invention has the advantages that:
1. the method for testing the temperature stress field of the silicon substrate type transceiver component, disclosed by the invention, has the advantages that the key size is small, the integration level is high, the capability boundary of the existing testing means is broken through, the temperature and stress distribution of the component in the working state can be measured in real time based on the high precision of the simulation component, the structural stress singular point and the junction temperature of the key functional chip can be found, and the basis is provided for the design of the component. The method comprises the steps of manufacturing a heating unit, a temperature sensing unit, a stress sensing unit and the like on the surface of each layer of to-be-tested area of the vertical stacking assembly. And then can play initiative heating, temperature and stress sensing's effect simultaneously to can be with heating unit, temperature sensing unit and stress sensing unit etc. integrate on various substrates, realize the test and the integration of the arbitrary district that waits to test of each layer inside the subassembly. Compared with the prior art, the temperature inside the packaged or assembled component can be tested, the high-precision measurement of the stress field inside or on the surface of the component can be realized, and the precision of the stress distribution result is higher.
2. The method replaces an actual assembly with an analog assembly manufactured based on the same structure, material and process, comprehensively simulates the power consumption, structure and material of the actual assembly, and realizes the test and integration of any to-be-tested area of each layer in the assembly. The temperature and stress distribution of the module in the working state can be measured based on the real-time high precision of the analog module, the structural stress singular point and the junction temperature of the key functional chip can be found, and a basis is provided for the module design.
3. The heating unit, the temperature sensing unit and the stress sensing unit manufactured based on the semiconductor film technology have small critical dimensions and high integration level, and are convenient for realizing high-precision measurement of the temperature stress field in the assembly or on the surface. The two vertical films of each stress sensing unit, namely the two snake-shaped resistors which are orthogonally distributed, can respectively measure the horizontal stress in the two corresponding orthogonal directions, so as to reflect the actual stress of the region to be tested, and the test result is more accurate.
4. The stress sensing unit is calibrated and compensated, and the measurement accuracy is high, so that high-fidelity three-dimensional reproduction of the stress field can be realized.
5. The heating calibration can ensure that the heating condition of the heating unit is the same as the heating condition of the chip in actual use as far as possible, so that the heating condition of the actual chip is accurately simulated, and the actual parameters are fed back better.
The temperature sensing unit is calibrated and compensated, and the measurement accuracy is high, so that high-fidelity three-dimensional reproduction of a temperature field can be realized.
6. The active heating areas such as the chip and the like can generate heat in actual operation, so that the heating units, the temperature sensing units and the stress sensing units are required to be arranged at the same time, the non-active heating areas such as the silicon cap and the silicon substrate and the like do not generate heat in actual operation, and only the temperature sensing units and the stress sensing units are required to be arranged, so that the defined I-type test unit array is distributed on the lower insulating layer of the active heating areas such as the chip and the like; the II-type test unit array is distributed on the lower insulating layer of the non-active heating area such as the silicon cap, the silicon substrate and the like, so that the whole coverage of the area to be tested is realized, and the three-dimensional reproduction of the temperature and the stress field is realized.
Drawings
FIG. 1 is a schematic diagram of a prior art silicon-based transceiver component;
FIG. 2 is a schematic diagram of a temperature stress field test of a silicon substrate transceiver component in an embodiment of the invention;
FIG. 3 is a schematic diagram of a class I test cell in accordance with an embodiment of the present invention;
FIG. 4 is a schematic diagram of a class II test unit according to an embodiment of the invention;
wherein, the liquid crystal display device comprises a liquid crystal display device,
the second-layer silicon cap-1, the second-layer silicon substrate-2, the first-layer silicon cap-3, the first-layer silicon substrate-4, the second-layer functional chip-5, the second-layer solder ball-6, the first-layer functional chip-7, the first-layer solder ball-8 and the assembly substrate-9;
the device comprises a heating unit-10, a temperature sensing unit-20 and a stress sensing unit-30;
class I test unit-A, class II test unit-B.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described in the following in conjunction with the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
A method for testing a temperature stress field of a silicon substrate type transceiver component comprises the following steps:
and (3) manufacturing parts: the components are manufactured according to the same structure, materials and process as those of the components of the silicon substrate transceiver component to be tested, and the manufactured components comprise a silicon cap, a silicon substrate and a chip. That is, the silicon cap, silicon substrate and chip of each layer, including possible surface interconnect layers and vertical interconnect layers, are fabricated based on the same structure, materials and process as the vertically stacked silicon substrate transceiver component.
After the component manufacturing step is completed, step s1 is performed.
s1, manufacturing a lower insulating layer
Manufacturing a lower insulating layer in a substrate to-be-tested area of each component of the silicon substrate type transceiver component; the substrate is made of silicon or gallium arsenide, and includes but is not limited to silicon, gallium arsenide, and the like. Specifically, a lower insulating layer is manufactured in a region to be tested of a substrate through a semiconductor thin film process such as magnetron sputtering, chemical vapor deposition, electron beam evaporation and the like, and the subsequent serpentine structures of the heating unit 10, the temperature sensing unit 20, the stress sensing unit 30 and the like are insulated and isolated from the substrate by the lower insulating layer.
s2, manufacturing the heating unit 10 and the temperature sensing unit 20
Manufacturing a heating unit 10 and a temperature sensing unit 20 on a lower insulating layer of an active heating area such as a chip through a semiconductor process, and manufacturing a temperature sensing unit 20 on a lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate;
the heating unit 10 and the temperature sensing unit 20 are made of metal platinum films, the heating unit 10 and the temperature sensing unit 20 are both in a snake-shaped structure, and the key dimensions of the metal platinum films are in the micrometer level. Specifically, as shown in fig. 3, the metal platinum thin films of the heat generating unit 10 and the temperature sensing unit 20 are entirely bent reciprocally in the left-right direction, so as to form a symmetrical serpentine structure with the symmetry axis along the left-right direction.
s3, manufacturing stress sensing unit 30
Manufacturing a stress sensing unit 30 on a lower insulating layer of an active heating area such as a chip and the like and a lower insulating layer of an inactive heating area such as a silicon cap, a silicon substrate and the like through a semiconductor process;
the stress sensing units 30 are made of films made of copper-nickel alloy or nickel-chromium alloy, the critical dimensions of the copper-nickel alloy or nickel-chromium alloy films are in the micrometer level, each stress sensing unit 30 comprises two perpendicular films, and the two films in each stress sensing unit 30 have the same structure and are all in a snake-shaped structure.
One of the two vertical films of each stress sensing unit 30 is located at the upper right side, and the other is located at the lower left side, and the two vertical films have the same structure, except that the upper right film is bent back and forth to form a snake shape with a symmetry axis along the left-right direction, and the lower left film is bent back and forth along the up-down direction to form a snake shape with a symmetry axis along the up-down direction.
In this embodiment, as shown in fig. 3 and 4, two types of test units, i.e., a type i test unit a and a type ii test unit B, are provided based on whether the components actively generate heat.
As shown in fig. 3, the class i test unit a includes a heat generating unit 10, a temperature sensing unit 20, and a stress sensing unit 30, and the array of class i test units a is distributed on a lower insulating layer of an active heat generating area such as a chip. Specifically, in the class i test unit a, the heat generating unit 10 and the temperature sensing unit 20 are located on the left side of the stress sensing unit 30, and the heat generating unit 10 is above the temperature sensing unit 20.
As shown in fig. 4, the class ii test unit B includes a temperature sensing unit 20 and a stress sensing unit 30, and the array of class ii test units B is distributed on the lower insulating layer of the non-active heating area such as the silicon cap and the silicon substrate. Specifically, in the class ii test unit B, the temperature sensing unit 20 is located below the upper right film and to the right of the lower left film.
In this embodiment, the array distribution modes of the class i test unit a and the class ii test unit B are rectangular arrays.
Specifically, as shown in fig. 2, the class i test unit a is located in active heating areas such as the second layer functional chip 5 and the first layer functional chip 7, and the class ii test unit B is located in non-active heating areas such as the second layer silicon cap 1, the second layer silicon substrate 2, the first layer silicon cap 3 and the first layer silicon substrate 4.
s4, manufacturing an upper insulating layer and a lead
Sequentially manufacturing a patterned upper insulating layer and a lead wire on the heating unit 10, the temperature sensing unit 20 and the stress sensing unit 30 through a semiconductor process;
and (3) heating calibration: and (3) calibrating the power consumption of the heating units 10 on the surfaces of active heating areas such as chips and the like under the thermal infrared imager, and correcting the power consumption of each heating unit to ensure that the main heating area and the actual chip have the same heating power consumption distribution.
Standard signal output: leading out the lead wires, respectively forming a Wheatstone bridge with external standard resistors through a multi-channel signal switching module, and carrying out signal amplification through a high-impedance amplification module to obtain standard signal output;
temperature sensing calibration: calibrating the temperature sensing unit 20 in a standard incubator to obtain the resistance temperature relation of the temperature sensing unit 20: r=r 0 (1+αT) wherein R 0 The resistance is at room temperature, T is the working temperature, and alpha is a constant coefficient;
stress sensing calibration: calibrating the stress sensing unit 30 at different temperatures by using a four-point bending method to obtain the resistance stress relation of the stress sensing unit 30: r=r 0 (1+ασ) (1+βT) wherein R 0 The resistance at room temperature is represented by T, the working temperature is represented by T, the stress is represented by sigma, the actual temperature values obtained by calculation are the temperature references of pressure calibration, and the root mean square value of the stress measured by two films vertically distributed in the same stress sensing unit 30 is the actual stress of the stress sensing unit 30;
s5, stacking interconnect
Stacking and interconnecting all components of the silicon substrate type transceiver component to form the silicon substrate type transceiver component, and leading out or leading in signal output and power input of the heating unit 10, the temperature sensing unit 20 and the stress sensing unit 30 through leads;
s6, stress test
The stacked and interconnected silicon substrate transceiver components are subjected to stress test in a room temperature natural state, so that residual stress of the assembled components is obtained;
s7, temperature and stress value output
And controlling the heating of the silicon substrate type transceiver component, and testing to obtain the output of the temperature sensing unit 20 and the stress sensing unit 30, thereby obtaining the temperature and the stress value of the working state of the component. Specifically, based on the simulated heat source array control strategy obtained in the step s4, the heating of the simulated assembly is controlled, the output of the temperature and stress array is obtained through testing, and the temperature and stress value of the working state of the assembly is obtained after calculation.
The method provided by the invention is based on the test unit array manufactured by the semiconductor film process, has small critical dimension and high integration level, breaks through the capability boundary of the existing test means, can be used for measuring the temperature and stress distribution of the component in real time and high precision based on the analog component, and can find out the structural stress singular point and the junction temperature of the critical functional chip, thereby providing a basis for the design of the component. The method replaces an actual assembly with an analog assembly manufactured based on the same structure, material and process, and an array of test units is manufactured on the surface of each layer of to-be-tested area of the vertically stacked assembly, wherein each test unit comprises a heating area, a temperature sensing area and a stress sensing area. The test unit array provided by the invention can play the roles of active heating, temperature and stress sensing simultaneously, is manufactured by adopting an all-metal film process based on a semiconductor process, can be integrated on various substrates such as silicon, gallium arsenide and the like, comprehensively simulates the power consumption, the structure and the materials of an actual assembly, and realizes the test and the integration of any region to be tested of each layer in the assembly. Meanwhile, the testing method performs calibration and compensation aiming at the temperature and stress sensing unit, and has high measurement precision, thereby realizing high-fidelity three-dimensional reproduction of the temperature and stress field.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for testing a temperature stress field of a silicon substrate type receiving and transmitting component is characterized by comprising the following steps of: the method comprises the following steps:
s1, manufacturing a lower insulating layer
Manufacturing a lower insulating layer in a substrate to-be-tested area of each component of the silicon substrate type transceiver component;
s2, manufacturing a heating unit (10) and a temperature sensing unit (20)
Manufacturing a heating unit (10) and a temperature sensing unit (20) on a lower insulating layer of an active heating area of a chip, and manufacturing the temperature sensing unit (20) on a lower insulating layer of a silicon cap and a silicon substrate without the active heating area;
s3, manufacturing stress sensing unit (30)
Manufacturing a stress sensing unit (30) on the lower insulating layer of the active heating area of the chip and the lower insulating layer of the non-active heating area of the silicon cap and the silicon substrate;
s4, manufacturing an upper insulating layer and a lead
Sequentially manufacturing an upper insulating layer and a lead on the heating unit (10), the temperature sensing unit (20) and the stress sensing unit (30);
s5, stacking interconnect
The method comprises the steps of stacking and interconnecting all components of a silicon substrate type transceiver component to form the silicon substrate type transceiver component, and leading out or leading in signal output and power input of a heating unit (10), a temperature sensing unit (20) and a stress sensing unit (30) through leads;
s6, stress test
The stacked and interconnected silicon substrate transceiver components are subjected to stress test in a room temperature natural state, so that residual stress of the assembled components is obtained;
s7, temperature and stress value output
Controlling the heating of the silicon substrate type receiving and transmitting component, and testing to obtain the output of the temperature sensing unit (20) and the stress sensing unit (30) to obtain the temperature and the stress value of the working state of the component;
the dimensions of the heating unit (10), the temperature sensing unit (20) and the stress sensing unit (30) are all in the order of micrometers.
2. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the method also comprises the following steps:
and (3) manufacturing parts: manufacturing components according to the same structure, materials and process as those of the components of the silicon substrate type transceiver component to be tested, wherein the manufactured components comprise a silicon cap, a silicon substrate and a chip;
the step of making the component is preceded by step s1.
3. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the substrate in the step s1 is made of silicon or gallium arsenide.
4. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the heating unit (10) and the temperature sensing unit (20) are made of metal platinum films, and the heating unit (10) and the temperature sensing unit (20) are of serpentine structures.
5. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the stress sensing units (30) are made of copper-nickel alloy or nickel-chromium alloy films, each stress sensing unit (30) comprises two perpendicular films, and the two films in each stress sensing unit (30) are identical in structure and are all in a serpentine structure.
6. The method for testing the temperature stress field of the silicon substrate transceiver component according to claim 5, wherein the method comprises the following steps: the method also comprises the following steps:
stress sensing calibration: calibrating the stress sensing unit (30) at different temperatures by using a four-point bending method to obtain the resistance stress relation of the stress sensing unit (30): r=r 0 (1+ασ) (1+βT) wherein R 0 The resistance at room temperature is represented by T, the working temperature is represented by T, the stress is represented by sigma, the actual temperature values obtained by calculation are the temperature references of pressure calibration, and the root mean square value of the stress measured by two films vertically distributed by the same stress sensing unit (30) is the actual stress of the stress sensing unit (30);
the stress sensing calibration step is performed between steps s4 and s 5.
7. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the method also comprises the following steps:
and (3) heating calibration: the heating of the heating unit (10) is calibrated under the thermal infrared imager, so that the heating unit is the same as the heating of an actual chip;
the heat calibration step is performed between steps s4 and s 5.
8. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the method also comprises the following steps:
standard signal output: leading out the lead wires, respectively forming a Wheatstone bridge with external standard resistors through a multi-channel signal switching module, and carrying out signal amplification through a high-impedance amplification module to obtain standard signal output;
the standard signal outputting step is performed between steps s4 and s 5.
9. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the method also comprises the following steps:
temperature sensing calibration: calibrating the temperature sensing unit (20) in a standard incubator to obtain the resistance temperature relation of the temperature sensing unit (20): r=r 0 (1+αT) wherein R 0 The resistance is at room temperature, T is the working temperature, and alpha is a constant coefficient;
the temperature sensing calibration step is performed between steps s4 and s 5.
10. The method for testing the temperature stress field of the silicon substrate type transceiver component according to claim 1, wherein the method comprises the following steps: the test system also comprises a class I test unit (A) and a class II test unit (B);
the I-type test unit (A) comprises a heating unit (10), a temperature sensing unit (20) and a stress sensing unit (30), and is distributed on a lower insulating layer of an active heating area of the chip in an array manner;
the II-type test unit (B) comprises a temperature sensing unit (20) and a stress sensing unit (30), and the II-type test unit (B) is distributed on the lower insulating layer of the silicon cap and the silicon substrate without the active heating area.
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