CN113555293A - Silicon substrate type receiving and dispatching assembly temperature stress field testing method - Google Patents
Silicon substrate type receiving and dispatching assembly temperature stress field testing method Download PDFInfo
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- CN113555293A CN113555293A CN202110826137.2A CN202110826137A CN113555293A CN 113555293 A CN113555293 A CN 113555293A CN 202110826137 A CN202110826137 A CN 202110826137A CN 113555293 A CN113555293 A CN 113555293A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
Abstract
The invention relates to the field of semiconductor testing, in particular to a method for testing a temperature stress field of a silicon substrate type transceiving component, which comprises the following steps: manufacturing a lower insulating layer, manufacturing a stress sensing unit, manufacturing an upper insulating layer and a lead, stacking interconnection, stress testing, and outputting temperature and stress values. The invention has the advantages that: compared with the prior art, the temperature inside the packaged or assembled component can be tested, the high-precision measurement of the stress field inside the component or on the surface of the component can be realized, and the precision of the stress distribution result is higher.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a method for testing a temperature stress field of a silicon substrate type transceiving component, which is specially used for testing the three-dimensional temperature and stress field of a large-size high-power vertically stacked silicon substrate type transceiving component.
Background
In the prior art, for example, a chinese patent with publication number CN111276475B discloses a three-dimensional heterogeneous integrated radio frequency front end microsystem, which adopts a stacked structure of multiple layers of silicon interposer, and multiple power reconfigurable transceiver chips are embedded in one or multiple layers of silicon interposer; the power management chip is embedded in a silicon adapter plate provided with a power reconfigurable transceiving chip; the ultra-wideband mixer chip and the radio frequency switch matrix chip are embedded in the same layer of silicon adapter plate; each adjustable filter chip is arranged between two layers of silicon adapter plates through integrated processing to form a sandwich structure, and the sandwich structure is arranged outside the layer where the ultra-wideband mixer chip is arranged or between the layer where the ultra-wideband mixer chip is arranged and the layer where the power management chip is arranged; each power reconfigurable transceiver chip is connected with the radio frequency switch matrix chip through an adjustable filter chip; the radio frequency switch matrix chip is connected with the ultra-wideband mixer chip; the power management chip is used for providing control signals and supplying power. The above patent describes a typical rf front-end microsystem in the prior art, which employs a stacked structure of multiple silicon interposer.
The receiving and transmitting assembly is an important component of a radar radio frequency front end, a silicon substrate type receiving and transmitting assembly with a vertical stacking structure is based on silicon substrate advanced packaging, has large assembly density and small volume, and can greatly improve the integration level of a radar whole machine, the typical structure of the receiving and transmitting assembly is shown in figure 1, and the receiving and transmitting assembly comprises a box body consisting of a single-layer or multi-layer silicon substrate and a silicon cap and a functional chip inside the box body, wherein the box body specifically comprises a second-layer silicon cap 1, a second-layer silicon substrate 2, a first-layer silicon cap 3, a first-layer silicon substrate 4, a second-layer functional chip 5, a second-layer solder ball 6, a first-layer functional chip 7, a first-layer solder ball 8 and an assembly substrate 9, the first-layer silicon substrate 4 is arranged above the assembly substrate 9, the first-layer silicon substrate 4 is connected with the assembly substrate 9 through the first-layer solder ball 8, the first-layer silicon cap 3 is arranged above the first-layer silicon substrate 4, and the first-layer functional chip 7 is arranged between the first-layer silicon cap 3, the second layer silicon substrate 2 is arranged above the first layer silicon cap 3, the first layer silicon cap 3 is connected with the second layer silicon substrate 2 through a second layer solder ball 6, the second layer silicon cap 1 is arranged above the second layer silicon substrate 2, and a second layer functional chip 5 is arranged between the second layer silicon substrate 2 and the second layer silicon cap 1.
The vertically stacked silicon-based chip transceiver module is generally large in area, more than 10mm x 10mm, integrates materials with different thermal expansion coefficients, such as silicon, gallium arsenide, gallium nitride, organic media, metal and the like, and is easy to generate thermal mismatch when assembled through processes, such as reflow soldering, thermal bonding and the like, or subjected to subsequent high-density assembly with other structures, such as a substrate and the like, so that large residual stress is formed, and the service life of the module is influenced. Considering that the chip transceiver module usually has high power and large thermal power consumption in a working state, whether the chip junction temperature inside the module is in a reasonable interval or not, and the service life of the module is also reduced by the unbalanced temperature distribution inside and outside and the thermal stress generated by different materials, which are key factors restricting the reliability of the system. Therefore, when the structure and the process of the component are optimally designed based on manufacturability and reliability, the three-dimensional temperature and stress distribution of the component in different states of different design schemes needs to be compared. The method for measuring the accurate real-time three-dimensional temperature and stress distribution is particularly important for designing a silicon substrate type transceiving component with a vertical stacking structure.
At present, a thermal imager can be used for monitoring the temperature distribution of a chip in real time, which is the most common temperature measurement means at present, but the method can only test the surface of the chip, and the inside of a packaged or assembled component cannot be measured. The conventional stress test is based on a resistance strain gauge, the strain gauge needs to be adhered to a surface to be tested through glue, then a signal is led out through a lead, the strain gauge is usually large, only one strain test unit can be distributed even in a 10mm square area, integration cannot be carried out inside a silicon substrate type transceiving component, and high-precision measurement of the internal or surface stress field of the component cannot be realized. The moire fringe method is a method for measuring the surface morphology based on optical interference with high precision, can measure a deformation cloud picture of an assembly in real time with higher precision, and calculates stress distribution by combining a finite element model.
Therefore, in order to optimally design the components based on temperature and stress distribution, it is necessary to develop a test method for vertically stacked components, and analyze three-dimensional distribution temperature and stress fields of the multi-layer stacked structure inside the components in an assembled or working state.
Based on the above-mentioned drawbacks, the inventor of the present invention has finally obtained the present invention through long-term research and practice.
Disclosure of Invention
The technical problem to be solved by the invention is as follows:
when a silicon substrate type transceiving component is tested in the prior art, the internal temperature of the packaged or assembled component cannot be tested, the high-precision measurement of the internal or surface stress field of the component cannot be realized, and the precision of a stress distribution calculation result is not high.
The invention solves the technical problems through the following technical means: a method for testing the temperature stress field of a silicon substrate type transceiving component comprises the following steps:
s1, making a lower insulating layer
Manufacturing a lower insulating layer in a substrate to-be-tested area of each component of the silicon-based chip type transceiving component;
s2 production of heating element and temperature sensing element
Manufacturing a heating unit and a temperature sensing unit on a lower insulating layer of an active heating area such as a chip, and manufacturing a temperature sensing unit on a lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate;
s3 manufacturing stress sensing unit
Manufacturing stress sensing units on lower insulating layers of active heating areas such as chips and the like and lower insulating layers of non-active heating areas such as silicon caps, silicon substrates and the like;
s4 fabrication of upper insulating layer and lead wire
Sequentially manufacturing an upper insulating layer and a lead on the heating unit, the temperature sensing unit and the stress sensing unit;
s5 Stack interconnect
Stacking and interconnecting all the components of the silicon-based chip type transceiving component to form the silicon-based chip type transceiving component, and leading out or leading in the signal output and power input of the heating unit, the temperature sensing unit and the stress sensing unit by lead wires;
s6 stress test
Stress testing is carried out on the silicon substrate type receiving and transmitting assemblies after being stacked and interconnected at a room temperature natural state, and residual stress of the assembled assemblies is obtained;
s7, temperature and stress value output
And controlling the heating of the silicon substrate type transceiving component, and testing to obtain the output of the temperature sensing unit and the stress sensing unit to obtain the temperature and the stress value of the working state of the component.
According to the silicon substrate type transceiving component temperature stress field testing method, the heating unit, the temperature sensing unit, the stress sensing unit and the like are small in key size and high in integration level, the capability boundary of the existing testing means is broken through, the temperature and stress distribution of the component in the working state can be measured in real time and at high precision based on the simulation component, the structural stress singularity and the junction temperature of a chip with a key function can be found out, and a basis is provided for component design. The method is used for manufacturing a heating unit, a temperature sensing unit, a stress sensing unit and the like on the surface of each layer of to-be-tested area of the vertical stacking assembly. And then can play the effect of initiative heating, temperature and stress sensing simultaneously to can integrate heating element, temperature sensing unit and stress sensing unit etc. on various substrates, realize the test and the integration of each layer arbitrary region of awaiting measuring in the subassembly. Compared with the prior art, the temperature inside the packaged or assembled component can be tested, the high-precision measurement of the stress field inside the component or on the surface of the component can be realized, and the precision of the stress distribution result is higher.
The optimization method further comprises the following steps:
manufacturing a component: manufacturing components according to the same structure, materials and process as those of the silicon substrate type transceiving component to be tested, wherein the manufactured components comprise a silicon cap, a silicon substrate and a chip;
the step of fabricating the part precedes step s 1.
The method replaces an actual assembly with a simulation assembly manufactured based on the same structure, material and process, comprehensively simulates the power consumption, structure and material of the actual assembly, and realizes the test and integration of any to-be-tested area of each layer in the assembly. The temperature and stress distribution of the simulation assembly in a working state can be measured in real time and at high precision, structural stress singular points and junction temperature of a chip with a key function can be found out, and a basis is provided for assembly design.
Preferably, the substrate in step s1 is made of silicon or gallium arsenide.
Preferably, the heating unit and the temperature sensing unit are made of metal platinum films and are of serpentine structures.
Preferably, the stress sensing units are made of films made of copper-nickel alloy or nickel-chromium alloy, each stress sensing unit comprises two vertical films, and the two films in each stress sensing unit have the same structure and are of snake-shaped structures.
The heating unit, the temperature sensing unit and the stress sensing unit manufactured based on the semiconductor film process have small critical dimension and high integration level, and are convenient for realizing high-precision measurement of the temperature stress field inside or on the surface of the component.
The two vertical films of each stress sensing unit, namely the two snake-shaped resistors which are distributed in an orthogonal mode, can respectively measure the horizontal stress of the corresponding two orthogonal directions, so that the actual stress of the area to be tested is reflected, and the test result is accurate.
The optimization method further comprises the following steps:
stress sensing calibration: calibrating the stress sensing unit at different temperatures by using a four-point bending method to obtain the resistance stress relation of the stress sensing unit: r ═ R0(1+ α σ) (1+ β T), wherein R0The resistance at room temperature, T is the working temperature, sigma is the stress, alpha and beta are constant coefficients, the calculated actual temperature value is the temperature reference of pressure calibration, and the root mean square value of the stress measured by two vertically distributed films of the same stress sensing unit is the actual stress of the stress sensing unit;
the stress sensing calibration step is performed between steps s4 and s 5.
The stress sensing unit is calibrated and compensated, and the measurement precision is high, so that high-fidelity three-dimensional reproduction of a stress field can be realized.
The optimization method further comprises the following steps:
heating calibration: calibrating the heating of the heating unit under the thermal infrared imager to ensure that the heating is the same as the heating of an actual chip;
the heating calibration step is performed between steps s4 and s 5.
The heating calibration can ensure that the heating condition of the heating unit is the same as the heating condition of the chip in actual use as far as possible, so that the heating condition of the actual chip is accurately simulated, and actual parameters are better fed back.
The optimization method further comprises the following steps:
outputting a standard signal: leading out the lead wires, forming a Wheatstone bridge with an external standard resistor through a multi-channel signal switching module, and amplifying signals through a high-impedance amplifying module to obtain a standard signal output;
the standard signal output step is performed between steps s4 and s 5.
The optimization method further comprises the following steps:
temperature sensing calibration: calibrating the temperature sensing unit in a standard incubator to obtain a temperature sensing listResistance temperature relationship of the cell: r ═ R0(1+ α T), wherein R0The resistance at room temperature, T the working temperature and alpha the constant coefficient;
the temperature sensing calibration step is performed between steps s4 and s 5.
The temperature sensing unit is calibrated and compensated, and the measurement precision is high, so that high-fidelity three-dimensional reproduction of a temperature field can be realized.
The optimized test device also comprises a type I test unit and a type II test unit;
the I-type test unit comprises a heating unit, a temperature sensing unit and a stress sensing unit, and is distributed on the lower insulating layer of an active heating area such as a chip in an array manner;
the II-type test units comprise temperature sensing units and stress sensing units, and are distributed on the lower insulating layers of the silicon cap, the silicon substrate and other regions without active heating in an array mode.
The chip and other active heating areas can generate heat in actual work, so that a heating unit, a temperature sensing unit and a stress sensing unit are required to be arranged at the same time, and the silicon cap, the silicon substrate and other non-active heating areas do not generate heat in actual work, so that the temperature sensing unit and the stress sensing unit are only required to be arranged, and the defined I-type test unit array is distributed on the lower insulating layer of the chip and other active heating areas; the II-type test unit arrays are distributed on the lower insulating layer of the silicon cap, the silicon substrate and other areas without active heating, so that the comprehensive coverage of the area to be tested is realized, and the three-dimensional reproduction of the temperature and stress field is realized.
The invention has the advantages that:
1. according to the silicon substrate type transceiving component temperature stress field testing method, the heating unit, the temperature sensing unit, the stress sensing unit and the like are small in key size and high in integration level, the capability boundary of the existing testing means is broken through, the temperature and stress distribution of the component in the working state can be measured in real time and at high precision based on the simulation component, the structural stress singularity and the junction temperature of a chip with a key function can be found out, and a basis is provided for component design. The method is used for manufacturing a heating unit, a temperature sensing unit, a stress sensing unit and the like on the surface of each layer of to-be-tested area of the vertical stacking assembly. And then can play the effect of initiative heating, temperature and stress sensing simultaneously to can integrate heating element, temperature sensing unit and stress sensing unit etc. on various substrates, realize the test and the integration of each layer arbitrary region of awaiting measuring in the subassembly. Compared with the prior art, the temperature inside the packaged or assembled component can be tested, the high-precision measurement of the stress field inside the component or on the surface of the component can be realized, and the precision of the stress distribution result is higher.
2. The method replaces an actual assembly with a simulation assembly manufactured based on the same structure, material and process, comprehensively simulates the power consumption, structure and material of the actual assembly, and realizes the test and integration of any to-be-tested area of each layer in the assembly. The temperature and stress distribution of the simulation assembly in a working state can be measured in real time and at high precision, structural stress singular points and junction temperature of a chip with a key function can be found out, and a basis is provided for assembly design.
3. The heating unit, the temperature sensing unit and the stress sensing unit manufactured based on the semiconductor film process have small critical dimension and high integration level, and are convenient for realizing high-precision measurement of the temperature stress field inside or on the surface of the component. The two vertical films of each stress sensing unit, namely the two snake-shaped resistors which are distributed in an orthogonal mode, can respectively measure the horizontal stress of the corresponding two orthogonal directions, so that the actual stress of the area to be tested is reflected, and the test result is accurate.
4. The stress sensing unit is calibrated and compensated, and the measurement precision is high, so that high-fidelity three-dimensional reproduction of a stress field can be realized.
5. The heating calibration can ensure that the heating condition of the heating unit is the same as the heating condition of the chip in actual use as far as possible, so that the heating condition of the actual chip is accurately simulated, and actual parameters are better fed back.
The temperature sensing unit is calibrated and compensated, and the measurement precision is high, so that high-fidelity three-dimensional reproduction of a temperature field can be realized.
6. The chip and other active heating areas can generate heat in actual work, so that a heating unit, a temperature sensing unit and a stress sensing unit are required to be arranged at the same time, and the silicon cap, the silicon substrate and other non-active heating areas do not generate heat in actual work, so that the temperature sensing unit and the stress sensing unit are only required to be arranged, and the defined I-type test unit array is distributed on the lower insulating layer of the chip and other active heating areas; the II-type test unit arrays are distributed on the lower insulating layer of the silicon cap, the silicon substrate and other areas without active heating, so that the comprehensive coverage of the area to be tested is realized, and the three-dimensional reproduction of the temperature and stress field is realized.
Drawings
FIG. 1 is a schematic diagram of a prior art silicon-based chip transceiver module;
FIG. 2 is a schematic diagram of a temperature stress field test of a silicon substrate type transceiver module according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a class I test unit in an embodiment of the present invention;
FIG. 4 is a schematic diagram of a class II test unit in an embodiment of the present invention;
wherein the content of the first and second substances,
a second layer of silicon cap-1, a second layer of silicon substrate-2, a first layer of silicon cap-3, a first layer of silicon substrate-4, a second layer of functional chip-5, a second layer of solder balls-6, a first layer of functional chip-7, a first layer of solder balls-8 and an assembly substrate-9;
a heating unit-10, a temperature sensing unit-20 and a stress sensing unit-30;
class I test unit-A, class II test unit-B.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the embodiments of the present invention, and it is obvious that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A method for testing the temperature stress field of a silicon substrate type transceiving component comprises the following steps:
manufacturing a component: and manufacturing components according to the same structure, material and process as those of the silicon substrate type transceiving component to be tested, wherein the manufactured components comprise a silicon cap, a silicon substrate and a chip. That is, the silicon cap, silicon substrate and chip of each layer are fabricated based on the same structure, materials and processes as the vertically stacked silicon substrate type transceiver component, including possible surface interconnect layers and vertical interconnect layers.
After the step of fabricating the part is completed, step s1 is performed.
s1, making a lower insulating layer
Manufacturing a lower insulating layer in a substrate to-be-tested area of each component of the silicon-based chip type transceiving component; the substrate is made of silicon or gallium arsenide, including but not limited to silicon, gallium arsenide, and the like. Specifically, a lower insulating layer is manufactured in a to-be-tested area of a substrate through semiconductor film processes such as magnetron sputtering, chemical vapor deposition, electron beam evaporation and the like, and the subsequent snake-shaped structures of the heating unit 10, the temperature sensing unit 20, the stress sensing unit 30 and the like are insulated and isolated from the substrate through the lower insulating layer.
s2 production of heating element 10 and temperature sensing element 20
Manufacturing a heating unit 10 and a temperature sensing unit 20 on a lower insulating layer of an active heating area such as a chip through a semiconductor process, and manufacturing the temperature sensing unit 20 on the lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate;
the heating unit 10 and the temperature sensing unit 20 are made of metal platinum films, the heating unit 10 and the temperature sensing unit 20 are of snake-shaped structures, and the key sizes of the metal platinum films are in the micrometer level. Specifically, as shown in fig. 3, the entire platinum films of the heat generating unit 10 and the temperature sensing unit 20 are bent back and forth in the left-right direction, and further, a serpentine structure having a symmetrical axis in the left-right direction is formed.
s3 manufacturing stress sensing unit 30
Manufacturing a stress sensing unit 30 on a lower insulating layer of an active heating area such as a chip and the like and on a lower insulating layer of a non-active heating area such as a silicon cap, a silicon substrate and the like by a semiconductor process;
the stress sensing units 30 are made of copper-nickel alloy or nickel-chromium alloy films, the critical dimensions of the copper-nickel alloy or nickel-chromium alloy films are in the micron order, each stress sensing unit 30 comprises two vertical films, and the two films in each stress sensing unit 30 are identical in structure and are of a snake-shaped structure.
One of the two vertical thin films of each stress sensing unit 30 is located at the upper right side, and the other is located at the lower left side, which have the same structure, but are different in that the upper right thin film is bent back and forth to form a serpentine shape having a symmetry axis along the left-right direction, and the lower left thin film is bent back and forth along the up-down direction to form a serpentine shape having a symmetry axis along the up-down direction.
As shown in fig. 3 and 4, in this embodiment, two types of test units, i.e., a type i test unit a and a type ii test unit B, are provided based on whether the component actively generates heat.
As shown in fig. 3, the class i test unit a includes a heating unit 10, a temperature sensing unit 20, and a stress sensing unit 30, and the class i test unit a is distributed in an array on a lower insulating layer of an active heating area such as a chip. Specifically, in the type i test unit a, the heating unit 10 and the temperature sensing unit 20 are located on the left side of the stress sensing unit 30, and the heating unit 10 is located above the temperature sensing unit 20.
As shown in fig. 4, the class ii test unit B includes a temperature sensing unit 20 and a stress sensing unit 30, and the class ii test unit B is distributed in an array on the lower insulating layer of the silicon cap, the silicon substrate and other regions without active heat generation. Specifically, in the class ii test unit B, the temperature sensing unit 20 is located below the upper right film and to the right of the lower left film.
In this embodiment, the array distribution modes of the type i test unit a and the type ii test unit B are both rectangular arrays.
Specifically, as shown in fig. 2, the type i test unit a is located in an active heating area such as the second layer functional chip 5 and the first layer functional chip 7, and the type ii test unit B is located in an inactive heating area such as the second layer silicon cap 1, the second layer silicon substrate 2, the first layer silicon cap 3, and the first layer silicon substrate 4.
s4 fabrication of upper insulating layer and lead wire
Sequentially manufacturing a patterned upper insulating layer and a lead on the heating unit 10, the temperature sensing unit 20 and the stress sensing unit 30 through a semiconductor process;
heating calibration: the power consumption of the heating units 10 on the surfaces of the active heating areas such as the chips is calibrated under the thermal infrared imager, and the power consumption of each heating unit is corrected, so that the heating power consumption distribution of the main heating area is the same as that of the actual chip.
Outputting a standard signal: leading out the lead wires, forming a Wheatstone bridge with an external standard resistor through a multi-channel signal switching module, and amplifying signals through a high-impedance amplifying module to obtain a standard signal output;
temperature sensing calibration: calibrating the temperature sensing unit 20 in a standard incubator to obtain the resistance-temperature relationship of the temperature sensing unit 20: r ═ R0(1+ α T), wherein R0The resistance at room temperature, T the working temperature and alpha the constant coefficient;
stress sensing calibration: calibrating the stress sensing unit 30 at different temperatures by using a four-point bending method to obtain a resistance stress relation of the stress sensing unit 30: r ═ R0(1+ α σ) (1+ β T), wherein R0The resistance at room temperature, T is the working temperature, σ is the stress, α, β are the constant coefficients, the calculated actual temperature value is the temperature reference for pressure calibration, and the root mean square value of the stress measured by two vertically distributed films of the same stress sensing unit 30 is the actual stress of the stress sensing unit 30;
s5 Stack interconnect
Stacking and interconnecting all the components of the silicon-based chip type transceiving component to form the silicon-based chip type transceiving component, and leading out or leading in the signal output and power input of the heating unit 10, the temperature sensing unit 20 and the stress sensing unit 30 by leads;
s6 stress test
Stress testing is carried out on the silicon substrate type receiving and transmitting assemblies after being stacked and interconnected at a room temperature natural state, and residual stress of the assembled assemblies is obtained;
s7, temperature and stress value output
And controlling the heating of the silicon substrate type transceiving component, and testing to obtain the output of the temperature sensing unit 20 and the stress sensing unit 30 to obtain the temperature and the stress value of the working state of the component. Specifically, the heating of the simulation component is controlled based on the simulation heat source array control strategy obtained in the step s4, the output of the temperature and stress array is obtained through testing, and the temperature and stress value of the working state of the component is obtained through calculation.
The method provided by the invention is based on the test unit array manufactured by the semiconductor thin film process, has small critical dimension and high integration level, breaks through the capability boundary of the existing test means, can measure the temperature and stress distribution of the assembly in a working state at high precision in real time based on the simulation assembly, finds out the structural stress singular point and the junction temperature of the chip with the critical function, and provides a basis for the assembly design. The method uses a simulation component manufactured based on the same structure, material and process to replace an actual component, and a test unit array is manufactured on the surface of each layer of to-be-tested area of the vertical stacking component, wherein each test unit comprises a heating area, a temperature sensing area and a stress sensing area. The test unit array provided by the invention can play a role in active heating, temperature and stress sensing at the same time, is manufactured by adopting an all-metal film process based on a semiconductor process, can be integrated on various substrates such as silicon, gallium arsenide and the like, comprehensively simulates the power consumption, the structure and the material of an actual assembly, and realizes the test and integration of any region to be tested in each layer of the assembly. Meanwhile, the test method is calibrated and compensated aiming at the temperature and stress sensing units, and the measurement precision is high, so that high-fidelity three-dimensional reproduction of the temperature and stress fields is realized.
The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A silicon substrate type receiving and dispatching component temperature stress field test method is characterized in that: the method comprises the following steps:
s1, making a lower insulating layer
Manufacturing a lower insulating layer in a substrate to-be-tested area of each component of the silicon-based chip type transceiving component;
s2 manufacturing heating unit (10) and temperature sensing unit (20)
Manufacturing a heating unit (10) and a temperature sensing unit (20) on a lower insulating layer of an active heating area such as a chip, and manufacturing the temperature sensing unit (20) on the lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate;
s3 fabrication of stress sensing cell (30)
Manufacturing a stress sensing unit (30) on a lower insulating layer of an active heating area such as a chip and the like and on a lower insulating layer of a non-active heating area such as a silicon cap and a silicon substrate;
s4 fabrication of upper insulating layer and lead wire
Sequentially manufacturing an upper insulating layer and a lead on the heating unit (10), the temperature sensing unit (20) and the stress sensing unit (30);
s5 Stack interconnect
Stacking and interconnecting all parts of the silicon-based chip type transceiving assembly to form the silicon-based chip type transceiving assembly, and leading out or leading in signal output and power input of the heating unit (10), the temperature sensing unit (20) and the stress sensing unit (30) through lead wires;
s6 stress test
Stress testing is carried out on the silicon substrate type receiving and transmitting assemblies after being stacked and interconnected at a room temperature natural state, and residual stress of the assembled assemblies is obtained;
s7, temperature and stress value output
And controlling the heating of the silicon substrate type transceiving component, and testing to obtain the output of the temperature sensing unit (20) and the stress sensing unit (30) so as to obtain the temperature and the stress value of the working state of the component.
2. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: also comprises the following steps:
manufacturing a component: manufacturing components according to the same structure, materials and process as those of the silicon substrate type transceiving component to be tested, wherein the manufactured components comprise a silicon cap, a silicon substrate and a chip;
the step of fabricating the part precedes step s 1.
3. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: the substrate in step s1 is made of silicon or gallium arsenide.
4. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: the heating unit (10) and the temperature sensing unit (20) are made of metal platinum films, and the heating unit (10) and the temperature sensing unit (20) are of snake-shaped structures.
5. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: the stress sensing units (30) are made of films made of copper-nickel alloy or nickel-chromium alloy, each stress sensing unit (30) comprises two vertical films, and the two films in each stress sensing unit (30) are identical in structure and are of a snake-shaped structure.
6. The method for testing the temperature stress field of the silicon substrate type transceiver module as claimed in claim 5, wherein: also comprises the following steps:
stress sensing calibration: calibrating the stress sensing unit (30) at different temperatures by using a four-point bending method to obtain the resistance stress relation of the stress sensing unit (30): r ═ R0(1+ α σ) (1+ β T), wherein R0The resistance at room temperature, T is the working temperature, sigma is the stress, alpha and beta are constant coefficients, the calculated actual temperature value is the temperature reference of pressure calibration, and the root mean square value of the stress measured by two vertically distributed films of the same stress sensing unit (30) is the actual stress of the stress sensing unit (30);
the stress sensing calibration step is performed between steps s4 and s 5.
7. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: also comprises the following steps:
heating calibration: calibrating the heating of the heating unit (10) under the thermal infrared imager to ensure that the heating is the same as the heating of an actual chip;
the heating calibration step is performed between steps s4 and s 5.
8. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: also comprises the following steps:
outputting a standard signal: leading out the lead wires, forming a Wheatstone bridge with an external standard resistor through a multi-channel signal switching module, and amplifying signals through a high-impedance amplifying module to obtain a standard signal output;
the standard signal output step is performed between steps s4 and s 5.
9. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: also comprises the following steps:
temperature sensing calibration: calibrating the temperature sensing unit (20) in a standard incubator to obtain the resistance temperature relation of the temperature sensing unit (20): r ═ R0(1+ α T), wherein R0The resistance at room temperature, T the working temperature and alpha the constant coefficient;
the temperature sensing calibration step is performed between steps s4 and s 5.
10. The method for testing the temperature stress field of the silicon substrate type transceiver module according to claim 1, wherein: the test device also comprises a type I test unit (A) and a type II test unit (B);
the I-type test unit (A) comprises a heating unit (10), a temperature sensing unit (20) and a stress sensing unit (30), and is distributed on the lower insulating layer of an active heating area such as a chip in an array manner;
the II-type test unit (B) comprises a temperature sensing unit (20) and a stress sensing unit (30), and is distributed on the lower insulating layer of the silicon cap, the silicon substrate and other regions without active heating in an array manner.
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