CN113555287B - Preparation method of moisture triggered degradation P-type transient thin film transistor - Google Patents
Preparation method of moisture triggered degradation P-type transient thin film transistor Download PDFInfo
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- 239000010409 thin film Substances 0.000 title claims abstract description 39
- 230000001960 triggered effect Effects 0.000 title claims abstract description 34
- 238000002360 preparation method Methods 0.000 title claims abstract description 33
- 230000015556 catabolic process Effects 0.000 title claims abstract description 32
- 238000006731 degradation reaction Methods 0.000 title claims abstract description 32
- 230000001052 transient effect Effects 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 140
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 claims abstract description 92
- 239000010410 layer Substances 0.000 claims abstract description 91
- 238000000151 deposition Methods 0.000 claims abstract description 83
- 108010022355 Fibroins Proteins 0.000 claims abstract description 62
- 239000000463 material Substances 0.000 claims abstract description 57
- 239000011241 protective layer Substances 0.000 claims abstract description 52
- 238000000137 annealing Methods 0.000 claims abstract description 38
- 239000007772 electrode material Substances 0.000 claims abstract description 32
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims abstract description 26
- 238000005566 electron beam evaporation Methods 0.000 claims abstract description 17
- 238000001035 drying Methods 0.000 claims abstract description 15
- 239000007864 aqueous solution Substances 0.000 claims abstract description 14
- 239000011248 coating agent Substances 0.000 claims abstract description 11
- 238000000576 coating method Methods 0.000 claims abstract description 11
- 238000001704 evaporation Methods 0.000 claims abstract description 4
- 230000008021 deposition Effects 0.000 claims description 68
- 239000010408 film Substances 0.000 claims description 67
- 238000000034 method Methods 0.000 claims description 31
- 238000004544 sputter deposition Methods 0.000 claims description 31
- 229910052681 coesite Inorganic materials 0.000 claims description 22
- 229910052906 cristobalite Inorganic materials 0.000 claims description 22
- 239000000377 silicon dioxide Substances 0.000 claims description 22
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052682 stishovite Inorganic materials 0.000 claims description 22
- 229910052905 tridymite Inorganic materials 0.000 claims description 22
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 20
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 15
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 12
- 238000002207 thermal evaporation Methods 0.000 claims description 10
- 229910052751 metal Inorganic materials 0.000 claims description 7
- 239000002184 metal Substances 0.000 claims description 7
- 108090000623 proteins and genes Proteins 0.000 description 40
- 102000004169 proteins and genes Human genes 0.000 description 40
- 239000000243 solution Substances 0.000 description 30
- 230000008569 process Effects 0.000 description 21
- 239000004065 semiconductor Substances 0.000 description 17
- 238000010586 diagram Methods 0.000 description 10
- 239000002904 solvent Substances 0.000 description 10
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 7
- 230000000052 comparative effect Effects 0.000 description 7
- 238000005546 reactive sputtering Methods 0.000 description 7
- 230000009471 action Effects 0.000 description 6
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 239000002253 acid Substances 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 5
- 239000008367 deionised water Substances 0.000 description 5
- 229910021641 deionized water Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000003513 alkali Substances 0.000 description 3
- 239000002585 base Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000003960 organic solvent Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 208000035965 Postoperative Complications Diseases 0.000 description 1
- 238000007605 air drying Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000006065 biodegradation reaction Methods 0.000 description 1
- 210000001124 body fluid Anatomy 0.000 description 1
- 239000010839 body fluid Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229920006237 degradable polymer Polymers 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000002346 layers by function Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 239000012460 protein solution Substances 0.000 description 1
- 230000000638 stimulation Effects 0.000 description 1
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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Abstract
The invention discloses a preparation method of a moisture-triggered degradation P-type transient transistor, which comprises the following steps: depositing an insulating layer on the polished side of the iron foil substrate to obtain a first sample; depositing an active layer material on the first sample to obtain a second sample; depositing a source-drain electrode material on the second sample to obtain a third sample, and annealing the third sample to obtain a fourth sample; coating a silk fibroin aqueous solution with the concentration of 6% on the surface of a fourth sample, and drying to obtain a fifth sample; covering a protective layer mask plate on the unpolished substrate of the fifth sample, and depositing a protective layer material to obtain a sixth sample; fixing the sixth sample in a clamp, and immersing the sixth sample in dilute hydrochloric acid to dissolve the iron foil substrate in the sixth sample to obtain a seventh sample; and placing the seventh sample in electron beam evaporation equipment, and evaporating a gate electrode to obtain the p-type thin film transistor triggered and degraded by moisture. Can overcome the limitation of the heat resistance of the substrate material on the preparation temperature of the device.
Description
Technical Field
The invention relates to a preparation method of a moisture-triggered degradation P-type transient thin film transistor.
Background
The traditional silicon-based electronic device has the advantages of firmness and durability, but any object has two sides, and the application of the traditional silicon-based electronic device in some special fields is limited due to the fact that the traditional silicon-based electronic device is too firm, for example, in the medical field, after the traditional silicon-based electronic device is implanted into a human body and a treatment or monitoring task is completed, a secondary operation is needed to take out the device, healed tissues are damaged, great pain is brought to a patient, and the risk of postoperative complications is increased; in the military field, once the traditional device falls into an enemy, the traditional device is easy to crack, and the secret is leaked. The problems can be well solved by a degradable transient electronic device in recent years, the transient electronic device is generally composed of a degradable substrate material, a semiconductor functional material and an electrode material, and after the prepared electronic functional device completes a specified function, the physical form and the function of the transient electronic device can completely or partially disappear under the triggering of external stimulation, so that the novel electronic device has a very wide application prospect in the aspects of biomedical treatment, information safety, environmental protection and the like. The transient device degradation is triggered by moisture triggering, thermal triggering, light triggering, acid/base triggering, biodegradation and the like. Among them, transient electronic devices triggered by moisture have unique advantages in the field of implantable degradable medical electronic devices because they can be dissolved in human body fluids.
The variety of electronic devices is large, transistors are one of the most important core devices, and some researchers have fabricated transient transistor devices on degradable polymer substrates or protein substrates. Although successful, it remains challenging to fabricate electronic devices on protein substrates, first, protein substrates are generally less heat resistant and generally have a decomposition temperature not exceeding 200 ℃, and for the growth of semiconductor materials, higher temperatures are beneficial to improve the crystalline quality of the material, reduce defects, and thus improve device performance. Due to the limitation of the heat resistance of the substrate material, the temperature of the preparation process of the degradable transient device is lower than the decomposition temperature of the substrate material, which seriously affects the performance of the semiconductor device. Secondly, the protein substrate has poor acid/alkali resistance and organic solvent resistance, and the semiconductor device is usually processed by acid/alkali, organic solvent or plasma in the preparation process, and the harsh processing conditions can damage the protein substrate and then the semiconductor device. Therefore, the manufacturing process conditions of semiconductor devices need to be compromised to the heat resistance and acid/alkali resistance of protein substrates. Part of material systems can achieve better performance at lower preparation temperature, such as n-type AZO-TFT, TZO-TFT, AZTO-TFT and the like, but some materials still need high-temperature process to achieve ideal performance, such as p-type oxide, wherein SnO-TFT needs annealing at 200-300 ℃, Cu-TFT needs annealing at the temperature of CuxThe O-TFT needs to be annealed at 500 ℃. Therefore, the poor heat resistance of the degradable substrate material severely limits the applications of semiconductor materials and devices requiring high temperature processes in the field of degradable devices. Furthermore, for transient devices with moisture-triggered degradation, how to protect the water-soluble protein substrate from acid/base and solvent exposure during device fabrication is another problematic issue。
Disclosure of Invention
The invention designs and develops a preparation method of a moisture-triggered degradation P-type transient thin film transistor, which prepares a transistor device on an iron foil substrate with a polished single surface, overcomes the limitation of the heat resistance of a substrate material on the preparation temperature of the device, is beneficial to improving the performance of the device, and also avoids the damage of aqueous solution on a water-soluble protein substrate in the preparation process of the device.
The technical scheme provided by the invention is as follows:
a preparation method of a moisture triggered degradation P-type transient thin film transistor comprises the following steps:
placing a single-side polished iron foil substrate in plasma enhanced chemical vapor deposition equipment, and performing insulating layer deposition on the polished side of the iron foil substrate to obtain a first sample;
covering the active layer template on the first sample, and depositing an active layer material in a radio frequency magnetron sputtering device to obtain a second sample;
covering a source-drain electrode mask plate on the second sample, placing the second sample in a thermal evaporation table for source-drain electrode material deposition to obtain a third sample, and placing the third sample in a rapid annealing furnace for annealing to obtain a fourth sample;
step four, coating the silk fibroin aqueous solution with the concentration of 6% on the surface of a fourth sample, and drying to obtain a fifth sample;
covering a protective layer mask plate on the unpolished substrate of the fifth sample, and depositing a protective layer material in radio frequency magnetron sputtering equipment to obtain a sixth sample;
fixing the sixth sample in a clamp, and immersing the sixth sample in dilute hydrochloric acid to dissolve the iron foil substrate in the sixth sample to obtain a seventh sample;
wherein the polished side of the iron foil substrate in the sixth sample is directed to the lower plate of the jig, and the unpolished side is directed to the upper plate of the jig;
and step seven, placing the seventh sample in electron beam evaporation equipment, and evaporating a gate electrode to obtain the p-type thin film transistor triggered and degraded by moisture.
Preferably, the first step includes:
deposition of SiO on the polished side of an iron foil substrate2An insulating layer material;
wherein the RF power is 50-100W, the deposition temperature is 150-250 deg.C, the pressure is 0.2-0.6 torr, SiH4The flow rate is 20-40 sccm, N2The flow rate of O is 80-150 sccm and SiO2The thickness of the film is 150 to 250 nm.
Preferably, the second step includes:
the active layer material is SnO, and the deposition of the active layer material is carried out by adopting a metal Sn target;
wherein the sputtering power is 25-35W, the temperature is room temperature, the pressure is 5-7 mtorr, Ar/O2The deposition time is 9: 1-2: 1, the deposition time is 10-20 min, and the film thickness is 45-70 nm.
Preferably, the third step includes:
the electrode material is Au, and the thickness is 50-100 nm;
the distance between the adjacent source and drain electrodes is 10 mu m-1 mm;
the annealing temperature is 250-350 ℃, and the annealing time is 25-40 min.
Preferably, the fourth step includes:
the protective layer is made of HfO2The sputtering power is 100-250W, the temperature is 25-200 ℃, the pressure is 8-20 mtorr, Ar/O29: 1-2: 1, deposition time of 50-150 min, and film thickness of 50-200 nm.
Preferably, the sixth step includes:
the clamp comprises an upper clamp plate and a lower clamp plate, the upper clamp plate and the lower clamp plate are both rectangular, a rectangular groove is formed in the center of the lower clamp plate, and a through hole is formed in the center of the upper clamp plate;
the concentration of the dilute hydrochloric acid is as follows: 1-30 wt%.
Preferably, the seventh step includes:
the electrode material is Al, and the thickness of the electrode is 50-200 nm.
It is preferable that the first and second liquid crystal layers are formed of,
in the first step, the radio frequency power is 50W, the deposition temperature is 200 ℃, the pressure is 0.2torr, and SiH is adopted4The flow rate was 20sccm, N2O flow rate of 80sccm, SiO2The thickness of the film is 150 nm;
in the second step, the sputtering power is 25W, the temperature is room temperature, the pressure is 5mtorr, Ar/O2The deposition time is 10min, and the film thickness is 45nm at 9: 1;
in the third step, the electrode material is Au, and the thickness is 50 nm;
the distance between adjacent source and drain electrodes is: 10 mu m;
the annealing temperature is as follows: annealing at 250 deg.C for 25 min;
in the fourth step, the sputtering power is as follows: 100W, 25 ℃ and 8mtorr Ar/O pressure2Is that 2:1, depositing for 50min, wherein the thickness of the film is 50 nm;
in the sixth step, the concentration of the dilute hydrochloric acid is as follows: 1 wt%;
in the seventh step, the thickness of the electrode is 50 nm.
The invention has the following beneficial effects:
the invention provides a method for preparing a p-type transient thin film transistor with moisture triggered degradation, which comprises the steps of firstly preparing a semiconductor device on a single-side polished iron foil substrate with good heat resistance, then dripping a solution of a degradable substrate material on the device, exposing the unpolished side of an iron foil to a dilute hydrochloric acid solution after a solvent is evaporated, dissolving the iron foil, effectively preventing the damage of the hydrochloric acid solution to a protein substrate due to the isolation effect of an insulating layer, finally preparing a gate electrode to obtain the p-type transient thin film transistor device with the moisture triggered degradation, preparing a device needing a high-temperature treatment process on the substrate with poor heat resistance, overcoming the limitation of the heat resistance of the substrate material on the preparation temperature of the device, being beneficial to improving the performance of the device, simultaneously avoiding the damage of the water-soluble protein substrate by the aqueous solution in the preparation process of the device, and preparing the p-type transient thin film transistor with the moisture triggered degradation, Transient electronic devices that require high temperature processing are possible.
Drawings
FIG. 1 is a schematic diagram of a structure of the insulating layer deposition according to the present invention.
Fig. 2 is a schematic structural diagram of an active layer mask plate according to the present invention.
Fig. 3 is a schematic structural diagram of the deposition of an active layer according to the present invention.
Fig. 4 is a schematic structural diagram of a source-drain electrode mask plate according to the present invention.
FIG. 5 is a schematic structural diagram of Au source-drain electrode deposition according to the present invention.
FIG. 6 is a schematic structural diagram of a protein film according to the present invention.
Fig. 7 is a schematic structural diagram of a protective layer mask plate according to the present invention.
FIG. 8 is a schematic structural diagram of a protective layer mask plate covering the unpolished side of an iron foil substrate according to the present invention.
FIG. 9 shows HfO according to the present invention2The structure of the protective layer is shown schematically.
FIG. 10 shows a fixture and HfO according to the present invention2The structure of the protective layer is shown schematically.
Fig. 11 is a schematic diagram of a structure in which the iron foil substrate is removed.
Fig. 12 is a schematic structural diagram of a p-type SnO thin film transistor subjected to moisture triggered degradation and obtained after gate electrode deposition.
Detailed Description
The present invention is further described in detail below with reference to the attached drawings so that those skilled in the art can implement the invention by referring to the description text.
As shown in figures 1-12, the present invention provides a method for preparing a moisture-triggered degradation P-type transient thin film transistor, which comprises preparing a semiconductor device on a single-side polished iron foil substrate with good heat resistance, dripping a solution of a degradable substrate material on the device, exposing the unpolished side of the iron foil to a dilute hydrochloric acid solution after the solvent is evaporated, dissolving the iron foil, effectively preventing the protein substrate from being damaged by the hydrochloric acid solution due to the isolation effect of an insulating layer, and finally preparing a gate electrode to obtain the gate electrodeA moisture triggered degradation p-type transient thin film transistor device comprising: iron foil substrate 100, SiO2The active device comprises an insulating layer 200, an active layer mask plate 310, a SnO active layer 320, a source-drain electrode mask plate 410, an Au source-drain electrode 420, a silk fibroin film substrate 500, a protective layer mask plate 610 and HfO2The protective layer 620, the fixture upper plate 710, the fixture lower plate 720, and the Al gate electrode 800 specifically include:
placing a single-side polished iron foil substrate in plasma enhanced chemical vapor deposition equipment, and performing insulating layer deposition on the polished side of the iron foil substrate to obtain a first sample;
covering the active layer template on the first sample, and depositing an active layer material in a radio frequency magnetron sputtering device to obtain a second sample;
covering a source-drain electrode mask plate on the second sample, placing the second sample in a thermal evaporation table for source-drain electrode material deposition to obtain a third sample, and placing the third sample in a rapid annealing furnace for annealing to obtain a fourth sample;
step four, coating the silk fibroin aqueous solution with the concentration of 6% on the surface of a fourth sample, and drying to obtain a fifth sample;
covering a protective layer mask plate on the unpolished substrate of the fifth sample, and depositing a protective layer material in radio frequency magnetron sputtering equipment to obtain a sixth sample;
fixing the sixth sample in a clamp, and immersing the sixth sample in dilute hydrochloric acid to dissolve the iron foil substrate in the sixth sample to obtain a seventh sample;
wherein the polished side of the iron foil substrate in the sixth sample is directed to the lower plate of the jig, and the unpolished side is directed to the upper plate of the jig;
step seven, placing the seventh sample in an electron beam evaporation device, and evaporating a gate electrode 800 to obtain a moisture-triggered degraded p-type thin film transistor, which comprises the following steps:
1. insulating layer deposition
The single-sided polished iron foil substrate 100 is placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatusIn the preparation, SiO is deposited on the polished side2An insulating layer 200 material, wherein the RF power range is 50-100W, the temperature range is 150-250 ℃, the pressure range is 0.2-0.6 torr, SiH4Flow rate range of 20-40 sccm, N2The flow rate of O is 80-150 sccm and SiO2The thickness of the film is 150-250 nm, and a first sample is obtained, as shown in FIG. 1.
2. Active layer deposition
As shown in fig. 2, an active layer mask 310 with active patterns is covered on a first sample, and the first sample is placed in a radio frequency magnetron sputtering device for deposition of an active layer material, in the present invention, preferably, the active layer material is SnO, a metal Sn target is adopted, and a SnO active layer 320 is obtained by reactive sputtering, wherein the sputtering power range is 25-35W, the temperature is room temperature, the pressure range is 5-7 mtorr, and Ar/O is2The deposition time is 10-20 min, the film thickness is 45-70 nm, and a second sample is obtained, as shown in FIG. 3.
3. Source drain electrode deposition
As shown in fig. 4, a source/drain mask 410 with a source/drain electrode pattern is covered on the second sample, and placed in a thermal evaporation table to deposit a source/drain electrode material, in the present invention, preferably, Au is used as the electrode material, and the thickness is 50 to 100nm, so as to obtain a third sample, as shown in fig. 5. The distance between the source electrode and the drain electrode defines the channel length of the transistor device, and the channel length can be different values according to different requirements, and ranges from 10 micrometers to 1 mm.
4. Annealing of active layer
And placing the obtained third sample in a rapid annealing furnace, and annealing for 25-40 min at the temperature of 250-350 ℃ to obtain a fourth sample.
5. Preparation of protein films
And coating the silk fibroin aqueous solution with the concentration of 6 wt% on the surface of the fourth sample, preventing the fourth sample from being dried in a drying oven, and after the solvent in the silk fibroin solution is evaporated, forming a silk fibroin film on the surface of the fourth sample, wherein the silk fibroin film can be used as a silk fibroin film substrate 500 to obtain a fifth sample, as shown in fig. 6.
6. Preparation of iron foil protective layer
As shown in fig. 7 and 8, a mask plate 610 with a protective layer pattern is covered on the unpolished surface of the iron foil substrate 100 in the fifth sample, and is placed in the rf magnetron sputtering apparatus to deposit a protective layer material, wherein the protective layer is used to prevent corrosion of the position of the iron foil edge for fixing in the subsequent process of removing the iron foil substrate2Using ceramic HfO2Obtaining HfO by target sputtering2The protective layer 620 has a sputtering power of 100-250W, a temperature of 25-200 deg.C, a pressure of 8-20 mtorr, Ar/O2The deposition time is within a range of 9: 1-2: 1, the deposition time is within a range of 50-150 min, and the film thickness is within a range of 50-200 nm, so as to obtain a sixth sample, as shown in FIG. 9.
7. Removal of iron foil substrate
As shown in fig. 10, the sixth sample was placed in a fixture comprising: the fixture comprises an upper fixture plate 710 and a lower fixture plate 720, wherein the lower fixture plate 710 is of a rectangular framework, and a rectangular groove is formed in the center of the lower fixture plate and used for accommodating a protein substrate and a semiconductor device; the upper clamp plate 710 is of a rectangular structure and is matched with the lower clamp plate 720, the size of the upper clamp plate 710 is the same as that of the lower clamp plate 720, a through hole is formed in the center of the upper clamp plate 710 and is the same as that of a groove of the lower clamp plate, and the through hole is used for enabling a solution to react with an iron foil through the through hole in a subsequent process.
The polished side of the iron foil in the sixth sample is directed to the lower fixture plate 710, the unpolished side is directed to the upper fixture plate 710, and the upper fixture plate 710 and the lower fixture plate 720 are tightly fixed around to prevent the solution from entering the groove portion of the fixture and damaging the protein substrate in the subsequent process. Immersing the fixed clamp into a dilute hydrochloric acid solution with the concentration of 1-30 wt% to etch the iron foil substrate, wherein SiO is used2Insoluble in dilute hydrochloric acid, so that the silk fibroin film substrate can be effectively prevented from being dissolved, meanwhile, the silk fibroin substrate provides support for a transistor device and prevents the transistor device from being cracked under the action of external force, and the iron foil substrate 100 is used after being dissolvedCleaning the clamp with ionized water, air drying at room temperature, removing the clamp, and cutting out HfO around2The area of the iron foil not etched under the protective layer gave a seventh sample, as shown in fig. 11. A p-type thin film transistor device is to be transferred onto the silk fibroin substrate 500.
The seventh sample was placed in an electron beam Evaporation (EB) apparatus on SiO2As shown in FIG. 12, in the present invention, preferably, the electrode material is Al, the thickness of the electrode is in the range of 50-200 nm, and finally, a p-type SnO thin film transistor with moisture triggered degradation is obtained on the silk fibroin substrate. The switching ratio of the p-type thin film transistor can reach the power of 4 of 10, the transient device is placed in water, the silk fibroin protein substrate can be hydrolyzed within 30 minutes, and the semiconductor function layer is cracked due to loss of support, so that degradation is realized.
Example 1
1. Insulating layer deposition
The single-side polished iron foil substrate 100 was placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus to deposit SiO on the polished side2An insulating layer 200 of SiH material, wherein the RF power is 50W, the temperature is 200 deg.C, and the pressure is 0.2torr4The flow rate was 20sccm, N2O flow rate of 80sccm, SiO2The film thickness was 150nm, and a first sample was obtained as shown in FIG. 1.
2. Active layer deposition
As shown in fig. 2, an active layer mask 310 with active patterns is covered on the first sample, and is placed in a radio frequency magnetron sputtering device for deposition of an active layer material, in the present invention, preferably, the active layer material is SnO, and a metallic Sn target is used to obtain a SnO active layer 320 by reactive sputtering, wherein the sputtering power is 25W, the temperature is room temperature, the pressure is 5mtorr, Ar/O is 5mtorr, and the sputtering power is 25W29:1, deposition time 10min, film thickness 45nm, a second sample was obtained as shown in fig. 3.
3. Source drain electrode deposition
As shown in fig. 4, a source/drain mask 410 with a source/drain electrode pattern was placed on the second sample and placed in a thermal evaporation station to deposit a source/drain electrode material, and in the present invention, it is preferable that the electrode material used be Au with a thickness of 50nm, to obtain a third sample, as shown in fig. 5. Wherein the distance between the source and drain electrodes defines the channel length of the transistor device, and in this embodiment, the channel length is preferably 10 μm.
4. Annealing of active layer
And placing the obtained third sample in a rapid annealing furnace, and annealing for 25min at the temperature of 250 ℃ to obtain a fourth sample.
5. Preparation of protein films
And coating the silk fibroin aqueous solution with the concentration of 6 wt% on the surface of the fourth sample, preventing the fourth sample from being dried in a drying oven, and after the solvent in the silk fibroin solution is evaporated, forming a silk fibroin film on the surface of the fourth sample, wherein the silk fibroin film can be used as a silk fibroin film substrate 500 to obtain a fifth sample, as shown in fig. 6.
6. Preparation of iron foil protective layer
As shown in fig. 7 and 8, a mask plate 610 with a protective layer pattern is covered on the unpolished surface of the iron foil substrate 100 in the fifth sample, and is placed in the rf magnetron sputtering apparatus to deposit a protective layer material, wherein the protective layer is used to prevent corrosion of the position of the iron foil edge for fixing in the subsequent process of removing the iron foil substrate2Using ceramic HfO2Obtaining HfO by target sputtering2The protective layer 620 has a sputtering power of 100W, a temperature of 25 deg.C, a pressure of 8mtorr, Ar/O22:1, deposition time 50min, film thickness 50nm, a sixth sample was obtained as shown in fig. 9.
7. Removal of iron foil substrate
As shown in fig. 10, the sixth sample was placed in a fixture comprising: the fixture comprises an upper fixture plate 710 and a lower fixture plate 720, wherein the lower fixture plate 710 is of a rectangular framework, and a rectangular groove is formed in the center of the lower fixture plate and used for accommodating a protein substrate and a semiconductor device; the upper clamp plate 710 is of a rectangular structure and is matched with the lower clamp plate 720, the size of the upper clamp plate 710 is the same as that of the lower clamp plate 720, a through hole is formed in the center of the upper clamp plate 710 and is the same as that of a groove of the lower clamp plate, and the through hole is used for enabling a solution to react with an iron foil through the through hole in a subsequent process.
The polished side of the iron foil in the sixth sample is directed to the lower fixture plate 710, the unpolished side is directed to the upper fixture plate 710, and the upper fixture plate 710 and the lower fixture plate 720 are tightly fixed around to prevent the solution from entering the groove portion of the fixture and damaging the protein substrate in the subsequent process. Immersing the fixed clamp into a dilute hydrochloric acid solution with the concentration of 1 wt% to etch the iron foil substrate due to SiO2Insoluble in dilute hydrochloric acid, thereby effectively preventing the silk fibroin film substrate from being dissolved, simultaneously, the silk fibroin substrate provides support for a transistor device, prevents the transistor device from being broken under the action of external force, after the iron foil substrate 100 is dissolved, the fixture is cleaned by deionized water and dried at room temperature, the fixture is disassembled, and the HfO at the periphery is cut off2The area of the iron foil not etched under the protective layer gave a seventh sample, as shown in fig. 11. A p-type thin film transistor device is to be transferred onto the silk fibroin substrate 500.
The seventh sample was placed in an electron beam Evaporation (EB) apparatus on SiO2As shown in fig. 12, in the present invention, preferably, the electrode material is Al, the thickness of the electrode is 50nm, and finally, a p-type SnO thin film transistor with moisture triggered degradation is obtained on the silk fibroin substrate.
Example 2
1. Insulating layer deposition
The single-side polished iron foil substrate 100 was placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus to deposit SiO on the polished side2An insulating layer 200 of material, wherein the RF power is 50W, the temperature is 150 deg.C, the pressure is 0.3torr, SiH4Flow range 30sccm, N2O flow range 100sccm, SiO2The film thickness ranged from 170nm, and the first sample was obtained, as shown in FIG. 1.
2. Active layer deposition
As shown in fig. 2, will carry an active patternThe active layer mask plate 310 is covered on the first sample, and the first sample is placed in radio frequency magnetron sputtering equipment for active layer material deposition, in the invention, the active layer material is preferably SnO, a metal Sn target is adopted, and the SnO active layer 320 is obtained by reactive sputtering, wherein the sputtering power range is 30W, the temperature is room temperature, the pressure range is 6mtorr, Ar/O2The range 7:1, deposition time range 13min, film thickness 65nm, gave a second sample, as shown in FIG. 3.
3. Source drain electrode deposition
As shown in fig. 4, a source/drain mask 410 with a source/drain electrode pattern is covered on the second sample and placed in a thermal evaporation station to deposit a source/drain electrode material, and in the present invention, preferably, Au is used as an electrode material with a thickness of 100nm, to obtain a third sample, as shown in fig. 5. Wherein the distance between the source and drain electrodes defines the channel length of the transistor device, which in the present invention is 1 mm.
4. Annealing of active layer
And placing the obtained third sample in a rapid annealing furnace, and annealing for 20min at the temperature of 300 ℃ to obtain a fourth sample.
5. Preparation of protein films
And coating the silk fibroin aqueous solution with the concentration of 6 wt% on the surface of the fourth sample, preventing the fourth sample from being dried in a drying oven, and after the solvent in the silk fibroin solution is evaporated, forming a silk fibroin film on the surface of the fourth sample, wherein the silk fibroin film can be used as a silk fibroin film substrate 500 to obtain a fifth sample, as shown in fig. 6.
6. Preparation of iron foil protective layer
As shown in fig. 7 and 8, a mask plate 610 with a protective layer pattern is covered on the unpolished surface of the iron foil substrate 100 in the fifth sample, and is placed in the rf magnetron sputtering apparatus to deposit a protective layer material, wherein the protective layer is used to prevent corrosion of the position of the iron foil edge for fixing in the subsequent process of removing the iron foil substrate2Using ceramic HfO2Obtaining HfO by target sputtering2The protective layer 620 has a sputtering power range of 250W, a temperature of 200 deg.C, a pressure range of 20mtorr, Ar/O2The range 2:1, the deposition time range 150min, and the film thickness 200nm, a sixth sample was obtained, as shown in fig. 9.
7. Removal of iron foil substrate
As shown in fig. 10, the sixth sample was placed in a fixture comprising: the fixture comprises an upper fixture plate 710 and a lower fixture plate 720, wherein the lower fixture plate 710 is of a rectangular framework, and a rectangular groove is formed in the center of the lower fixture plate and used for accommodating a protein substrate and a semiconductor device; the upper clamp plate 710 is of a rectangular structure and is matched with the lower clamp plate 720, the size of the upper clamp plate 710 is the same as that of the lower clamp plate 720, a through hole is formed in the center of the upper clamp plate 710 and is the same as that of a groove of the lower clamp plate, and the through hole is used for enabling a solution to react with an iron foil through the through hole in a subsequent process.
The polished side of the iron foil in the sixth sample is directed to the lower fixture plate 710, the unpolished side is directed to the upper fixture plate 710, and the upper fixture plate 710 and the lower fixture plate 720 are tightly fixed around to prevent the solution from entering the groove portion of the fixture and damaging the protein substrate in the subsequent process. Immersing the fixed clamp into a dilute hydrochloric acid solution with the concentration of 50 wt% to etch the iron foil substrate due to SiO2Insoluble in dilute hydrochloric acid, thereby effectively preventing the silk fibroin film substrate from being dissolved, simultaneously, the silk fibroin substrate provides support for a transistor device, prevents the transistor device from being broken under the action of external force, after the iron foil substrate 100 is dissolved, the fixture is cleaned by deionized water and dried at room temperature, the fixture is disassembled, and the HfO at the periphery is cut off2The area of the iron foil not etched under the protective layer gave a seventh sample, as shown in fig. 11. A p-type thin film transistor device is to be transferred onto the silk fibroin substrate 500.
The seventh sample was placed in an electron beam Evaporation (EB) apparatus on SiO2As shown in FIG. 12, in the present invention, preferably, the electrode material is Al, the thickness of the electrode is 200nm, and finally, a p-type SnO thin film transistor with moisture triggered degradation is obtained on a silk fibroin substrate。
Example 3
1. Insulating layer deposition
The single-side polished iron foil substrate 100 was placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus to deposit SiO on the polished side2An insulating layer 200 of SiH material, wherein the RF power is 50W, the temperature is 200 deg.C, and the pressure is 0.2torr4The flow rate was 25sccm, N2O flow rate of 100sccm, SiO2The film thickness was 200nm, and a first sample was obtained as shown in FIG. 1.
2. Active layer deposition
As shown in fig. 2, an active layer mask plate 310 with active patterns is covered on the first sample, and is placed in a radio frequency magnetron sputtering device for deposition of an active layer material, in the present invention, preferably, the active layer material is SnO, a metal Sn target is used, and a SnO active layer 320 is obtained by reactive sputtering, wherein the sputtering power is 25W, the temperature is room temperature, the pressure is 5mtorr, and Ar/O is29:1, deposition time 10min, film thickness 50nm, a second sample was obtained as shown in fig. 3.
3. Source drain electrode deposition
As shown in fig. 4, a source/drain mask 410 with a source/drain electrode pattern was placed on the second sample and placed in a thermal evaporation station to deposit a source/drain electrode material, and in the present invention, it is preferable that the electrode material used be Au with a thickness of 50nm, to obtain a third sample, as shown in fig. 5. Wherein the distance between the source and drain electrodes defines the channel length of the transistor device, which in this embodiment is preferably 50 μm.
4. Annealing of active layer
And (4) placing the obtained third sample in a rapid annealing furnace, and annealing for 30min at the temperature of 250 ℃ to obtain a fourth sample.
5. Preparation of protein films
And coating the silk fibroin aqueous solution with the concentration of 6 wt% on the surface of the fourth sample, placing the fourth sample in a drying oven for drying, and after the solvent in the silk fibroin solution is evaporated, forming a silk fibroin film on the surface of the fourth sample, wherein the silk fibroin film can be used as a silk fibroin film substrate 500 to obtain a fifth sample, as shown in fig. 6.
6. Preparation of iron foil protective layer
As shown in fig. 7 and 8, a mask plate 610 with a protective layer pattern is covered on the unpolished surface of the iron foil substrate 100 in the fifth sample, and is placed in the rf magnetron sputtering apparatus to deposit a protective layer material, wherein the protective layer is used to prevent corrosion of the position of the iron foil edge for fixing in the subsequent process of removing the iron foil substrate2Using ceramic HfO2Target sputtering to obtain HfO2The protective layer 620 has a sputtering power of 150W, a temperature of 30 deg.C, a pressure of 8mtorr, Ar/O29:1, deposition time 120min, film thickness 200nm, a sixth sample was obtained, as shown in fig. 9.
7. Removal of iron foil substrate
As shown in fig. 10, the sixth sample was placed in a fixture comprising: the fixture comprises an upper fixture plate 710 and a lower fixture plate 720, wherein the lower fixture plate 710 is of a rectangular framework, and a rectangular groove is formed in the center of the lower fixture plate and used for accommodating a protein substrate and a semiconductor device; the upper clamp plate 710 is of a rectangular structure and is matched with the lower clamp plate 720, the size of the upper clamp plate 710 is the same as that of the lower clamp plate 720, a through hole is formed in the center of the upper clamp plate 710 and is the same as that of a groove of the lower clamp plate, and the through hole is used for enabling a solution to react with an iron foil through the through hole in a subsequent process.
The polished side of the iron foil in the sixth sample is directed to the lower fixture plate 710, the unpolished side is directed to the upper fixture plate 710, and the upper fixture plate 710 and the lower fixture plate 720 are tightly fixed around to prevent the solution from entering the groove portion of the fixture and damaging the protein substrate in the subsequent process. Immersing the fixed clamp into a dilute hydrochloric acid solution with the concentration of 10 wt% to etch the iron foil substrate due to SiO2Insoluble in dilute hydrochloric acid, so that the silk fibroin film substrate can be effectively prevented from being dissolved, and simultaneously, the silk fibroin substrate provides support for a transistor device, prevents the transistor device from being cracked under the action of external force, and waits for the iron foil substrate to be dissolvedAfter the bottom 100 is dissolved, the clamp is cleaned by deionized water and dried at room temperature, the clamp is detached, and the HfO on the periphery is cut off2The area of the iron foil not etched under the protective layer gave a seventh sample, as shown in fig. 11. A p-type thin film transistor device is to be transferred onto the silk fibroin substrate 500.
The seventh sample was placed in an electron beam Evaporation (EB) apparatus on SiO2As shown in fig. 12, in the present invention, preferably, the electrode material is Al, the thickness of the electrode is 50nm, and finally, a p-type SnO thin film transistor with moisture triggered degradation is obtained on the silk fibroin substrate.
Example 4
1. Insulating layer deposition
The single-side polished iron foil substrate 100 was placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus to deposit SiO on the polished side2An insulating layer 200 of SiH material, wherein the RF power is 100W, the temperature is 250 deg.C, and the pressure is 0.6torr4The flow rate was 40sccm, N2O flow rate of 150sccm, SiO2The film thickness was 250nm, and a first sample was obtained as shown in FIG. 1.
2. Active layer deposition
As shown in fig. 2, an active layer mask 310 with active patterns is covered on the first sample, and is placed in a radio frequency magnetron sputtering device for deposition of an active layer material, in the present invention, preferably, the active layer material is SnO, a metallic Sn target is used, and a SnO active layer 320 is obtained by reactive sputtering, wherein the sputtering power is 35W, the temperature is room temperature, the pressure is 7mtorr, Ar/O is 7mtorr, and the sputtering power is 35W2At 4:1, the deposition time was 20min, and the film thickness was 70nm, to obtain a second sample, as shown in FIG. 3.
3. Source drain electrode deposition
As shown in fig. 4, a source/drain mask 410 with a source/drain electrode pattern was placed on the second sample and placed in a thermal evaporation station to deposit a source/drain electrode material, and in the present invention, it is preferable that the electrode material used be Au with a thickness of 75nm, to obtain a third sample, as shown in fig. 5. Wherein the distance between the source and drain electrodes defines the channel length of the transistor device, which in this embodiment is preferably 200 μm.
4. Annealing of active layer
And placing the obtained third sample in a rapid annealing furnace, and annealing for 40min at the temperature of 300 ℃ to obtain a fourth sample.
5. Preparation of protein films
And coating the silk fibroin aqueous solution with the concentration of 6 wt% on the surface of the fourth sample, placing the fourth sample in a drying oven for drying, and after the solvent in the silk fibroin solution is evaporated, forming a silk fibroin film on the surface of the fourth sample, wherein the silk fibroin film can be used as a silk fibroin film substrate 500 to obtain a fifth sample, as shown in fig. 6.
6. Preparation of iron foil protective layer
As shown in fig. 7 and 8, a mask plate 610 with a protective layer pattern is covered on the unpolished surface of the iron foil substrate 100 in the fifth sample, and is placed in the rf magnetron sputtering apparatus to deposit a protective layer material, wherein the protective layer is used to prevent corrosion of the position of the iron foil edge for fixing in the subsequent process of removing the iron foil substrate2Using ceramic HfO2Obtaining HfO by target sputtering2The protective layer 620 has a sputtering power of 200W, a temperature of 100 deg.C, a pressure of 13mtorr, Ar/O24:1, deposition time 90min, film thickness 150nm, a sixth sample was obtained as shown in fig. 9.
7. Removing the iron foil substrate
As shown in fig. 10, the sixth sample was placed in a fixture comprising: the fixture comprises an upper fixture plate 710 and a lower fixture plate 720, wherein the lower fixture plate 710 is of a rectangular framework, and a rectangular groove is formed in the center of the lower fixture plate and used for accommodating a protein substrate and a semiconductor device; the upper clamp plate 710 is of a rectangular structure and is matched with the lower clamp plate 720, the size of the upper clamp plate 710 is the same as that of the lower clamp plate 720, a through hole is formed in the center of the upper clamp plate 710 and is the same as that of a groove of the lower clamp plate, and the through hole is used for enabling a solution to react with an iron foil through the through hole in a subsequent process.
The polished side of the iron foil in the sixth sample is directed to the lower fixture plate 710, the unpolished side is directed to the upper fixture plate 710, and the upper fixture plate 710 and the lower fixture plate 720 are tightly fixed around to prevent the solution from entering the groove portion of the fixture and damaging the protein substrate in the subsequent process. Immersing the fixed clamp into a dilute hydrochloric acid solution with the concentration of 15 wt% to etch the iron foil substrate due to SiO2Insoluble in dilute hydrochloric acid, thereby effectively preventing the silk fibroin film substrate from being dissolved, simultaneously, the silk fibroin substrate provides support for a transistor device, prevents the transistor device from being broken under the action of external force, after the iron foil substrate 100 is dissolved, the fixture is cleaned by deionized water and dried at room temperature, the fixture is disassembled, and the HfO at the periphery is cut off2The area of the iron foil not etched under the protective layer gave a seventh sample, as shown in fig. 11. A p-type thin film transistor device is to be transferred onto the silk fibroin substrate 500.
The seventh sample was placed in an electron beam Evaporation (EB) apparatus on SiO2As shown in fig. 12, in the present invention, preferably, the electrode material is Al, the thickness of the electrode is 100nm, and finally, a p-type SnO thin film transistor with moisture triggered degradation is obtained on the silk fibroin substrate.
Comparative example 1
1. Insulating layer deposition
The single-side polished iron foil substrate 100 was placed in a Plasma Enhanced Chemical Vapor Deposition (PECVD) apparatus to deposit SiO on the polished side2An insulating layer 200 of SiH material, wherein the RF power is 50W, the temperature is 200 deg.C, and the pressure is 0.2torr4The flow rate was 25sccm, N2O flow rate of 100sccm, SiO2The film thickness was 200nm, and a first sample was obtained as shown in FIG. 1.
2. Active layer deposition
As shown in fig. 2, an active layer mask plate 310 with active patterns is covered on the first sample, and is placed in the rf magnetron sputtering apparatus for deposition of an active layer material, wherein the active layer material is preferably SnO, and SnO is adopted in the present inventionA metal Sn target, and obtaining the SnO active layer 320 by reactive sputtering, wherein the sputtering power is 40W, the temperature is room temperature, the pressure is 15mtorr, and Ar/O21:1, deposition time 40min, film thickness 200nm, a second sample was obtained as shown in fig. 3.
3. Source drain electrode deposition
As shown in fig. 4, a source/drain mask 410 with a source/drain electrode pattern was placed on the second sample and placed in a thermal evaporation station to deposit a source/drain electrode material, and in the present invention, it is preferable that the electrode material used be Au with a thickness of 50nm, to obtain a third sample, as shown in fig. 5. Wherein the distance between the source and drain electrodes defines the channel length of the transistor device, which in this embodiment is preferably 50 μm.
4. Annealing of active layer
And (4) placing the obtained third sample in a rapid annealing furnace, and annealing for 30min at the temperature of 250 ℃ to obtain a fourth sample.
5. Preparation of protein films
And coating the silk fibroin aqueous solution with the concentration of 6 wt% on the surface of the fourth sample, placing the fourth sample in a drying oven for drying, and after the solvent in the silk fibroin solution is evaporated, forming a silk fibroin film on the surface of the fourth sample, wherein the silk fibroin film can be used as a silk fibroin film substrate 500 to obtain a fifth sample, as shown in fig. 6.
6. Preparation of iron foil protective layer
As shown in fig. 7 and 8, a mask plate 610 with a protective layer pattern is covered on the unpolished surface of the iron foil substrate 100 in the fifth sample, and is placed in the rf magnetron sputtering apparatus to deposit a protective layer material, wherein the protective layer is used to prevent corrosion of the position of the iron foil edge for fixing in the subsequent process of removing the iron foil substrate2Using ceramic HfO2Obtaining HfO by target sputtering2The protective layer 620 has a sputtering power of 150W, a temperature of 30 deg.C, a pressure of 8mtorr, Ar/O29:1, deposition time 120min, film thickness 200nm, a sixth sample was obtained, as shown in fig. 9.
7. Removal of iron foil substrate
As shown in fig. 10, the sixth sample was placed in a fixture comprising: the fixture comprises an upper fixture plate 710 and a lower fixture plate 720, wherein the lower fixture plate 710 is of a rectangular framework, and a rectangular groove is formed in the center of the lower fixture plate and used for accommodating a protein substrate and a semiconductor device; the upper clamp plate 710 is of a rectangular structure and is matched with the lower clamp plate 720, the size of the upper clamp plate 710 is the same as that of the lower clamp plate 720, a through hole is formed in the center of the upper clamp plate 710 and is the same as that of a groove of the lower clamp plate, and the through hole is used for enabling a solution to react with an iron foil through the through hole in a subsequent process.
The polished side of the iron foil in the sixth sample is directed to the lower fixture plate 710, the unpolished side is directed to the upper fixture plate 710, and the upper fixture plate 710 and the lower fixture plate 720 are tightly fixed around to prevent the solution from entering the groove portion of the fixture and damaging the protein substrate in the subsequent process. Immersing the fixed clamp into a dilute hydrochloric acid solution with the concentration of 10 wt% to etch the iron foil substrate due to SiO2Insoluble in dilute hydrochloric acid, thereby effectively preventing the silk fibroin film substrate from being dissolved, simultaneously, the silk fibroin substrate provides support for a transistor device, prevents the transistor device from being broken under the action of external force, after the iron foil substrate 100 is dissolved, the fixture is cleaned by deionized water and dried at room temperature, the fixture is disassembled, and the HfO at the periphery is cut off2The area of the iron foil not etched under the protective layer gave a seventh sample, as shown in fig. 11. A p-type thin film transistor device is to be transferred onto the silk fibroin substrate 500.
The seventh sample was placed in an electron beam Evaporation (EB) apparatus on SiO2As shown in fig. 12, in the present invention, preferably, the electrode material is Al, the thickness of the electrode is 50nm, and finally, a p-type SnO thin film transistor with moisture triggered degradation is obtained on the silk fibroin substrate.
Comparative example 2
Directly depositing a p-type thin film transistor on a protein substrate by the following specific method:
1. preparing a protein substrate film, taking a flat PET plastic plate, coating silk fibroin aqueous solution with the concentration of 6 wt% on the PET plastic plate, placing the PET plastic plate in a drying box for drying, and obtaining the hydrolyzable protein substrate film after the solvent in the protein solution is evaporated.
2. The protein substrate is placed in an electron beam evaporation device, an aluminum film is evaporated to be used as a gate electrode, and the thickness of the electrode is 100 nm.
3. Placing the protein substrate plated with the gate electrode in radio frequency magnetron sputtering equipment, and depositing an insulating layer, wherein the insulating layer is made of HfO (high frequency oxide)2Using ceramic HfO2Target sputtering to obtain HfO2Insulating layer, sputtering power of 150W, reaction chamber temperature of 25 deg.C, pressure of 8mtorr, and introducing Ar and O2The flow ratio of (A) was 9:1, the deposition time was 150min, and the thickness of the insulating layer film was 150 nm.
4. Covering an active layer mask plate 310 on the insulating layer, placing the active layer mask plate in radio frequency magnetron sputtering equipment, performing active layer material deposition, and performing active layer deposition, wherein the active layer material is SnO, and a metal Sn target is adopted to obtain a SnO material through reactive sputtering; sputtering power is 25W, the temperature of the reaction chamber is room temperature, the pressure is 5mtorr, Ar and O are introduced2The flow ratio of (A) to (B) was 9:1, the deposition time was 10min, and the film thickness was 50 nm. And (3) placing the protein substrate on which the active layer is deposited in a rapid annealing furnace, and annealing for 30min at the temperature of 100 ℃.
5. And covering the source and drain mask plate 410 on the active layer, placing the active layer and the source and drain mask plate in a thermal evaporation table together, and depositing a source and drain electrode material, wherein the source and drain electrode material is Au, and the thickness is 50nm, so as to obtain the contrast device.
TABLE 1 comparison of device parameters
| On-state current | Off-state current | On-off ratio | |
| Example 1 | 25μA | 1.62nA | 15432 |
| Example 2 | 19μA | 1.74nA | 10920 |
| Example 3 | 13μA | 875pA | 14857 |
| Example 4 | 15μA | 1.13nA | 13274 |
| Comparative example 1 | 36μA | 34μA | 1.06 |
| Comparative example 2 | 216μA | 5.9μA | 36.6 |
Table 1 shows the comparison of the device parameters of the examples and the comparative examples, and it can be seen from table 1 that the p-type transient thin film transistor devices with moisture triggered degradation, which have the on-off ratios of more than 10000, can be realized in examples 1 to 4, and the devices prepared in examples 1 to 4 are placed in water, the silk fibroin substrate can be hydrolyzed within 30 minutes, and the semiconductor functional layer is cracked due to the loss of support, so as to realize degradation.
The preparation conditions of the active layer in the comparative example 1 are greatly deviated from the optimal conditions, so that the oxygen content of the active layer is too high, and the source-drain current hardly changes along with the change of the gate voltage, namely the carrier concentration of the channel layer is not controlled by the gate voltage and the p-type conduction characteristic cannot be presented.
The thin film transistor device directly deposited on the protein substrate in comparative example 2 is limited by the heat resistance of the protein substrate, and the annealing temperature is limited to 100 ℃ or less, so that the on-off ratio of the device is less than 100.
Therefore, the invention can realize the preparation of transistor devices on the protein substrate, overcomes the limitation of the heat resistance of the substrate material to the preparation temperature of the devices, is beneficial to improving the performance of the devices, and also avoids the damage of aqueous solution to the water-soluble protein substrate in the preparation process of the devices, so that the preparation of transient electronic devices which are subjected to moisture triggering degradation and need high-temperature treatment becomes possible.
While embodiments of the invention have been described above, it is not limited to the applications set forth in the description and the embodiments, which are fully applicable in various fields of endeavor to which the invention pertains, and further modifications may readily be made by those skilled in the art, it being understood that the invention is not limited to the details shown and described herein without departing from the general concept defined by the appended claims and their equivalents.
Claims (8)
1. A preparation method of a p-type transient thin film transistor with moisture triggered degradation is characterized by comprising the following steps:
placing a single-side polished iron foil substrate in plasma enhanced chemical vapor deposition equipment, and performing insulating layer deposition on the polished side of the iron foil substrate to obtain a first sample;
covering the active layer template on the first sample, and depositing an active layer material in a radio frequency magnetron sputtering device to obtain a second sample;
covering a source-drain electrode mask plate on the second sample, placing the second sample in a thermal evaporation table for source-drain electrode material deposition to obtain a third sample, and placing the third sample in a rapid annealing furnace for annealing to obtain a fourth sample;
step four, coating the silk fibroin aqueous solution with the concentration of 6% on the surface of a fourth sample, and drying to obtain a fifth sample;
covering a protective layer mask plate on the unpolished substrate of the fifth sample, and depositing a protective layer material in radio frequency magnetron sputtering equipment to obtain a sixth sample;
fixing the sixth sample in a clamp, and immersing the sixth sample in dilute hydrochloric acid to dissolve the iron foil substrate in the sixth sample to obtain a seventh sample;
wherein the polished side of the iron foil substrate in the sixth sample is directed to the lower plate of the jig, and the unpolished side is directed to the upper plate of the jig;
and step seven, placing the seventh sample in electron beam evaporation equipment, and evaporating a gate electrode to obtain the p-type thin film transistor triggered and degraded by moisture.
2. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 1, wherein the step one comprises the following steps:
deposition of SiO on the polished side of an iron foil substrate2An insulating layer material;
wherein the RF power is 50-100W, the deposition temperature is 150-250 deg.C, the pressure is 0.2-0.6 torr, SiH4The flow rate is 20-40 sccm, N2The flow rate of O is 80-150 sccm, SiO2The thickness of the film is 150 to 250 nm.
3. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 2, wherein the second step comprises:
the active layer material is SnO, and the deposition of the active layer material is carried out by adopting a metal Sn target;
wherein the sputtering power is 25-35W, the temperature is room temperature, the pressure is 5-7 mtorr, Ar/O2The deposition time is 9: 1-2: 1, the deposition time is 10-20 min, and the film thickness is 45-70 nm.
4. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 3, wherein the third step comprises:
the electrode material is Au, and the thickness of the electrode material is 50-100 nm;
the distance between the adjacent source and drain electrodes is 10 mu m-1 mm;
the annealing temperature is 250-350 ℃, and the annealing time is 25-40 min.
5. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 4, wherein the fourth step comprises:
the protective layer is made of HfO2The sputtering power is 100-250W, the temperature is 25-200 ℃, the pressure is 8-20 mtorr, Ar/O29: 1-2: 1, deposition time of 50-150 min, and film thickness of 50-200 nm.
6. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 5, wherein the sixth step comprises:
the clamp comprises an upper clamp plate and a lower clamp plate, the upper clamp plate and the lower clamp plate are both rectangular, a rectangular groove is formed in the center of the lower clamp plate, and a through hole is formed in the center of the upper clamp plate;
the concentration of the dilute hydrochloric acid is as follows: 1 to 30 wt%.
7. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 6, wherein the seventh step comprises:
the electrode material is Al, and the thickness of the electrode is 50-200 nm.
8. The method for preparing a p-type transient thin film transistor with moisture triggered degradation according to claim 7,
in the first step, the radio frequency power is 50W, the deposition temperature is 200 ℃, the pressure is 0.2torr, and SiH is adopted4The flow rate was 20sccm, N2O flow rate of 80sccm, SiO2The thickness of the film is 150 nm;
in the second step, the sputtering power is 25W, the temperature is room temperature, the pressure is 5mtorr, Ar/O2The deposition time is 10min, and the film thickness is 45nm, wherein the deposition time is 9: 1;
in the third step, the electrode material is Au, and the thickness is 50 nm;
the distance between adjacent source and drain electrodes is: 10 mu m;
the annealing temperature is as follows: annealing at 250 deg.C for 25 min;
in the fourth step, the sputtering power is as follows: 100W, 25 ℃ and 8mtorr Ar/O pressure2Is a ratio of 2:1, depositing for 50min, wherein the thickness of the film is 50 nm;
in the sixth step, the concentration of the dilute hydrochloric acid is as follows: 1 wt%;
in the seventh step, the thickness of the electrode is 50 nm.
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