CN113555051B - SAR imaging data transposition processing system based on DDR SDRAM - Google Patents
SAR imaging data transposition processing system based on DDR SDRAM Download PDFInfo
- Publication number
- CN113555051B CN113555051B CN202110834387.0A CN202110834387A CN113555051B CN 113555051 B CN113555051 B CN 113555051B CN 202110834387 A CN202110834387 A CN 202110834387A CN 113555051 B CN113555051 B CN 113555051B
- Authority
- CN
- China
- Prior art keywords
- ram
- write
- data
- group
- control unit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S13/00—Systems using the reflection or reradiation of radio waves, e.g. radar systems; Analogous systems using reflection or reradiation of waves whose nature or wavelength is irrelevant or unspecified
- G01S13/88—Radar or analogous systems specially adapted for specific applications
- G01S13/89—Radar or analogous systems specially adapted for specific applications for mapping or imaging
- G01S13/90—Radar or analogous systems specially adapted for specific applications for mapping or imaging using synthetic aperture techniques, e.g. synthetic aperture radar [SAR] techniques
- G01S13/9021—SAR image post-processing techniques
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/28—Details of pulse systems
- G01S7/2806—Employing storage or delay devices which preserve the pulse form of the echo signal, e.g. for comparing and combining echoes received during different periods
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
- G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
- G01S7/02—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S13/00
- G01S7/35—Details of non-pulse systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06M—COUNTING MECHANISMS; COUNTING OF OBJECTS NOT OTHERWISE PROVIDED FOR
- G06M3/00—Counters with additional facilities
- G06M3/08—Counters with additional facilities for counting the input from several sources; for counting inputs of different amounts
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Remote Sensing (AREA)
- Radar, Positioning & Navigation (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Networks & Wireless Communication (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Electromagnetism (AREA)
- Databases & Information Systems (AREA)
- Image Processing (AREA)
Abstract
The invention belongs to the technical field of radar imaging signals, and particularly relates to a SAR imaging data transposition processing system based on DDR SDRAM. The invention comprises a data input interface, input data channel switching, a write RAM control unit, a read RAM control unit, an RAM group 1, an RAM group 2, output data channel selection, asynchronous FIFO, output drive and DDR SDRAM. Multiple lines of input data are cached by using RAM resources in the FPGA, and then the data are written into the DDR by using a DDR burst transfer technology. The invention can improve the efficiency of writing the transposed input data into the DDR after the transposition, and simultaneously ensures that the transposed column data can be read out at the highest speed.
Description
Technical Field
The invention belongs to the technical field of radar imaging signals, and particularly relates to a SAR imaging data transposition processing system based on DDR SDRAM.
Background
Synthetic Aperture Radars (SAR) have all-weather working characteristics and high-resolution imaging accuracy all day long, and play a great role in remote sensing mapping in cloudy and foggy areas, military reconnaissance, national economic construction and the like. In recent years, with the rapid development of the hardware manufacturing level, the SAR real-time imaging system design is receiving more and more research. In addition, the SAR imaging signal processing process involves the transmission and storage of a large data volume, and because the access of data needs to be switched between a distance dimension and an azimuth dimension in the imaging processing process, the transposition efficiency is directly related to the SAR imaging signal processing speed.
At present, DDR SDRAM (double rate synchronous dynamic random access memory) is applied more and more in SAR imaging signal processing due to the advantages of large storage capacity, high speed, low power consumption, low cost and the like. In a SAR imaging processing system based on DDR SDRAM, a two-page type or three-page type transposition method is adopted in previous research, matrix transposition is realized by circularly accessing two or three SDRAM, the realization is simpler, but more external storage resources are occupied, and the system volume is larger due to the adoption of a plurality of SDRAM, the system power consumption is higher, and the miniaturization development of the SAR imaging system is not facilitated. The paper published by Nanjing electronics technology institute Wu Qinwen, "a high-efficiency matrix transposition method based on FPGA and DDR," disassembles data from a row dimension, and arranges an original row of data into a new small matrix to balance read-write efficiency, but in the method, a calculation method of a read-write address depends on a matrix scale and a DDR SDRAM row-column length, algorithm transplantation difficulty is large, and in addition to read-write balance, improvement of read-write access efficiency is at the cost of reduction of write-access efficiency. A paper published by the Western Ann electronic engineering research institute Liu Chen and the like, "a CTM algorithm based on DDR SDRAM and an implementation" propose a fastest column reading matrix transposition algorithm, firstly two azimuth data are received, and the two data are spliced and written into the DDR SDRAM alternately, the method can arrange the column data in sequence so as to read out the data sequentially, but the algorithm is related to the SAR imaging distance direction and azimuth data length, and the stability and the portability of the algorithm are poor.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a SAR imaging data transposition processing system based on DDR SDRAM, which caches a plurality of row data by using RAM resources in FPGA and writes the data into the DDR SDRAM by using the burst transmission technology of the DDR SDRAM.
The technical scheme of the invention is as follows:
a SAR imaging data transposition processing system based on DDR SDRAM is characterized by comprising a data input interface, an input data channel switching module, a write RAM control unit, a read RAM control unit, a first RAM group, a second RAM group, an output data channel switching module, an asynchronous FIFO, an output driver and DDR SDRAM; the first RAM group and the second RAM group are respectively provided with N independent RAM blocks, the data input bit widths and the depths of all the RAM blocks are the same, and each RAM block is provided with an independent write enable signal input port, a write address signal input port, a write data input bus, a read enable signal input port, a read address signal input port and a read data output bus; the write RAM control unit is internally provided with two counters, namely a first write counter and a second write counter, and the read RAM control unit is internally provided with a read counter;
the output end of the data input interface is connected with the input end of the input data channel switching module, the write data input buses of the first RAM group and the second RAM group are connected with the output end of the input data channel switching module, the write enable ports of the first RAM group and the second RAM group are connected with the enable signal output port of the write RAM control unit, and the write address ports of the first RAM group and the second RAM group are connected with the address signal output port of the write RAM control unit; the read data output buses of the first RAM group and the second RAM group are connected with the input end of the output data channel switching module, the read enable ports of the first RAM group and the second RAM group are connected with the enable signal output port of the read RAM control unit, and the read address ports of the first RAM group and the second RAM group are connected with the address signal output port of the read RAM control unit; the RAM group readable mark signal output port of the write RAM control unit is connected to the readable mark signal input port of the read RAM control unit; the RAM group writable mark signal output port of the read RAM control unit is connected to the writable mark signal input port of the write RAM control unit; the output end of the output data channel switching module is connected with the input end of the asynchronous FIFO; the output end of the asynchronous FIFO is connected to the input end of an output driver, and the output end of the output driver is connected to a user interface of the DDR SDRAM;
the input data channel switching module is used for selecting a data path between data input to the RAM group; the output data channel switching module is used for selecting a data path from the RAM group to the asynchronous FIFO;
the write RAM control unit generates corresponding write enable signals and corresponding write address signals under the control of the first write counter and the second write counter, so that input data are written into the first RAM group or the second RAM group, and meanwhile, a currently written RAM group readable mark signal is set to be 0; the step length of the first write counter is 1 each time, the address signal is 1 each time, after the first write counter reaches a set first upper write limit value, the first write counter is cleared and starts counting again, and the address signal is cleared and starts increasing again; after the first write counter reaches a set first write upper limit value each time, the write RAM control unit generates an enable signal for writing the next RAM block; after the first write counter reaches a set first write upper limit value each time, the second write counter is automatically added by 1, and after the first write counter reaches the set second write upper limit value, the second write counter is reset and starts counting again; after the first write counter reaches a set first write upper limit value and the second write counter reaches a set second write upper limit value, the write RAM control unit generates an enable signal for writing another RAM group RAM block 1 and sets a currently written RAM group readable flag signal to be 1;
the RAM reading control unit generates a corresponding reading enabling signal and a corresponding reading address signal under the control of the reading counter, so that data in the appointed RAM space is output to the output data channel switching module, and meanwhile, a writable flag signal of the current RAM group is set to be 0; the self-adding step length of the reading counter is 1 every time, the self-adding step length of the reading address signal is 1 every time, the reading counter is cleared and starts to count again after the reading counter reaches a set reading upper limit value, and the reading address signal is cleared and starts to increase again; after the reading counter reaches a set reading upper limit value each time, the reading RAM control unit generates an enabling signal for reading another RAM group and sets a writable flag signal of the current RAM group to be 1;
the asynchronous FIFO is used for data transmission across clock domains, the bit width of a data input end of the asynchronous FIFO is equal to the sum of bit widths of data outputs of all RAM blocks in a single RAM group, and the bit width of a data output end of the asynchronous FIFO is equal to 8 times of the bit width of the data output of the single RAM block;
the output driver writes the data read from the asynchronous FIFO into the DDR SDRAM, and the increment of the initial address of the data read from the two RAM groups written into the DDR SDRAM is equal to the number of RAM blocks in each RAM group; data at the same address in a single RAM bank is written to an adjacent address in the DDR SDRAM, and the number of address increments for writing data at the adjacent address to the DDR SDRAM is equal to the column length of the input data.
Further, the data input interface inputs data in a row sequence.
Further, the number of the RAM blocks in the first RAM group and the second RAM group is an integral multiple of 8, the data input bit width of each RAM block is equal to the bit width of the input data, and the depth is equal to the line length of the input data.
Further, the first writing upper limit value is equal to the depth of the RAM blocks, the second writing upper limit value is equal to the number of the RAM blocks in each group of the RAM, and the reading upper limit value is equal to the depth of the RAM blocks.
The invention has the advantages that the data can be written into the DDR SDRAM by using the burst transmission technology of the DDR SDRAM, the efficiency of writing the row data into the DDR SDRAM can be improved by increasing the number of RAM blocks, and the transposed column data addresses are continuous, so that the transposed column data can be read out at the fastest speed, and the system has simple address calculation mode for accessing the DDR SDRAM, good stability and portability.
Drawings
FIG. 1 is a block diagram of an implementation of a DDR SDRAM based SAR imaging data transpose processing system of the present invention;
FIG. 2 shows a matrix data arrangement and a data reading sequence to be transposed in the present invention;
FIG. 3 is a diagram showing the data arrangement of the matrix data to be transposed in two sets of RAMs according to the present invention;
FIG. 4 is a sequence of reading data in two sets of RAMs in accordance with the present invention;
FIG. 5 shows the arrangement of the transposed data in DDR SDRAM.
Detailed Description
The technical scheme of the invention is explained in detail in the following with the accompanying drawings.
As shown in fig. 1, the SAR imaging data transpose processing system based on DDR SDRAM of the present invention includes a data input interface, an input data channel switching, a write RAM control unit, a read RAM control unit, a first RAM bank, a second RAM bank, an output data channel switching, an asynchronous FIFO, an output driver, and DDR SDRAM.
Except DDR SDRAM, other modules are all realized on an FPGA, and the FPGA selects an xcku040-ffva1156-2-e chip of XILINX company. The DDR SDRAM chip is MT40A256M16HA-083E of Micron company, is DDR4SDRAM, and the burst transmission length is set to be 8. Vivado 2018.3 with a development environment of XILINX, and a DDR SDRAM read-write interface uses an MIG core provided by Vivado.
In this specific embodiment, the size of the matrix to be transposed is 4096, two sets of RAMs are provided, each set having 16 RAM blocks, and the addressing space of each RAM block being 4096.
The function and the working principle of each module of the invention are as follows:
the input data is sent to the input data buses of all the RAM blocks on the first RAM group through the input data channel switching module in a row sequence.
The write RAM control unit sets the readable flag signal of the first RAM group to 0, and then enables the write function of the RAM block 1 in the first RAM group, the first write counter self-increments by 1 every time data is written, and the write address signal self-increments by 1. When the first write counter reaches the set first write upper limit value, namely is equal to 4096, the write RAM control unit closes the write function of the RAM block 1 in the first RAM group, opens the write function of the RAM block 2 in the first RAM group, clears the first write counter, clears the write address signal, and writes data into the RAM block 2 of the first RAM group in sequence.
And sequentially writing data into other RAM blocks in the first RAM group, and adding 1 to the second write counter when one RAM block is fully written. Until all the RAM blocks in the first RAM group are full, at which time the first write counter equals 4096 and the second write counter equals 16. At this time, the readable flag signal of the first RAM group is set to 1.
The write RAM control unit turns off the write function of the RAM block 16 in the first RAM group, sets the readable flag signal of the second RAM group to 0, turns on the write function of the RAM block 1 in the second RAM group, and sequentially writes data into the RAM block 1 of the second RAM group. And writing data into the second RAM group according to the method for writing the first RAM group until the second RAM group is full, and setting the readable mark of the second RAM group to be 1.
The read RAM control unit sets the writable signal flag of the first RAM group to 0 after the write RAM control unit sets the readable flag signal of the first RAM group to 1, and starts sequentially reading data from the first RAM group.
The read RAM control unit enables read enablement of all RAM blocks in the first RAM group, and sequentially reads out data at the same address of all RAM blocks in the first RAM group in sequence by read address signals connected to all RAM blocks in the first RAM group.
First, 16 data with the position of 0 in 16 RAM blocks in a first RAM group are read out, the initial address written into the DDR SDRAM is 0, and the 16 data have continuous addresses in the DDR SDRAM. Then 16 data with address 1 are read out, the address increment for writing into DDR SDRAM is equal to input data line length 4096, 16 data are address-consecutive in DDR SDRAM.
Every time data is read out, the reading counter is automatically added with 1, and the reading address signal is automatically added with 1.
When the reading of all the data of the first RAM group is finished, the reading counter reaches a set reading upper limit value 4096 at the moment, and the reading RAM control unit sets the writable signal mark of the first RAM group to 1.
The read RAM control unit sets the writable signal flag of the second RAM group to 0 after the write RAM control unit sets the readable flag signal of the second RAM group to 1, and starts sequentially reading data from the second RAM group.
The method of reading data from the second RAM bank for writing to the DDR SDRAM is the same as the method of reading data from the first RAM bank for writing to the DDR SDRAM, except that the starting address of the 16 data having a RAM block address of 0 in the second RAM bank for writing to the DDR SDRAM is increased by a fixed value of 16, which is equal to the number of RAM blocks in a single RAM bank, compared to the first RAM bank.
The data writing of each group of the RAMs is completed by one writing cycle, the data reading of each group of the RAMs is completed by one reading cycle, and the reading and writing cycles are circularly performed in sequence.
Claims (4)
1. A SAR imaging data transposition processing system based on DDR SDRAM is characterized by comprising a data input interface, an input data channel switching module, a write RAM control unit, a read RAM control unit, a first RAM group, a second RAM group, an output data channel switching module, an asynchronous FIFO, an output driver and DDR SDRAM; the first RAM group and the second RAM group are respectively provided with N independent RAM blocks, the data input bit widths and the depths of all the RAM blocks are the same, and each RAM block is provided with an independent write enable signal input port, a write address signal input port, a write data input bus, a read enable signal input port, a read address signal input port and a read data output bus; the write RAM control unit is internally provided with two counters, namely a first write counter and a second write counter, and the read RAM control unit is internally provided with a read counter;
the output end of the data input interface is connected with the input end of the input data channel switching module, the write data input buses of the first RAM group and the second RAM group are connected with the output end of the input data channel switching module, the write enable ports of the first RAM group and the second RAM group are connected with the enable signal output port of the write RAM control unit, and the write address ports of the first RAM group and the second RAM group are connected with the address signal output port of the write RAM control unit; the read data output buses of the first RAM group and the second RAM group are connected with the input end of the output data channel switching module, the read enabling ports of the first RAM group and the second RAM group are connected with the enabling signal output port of the read RAM control unit, and the read address ports of the first RAM group and the second RAM group are connected with the address signal output port of the read RAM control unit; the RAM group readable mark signal output port of the write RAM control unit is connected to the readable mark signal input port of the read RAM control unit; the RAM group writable mark signal output port of the read RAM control unit is connected to the writable mark signal input port of the write RAM control unit; the output end of the output data channel switching module is connected with the input end of the asynchronous FIFO; the output end of the asynchronous FIFO is connected to the input end of an output driver, and the output end of the output driver is connected to a user interface of the DDR SDRAM;
the input data channel switching module is used for selecting a data path between data input to the RAM group; the output data channel switching module is used for selecting a data path from the RAM group to the asynchronous FIFO;
the write RAM control unit generates corresponding write enable signals and corresponding write address signals under the control of the first write counter and the second write counter, so that input data are written into the first RAM group or the second RAM group, and meanwhile, a currently written RAM group readable mark signal is set to be 0; the self-adding step length of the first write counter is 1 each time, the self-adding of 1 of the write address signal is performed each time, the first write counter is cleared and starts to count again after the first write counter reaches a set first write upper limit value, and the write address signal is cleared and starts to increase again; after the first write counter reaches a set first write upper limit value each time, the write RAM control unit generates an enable signal for writing the next RAM block; after the first write counter reaches a set first write upper limit value each time, the second write counter is added by 1, and after the set second write upper limit value is reached, the second write counter is reset and starts counting again; after the first write counter reaches a set first write upper limit value and the second write counter reaches a set second write upper limit value, the write RAM control unit generates an enable signal for writing a first RAM block of another RAM group and sets a currently written RAM group readable flag signal to be 1;
the RAM reading control unit generates a corresponding reading enabling signal and a corresponding reading address signal under the control of the reading counter, so that data in a specified RAM space is output to the output data channel switching module, and meanwhile, a writable flag signal of the current RAM group is set to be 0; the self-adding step length of the reading counter is 1 every time, the self-adding step length of the reading address signal is 1 every time, the reading counter is cleared and starts to count again after the reading counter reaches a set reading upper limit value, and the reading address signal is cleared and starts to increase again; after the reading counter reaches a set reading upper limit value each time, the reading RAM control unit generates an enabling signal for reading another RAM group and sets a writable flag signal of the current RAM group to be 1;
the asynchronous FIFO is used for data transmission across clock domains, the bit width of a data input end of the asynchronous FIFO is equal to the sum of bit widths of data outputs of all RAM blocks in a single RAM group, and the bit width of a data output end of the asynchronous FIFO is equal to 8 times of the bit width of the data output of the single RAM block;
the output driver writes the data read out from the asynchronous FIFO into the DDR SDRAM, and the increment of the initial address of the data read out from the two RAM groups written into the DDR SDRAM is equal to the number of RAM blocks in each RAM group; data at the same address in a single RAM bank is written to an adjacent address in the DDR SDRAM, and the number of address increments for writing data at the adjacent address to the DDR SDRAM is equal to the column length of the input data.
2. The SAR imaging data transpose processing system based on DDR SDRAM of claim 1, wherein the data input interface input data is input in row order.
3. The SAR imaging data transposition processing system based on DDR SDRAM is characterized in that the number of RAM blocks in the first RAM group and the second RAM group is integral multiple of 8, the data input bit width of each RAM block is equal to the bit width of input data, and the depth is equal to the line length of the input data.
4. The SAR imaging data transpose processing system based on DDR SDRAM, as recited in claim 1, wherein the first write ceiling is equal to the depth of the RAM blocks, the second write ceiling is equal to the number of RAM blocks in each set of RAM, and the read ceiling is equal to the depth of the RAM blocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110834387.0A CN113555051B (en) | 2021-07-23 | 2021-07-23 | SAR imaging data transposition processing system based on DDR SDRAM |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110834387.0A CN113555051B (en) | 2021-07-23 | 2021-07-23 | SAR imaging data transposition processing system based on DDR SDRAM |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113555051A CN113555051A (en) | 2021-10-26 |
| CN113555051B true CN113555051B (en) | 2023-04-07 |
Family
ID=78104210
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110834387.0A Active CN113555051B (en) | 2021-07-23 | 2021-07-23 | SAR imaging data transposition processing system based on DDR SDRAM |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113555051B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201465279U (en) * | 2009-06-04 | 2010-05-12 | 西南科技大学 | Wireless multi-channel vibration data synchronous acquisition system supplied with power by battery |
| CN102279386A (en) * | 2011-05-12 | 2011-12-14 | 西安电子科技大学 | SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) |
| CN102298139A (en) * | 2011-05-18 | 2011-12-28 | 中国科学院计算技术研究所 | Two-dimensional windowing method of synthetic aperture radar (SAR) imaging system based on field programmable gate array (FPGA) |
| CN103760525A (en) * | 2014-01-06 | 2014-04-30 | 合肥工业大学 | Completion type in-place matrix transposition method |
| CN103885727A (en) * | 2014-04-02 | 2014-06-25 | 清华大学 | Real-time transposition processing method and system for synthetic aperture radar |
| CN106021182A (en) * | 2016-05-17 | 2016-10-12 | 华中科技大学 | Line transpose architecture design method based on two-dimensional FFT (Fast Fourier Transform) processor |
| CN111707992A (en) * | 2019-03-15 | 2020-09-25 | 菲力尔安全公司 | Radar data processing system and method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8856464B2 (en) * | 2008-02-12 | 2014-10-07 | Virident Systems, Inc. | Systems for two-dimensional main memory including memory modules with read-writeable non-volatile memory devices |
| KR102273153B1 (en) * | 2019-04-24 | 2021-07-05 | 경희대학교 산학협력단 | Memory controller storing data in approximate momory device based on priority-based ecc, non-transitory computer-readable medium storing program code, and electronic device comprising approximate momory device and memory controller |
-
2021
- 2021-07-23 CN CN202110834387.0A patent/CN113555051B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201465279U (en) * | 2009-06-04 | 2010-05-12 | 西南科技大学 | Wireless multi-channel vibration data synchronous acquisition system supplied with power by battery |
| CN102279386A (en) * | 2011-05-12 | 2011-12-14 | 西安电子科技大学 | SAR (Synthetic Aperture Radar) imaging signal processing data transposing method based on FPGA (Field Programmable Gata Array) |
| CN102298139A (en) * | 2011-05-18 | 2011-12-28 | 中国科学院计算技术研究所 | Two-dimensional windowing method of synthetic aperture radar (SAR) imaging system based on field programmable gate array (FPGA) |
| CN103760525A (en) * | 2014-01-06 | 2014-04-30 | 合肥工业大学 | Completion type in-place matrix transposition method |
| CN103885727A (en) * | 2014-04-02 | 2014-06-25 | 清华大学 | Real-time transposition processing method and system for synthetic aperture radar |
| CN106021182A (en) * | 2016-05-17 | 2016-10-12 | 华中科技大学 | Line transpose architecture design method based on two-dimensional FFT (Fast Fourier Transform) processor |
| CN111707992A (en) * | 2019-03-15 | 2020-09-25 | 菲力尔安全公司 | Radar data processing system and method |
Non-Patent Citations (3)
| Title |
|---|
| Huanghui Shen等.Corner turn of SAR data based on multi-FPGAs parallel system.《ELSEVIER》.2012,1205-1212. * |
| 胡国光 等.基于多DSP芯片的实时SAR雷达转角变换模块设计.《航空电子技术》.2009,43-46. * |
| 闵锐.高分辨力机载SAR成像处理研究.《中国优秀硕士论文电子期刊网 信息科技辑》.2004,I136-238. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113555051A (en) | 2021-10-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101231877B (en) | N-port memory and method for accessing n-port memory M memory address | |
| CN101236774B (en) | Device and method for single-port memory to realize the multi-port storage function | |
| CN113641625B (en) | Four-way parallel data processing transposition system based on FPGA | |
| CN108053855B (en) | Matrix transposition method based on SDRAM chip | |
| CN102541749B (en) | Multi-granularity parallel storage system | |
| CN106846255B (en) | Image rotation realization method and device | |
| CN103760525A (en) | Completion type in-place matrix transposition method | |
| CN101154433A (en) | Memory systems and methods of operating the memory systems | |
| CN108169716B (en) | SAR imaging system matrix transposition device based on SDRAM chip and pattern interleaving method | |
| CN102004626B (en) | Dual-port memory | |
| CN101645305B (en) | Static random access memory (SRAM) for automatically tracking data | |
| CN101825997A (en) | Asynchronous first-in first-out storage | |
| CN110415163A (en) | Data matrix transposition method and device for SAR imaging | |
| CN113555051B (en) | SAR imaging data transposition processing system based on DDR SDRAM | |
| CN114626005B (en) | FPGA (field programmable Gate array) implementation method of CS (circuit switched) algorithm in video SAR (synthetic aperture radar) real-time imaging | |
| CN100568382C (en) | Push-up storage | |
| CN105577985A (en) | Digital image processing system | |
| CN111966628B (en) | Multi-core combined type large-capacity data synchronous storage method | |
| CN113740851B (en) | SAR imaging data processing system of time-sharing multiplexing single DDR | |
| CN201859658U (en) | Embedded SDRAM (synchronous dynamic random access memory) module | |
| KR100343831B1 (en) | Semiconductor memory | |
| CN107293318B (en) | Bit width configurable embedded memory | |
| CN115113820A (en) | System and method for realizing multi-target long-delay DRFM storage component | |
| CN101813971B (en) | Processor and internal memory thereof | |
| JP5499131B2 (en) | Dual port memory and method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |