KR102273153B1 - Memory controller storing data in approximate momory device based on priority-based ecc, non-transitory computer-readable medium storing program code, and electronic device comprising approximate momory device and memory controller - Google Patents

Abstract

The memory controller according to an embodiment of the present invention converts some bits of the first data into parity bits for an error correction operation, and includes parity bits replaced from some bits and the remaining bits of the first data. an error correction circuit configured to generate data, and a physical layer configured to transmit second data in place of the first data to the memory device.

Description

A memory controller for storing data in an approximate memory device based on priority-based ECC, a non-transitory computer readable medium for storing program code, and an electronic device including an approximate memory device and a memory controller IN APPROXIMATE MOMORY DEVICE BASED ON PRIORITY-BASED ECC, NON-TRANSITORY COMPUTER-READABLE MEDIUM STORING PROGRAM CODE, AND ELECTRONIC DEVICE COMPRISING APPROXIMATE MOMORY DEVICE AND MEMORY CONTROLLER}

The present invention relates to a memory controller for storing data in an approximate memory device based on priority-based ECC, a non-transitory computer readable medium for storing program codes, and an electronic device including the approximate memory device and the memory controller. will be.

Artificial intelligence technology based on an artificial neural network (ANN) similar to a biological neural network is being used in various fields such as image recognition, speech recognition, translation, search, deep learning, data collection and analysis, and autonomous driving. As the hardware of the computing device develops, a deep neural network (DNN) including a plurality of hidden layers is mainly used.

In learning, training, or inference of a neural network, multiple parameters may be created, referenced, or updated. As these parameters increase, the capacity, number, and density of memory devices for storing parameters also increase. Therefore, it is necessary to reduce the power consumption of the memory device required to execute the neural network.

The present invention is to solve the above technical problem, the present invention is a memory controller for storing data in an approximate memory device based on priority-based ECC, a non-transitory computer-readable medium for storing a program code, and an approximate An electronic device including an external memory device and a memory controller may be provided.

The memory controller according to an embodiment of the present invention converts some bits of the first data into parity bits for an error correction operation, and includes parity bits replaced from some bits and the remaining bits of the first data. an error correction circuit configured to generate data, and a physical layer configured to transmit second data in place of the first data to the memory device.

In a non-transitory computer-readable medium including a program code according to another embodiment of the present invention, when the program code is executed by a processor, the processor converts some bits of the first data into parity bits for an error correction operation and generating second data including parity bits in which some bits have been replaced and remaining bits of the first data, and generating a write command for storing the second data in the memory device.

An electronic device according to another embodiment of the present invention includes a processor configured to generate first data, convert some bits of the first data into parity bits for an error correction operation, and replace some bits with parity bits a memory controller configured to generate second data including the remaining bits of the first data; and a memory device configured to store second data transmitted from the memory controller.

The memory controller according to an embodiment of the present invention may store data in the approximate memory device based on the priority ECC. The memory controller may reduce refresh power consumption of the approximate memory device. The memory controller may adjust the approximate refresh rate of the memory device according to the BER, and may correct errors that may occur in the memory device operating at a low refresh rate using priority ECC.

1 illustrates an exemplary block diagram of an electronic device according to an embodiment of the present invention.
FIG. 2A illustrates an example in which the first data of FIG. 1 is converted into second data.
FIG. 2B shows exemplary values of some bits of the first data of FIG. 1 .
FIG. 2C illustrates another example in which the first data of FIG. 1 is converted into second data.
FIG. 3 shows an exemplary block diagram of the electronic device of FIG. 1 in more detail.
4 illustrates an example in which the second data of FIG. 3 is stored in a bank of a memory device.
FIG. 5 is an exemplary flowchart for the memory controller of FIG. 3 to store second data in a memory device.
6 is an exemplary flowchart for the memory controller of FIG. 3 to adjust an error zone and an error-free zone of the memory device.
FIG. 7 shows an exemplary flowchart for adjusting a refresh rate by the memory controller of FIG. 3 according to temperature and BER.
8 shows an example of a lookup table showing the relationship between BER and refresh.
FIG. 9 is an exemplary flowchart for the memory device of FIG. 3 to perform a refresh command.
10 is a more detailed exemplary block diagram of the electronic device of FIG. 1 according to another embodiment of the present invention.
11 illustrates an example in which the second data of FIG. 10 is stored in a bank of a memory device.
12 illustrates the memory device of FIG. 1 according to an embodiment of the present invention.
13 illustrates the memory device of FIG. 1 according to another embodiment of the present invention.
14 is an exemplary block diagram of an electronic device according to another embodiment of the present invention.
15 is an exemplary flowchart illustrating an operation method of the memory controller of FIG. 14 .
16 is an exemplary block diagram of an electronic device according to another embodiment of the present invention.

1 illustrates an exemplary block diagram of an electronic device according to an embodiment of the present invention. The electronic device 100 may also be referred to as an electronic system, a computer system, a memory system, or the like. For example, the electronic device 100 may be a desktop computer, a laptop computer, a workstation, a server, a mobile device, etc., but the scope of the present invention is not limited thereto. The electronic device 100 may include a memory controller 110 and a memory device 130 .

The memory controller 110 may control the memory device 130 . The memory controller 110 may generate commands and addresses for accessing the memory device 130 . The memory controller 110 may generate data to be stored in the memory device 130 . The memory controller 110 may receive data stored in the memory device 130 .

The memory controller 110 may include an error correction circuit 111 and a physical layer 112 (hereinafter, referred to as a PHY). The error correction circuit 111 may receive the first data. The first data may be provided from outside the memory controller 110 (eg, a processor, a buffer memory, etc.) or may be generated inside the memory controller 110 . The first data may be data to be stored in the memory device 130 . For example, the first data may be generated as the application program is executed or may be required to execute the application program.

The error correction circuit 111 may perform an encoding operation on write data (first data) to be stored in the memory device 130 . The error correction circuit 110 may perform a decoding operation on read data transmitted from the memory device 130 . For example, the error correction circuit 111 may generate parity bits for write data. The error correction circuit 111 may correct an error of the read data using parity bits of the read data transmitted from the memory device 130 . Errors in read data may occur due to various factors of the memory device 130 such as PVT (process, voltage, temperature) fluctuations, retention characteristics, interference, deterioration, noise, refresh rate, density, etc. can

More specifically, the error correction circuit 111 may generate parity bits for the first data based on the error correction code ECC. The parity bits may be used to protect the message bits of the first data from being corrupted. Unlike encoding using a general error correction code (ECC), the error correction circuit 111 according to an embodiment of the present invention does not add parity bits to the message bits of the first data. Instead, the error correction circuit 111 may replace some bits of the message bits of the first data with parity bits. The error correction circuit 111 may convert some bits of the message bits of the first data into parity bits for an error correction operation. The error correction circuit 111 may generate second data including parity bits and the remaining bits of the message bits of the first data.

As described above, since the error correction circuit 111 converts some bits into parity bits without adding parity bits to the message bits of the first data, the size (number of bits) of the first data and the size of the second data are may be identical to each other. The error correction circuit 111 may convert the first data into second data and provide the second data to the PHY 112 . The memory device 130 stores second data in which the first data is encoded based on the control of the memory controller 110 . Some bits of the message bits replaced with parity bits are not stored in the memory device 130 .

PHY 112 may also be referred to as an interface circuit. PHY 112 may communicate directly with memory device 130 . The PHY 112 is an interface standard supported by the memory device 130 (eg, Toggle double data rate (DDR) standard, DDR SDRAM (synchronous dynamic random access memory) standard, joint electron device engineering council (JEDEC) standard, etc. ) can be operated according to The PHY 112 may drive physical paths forming a channel between the memory controller 110 and the memory device 130 . The PHY 112 may transmit a command, an address, and write data (second data) generated by the memory controller 110 to the memory device 130 . The PHY 112 may receive read data from the memory device 130 and may provide the received read data to the error correction circuit 111 . Referring to FIG. 1 , the PHY 112 may transmit second data converted and generated by the error correction circuit 111 to the memory device 130 as it is. The PHY 112 may transmit second data other than the first data to the memory device 130 .

The memory device 130 may store write data transmitted from the memory controller 110 based on the control of the memory controller 110 . The memory device 130 may transmit stored data to the memory controller 110 as read data based on the control of the memory controller 110 . For example, the memory device 130 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a thyristor random access memory (TRAM) device, a NAND flash memory device, a NOR flash memory device, or a resistive RAM (RRAM) device. random access memory) device, ferroelectric random access memory (FRAM) device, phase change random access memory (PRAM) device, magnetic random access memory (MRAM) device, spin transfer torque magnetic random access memory (STT-MRAM) device, solid state It may be a drive (SSD), a memory card, a universal flash storage device (UFS), or the like, but the memory device 130 is not limited thereto.

Referring to FIG. 1 , the memory device 130 may receive and store second data from the memory controller 110 . If the memory device 130 is a DRAM device, the data stored in the memory cell of the memory device 130, that is, the amount of time the charge is maintained is limited, so refreshing the data stored in the memory cell before the data stored in the memory cell is lost. need. For example, the memory device 130 may periodically or aperiodically refresh the second data in response to the repetitive auto-refresh request of the memory controller 110 . As another example, the memory device 130 may periodically or aperiodically refresh the second data by itself in response to the self-refresh request of the memory controller 110 . The memory device 130 may perform a refresh operation on data stored in all DRAM cells as well as the second data illustrated in FIG. 1 .

As the capacity, number, and degree of integration of the memory device 130 increases, power required for the memory device 130 to perform a refresh operation (eg, IDD5, IDD6, etc.) also increases. When the electronic device 100 executes an artificial neural network (application program) such as a deep neural network, power consumption of the memory device 130 by the refresh operation may significantly increase. For example, the artificial neural network executed by the electronic device 100 may include a deep neural network (DNN), a convolution neural network (CNN), a recurrent neural network (RNN), a spiking neural network (SNN), and the like.

In order to reduce power consumption of the memory device 130 , the memory controller 110 may lower the refresh rate of the memory device 130 and operate the memory device 130 as an approximate memory device. The memory controller 110 may improve power consumption of the memory device 130 by the refresh operation by lowering the refresh rate of the memory device 130 .

A slow refresh rate may cause loss of data stored in memory cells. A slow refresh rate may cause an increase in a bit error rate (BER) of the memory device 130 and may affect the accuracy of calculation of an application program executed using the electronic device 100 . Nevertheless, the memory controller 110 may allow a probability that an error will occur in the memory device 130 due to a slow refresh rate. For example, the memory controller 110 may use a priority-based ECC so that the BER of the memory device 130 operating at a slow refresh rate does not affect the accuracy of calculation of the application program. .

Before storing the first data in the memory device 130 , the memory controller 110 encodes the first data using the priority-based ECC and transmits the first data-encoded second data to the memory device 130 . can be saved The error correction circuit 111 of the memory controller 110 may replace some bits of the first data with parity bits. A priority, ie, a criterion, in which the error correction circuit 111 selects some bits to be replaced with parity bits may be the significance of each of the bits. The error correction circuit 111 may replace some insignificant bits with parity bits. The error correction circuit 111 may protect the remaining important bits from errors using the parity bits.

Whether the memory controller 110 can effectively use the memory device 130 as an approximate memory depends on how important bits of data and non-significant bits are separated, that is, which bits of data. Depends on whether to replace with parity bit. Examples in which some bits of the message bits are replaced with parity bits by the error correction circuit 111 will be described in more detail with reference to FIGS. 2A to 2C .

FIG. 2A illustrates an example in which the first data of FIG. 1 is converted into second data. FIG. 2B shows exemplary values of some bits of the first data of FIG. 1 . 2A and 2B will be described together with reference to FIG. 1 .

The first data Data 1 may be expressed in, for example, a floating-point format specified by IEEE 754. Message bits of the first data expressed in the floating-point format may be divided into sign bits, exponent bits, and mantissa or fraction bits. For example, floating-point formats include half-precision floating-point format, single-precision floating-point format, double-precision floating-point format, and double-precision floating-point format. extended-precision floating-point formats, quadruple-precision floating-point formats, and the like.

Referring to FIG. 2A , the first data may be expressed in a single-precision floating-point format and the number of bits of the first data may be 32, but is not limited thereto. The message bits of the first data may include 1 sign bit s, 8 exponent bits e, and 23 mantissa bits m. The value of the floating-point format {s, e, m} may be ^{-1 s} XMX 2 ^E. Here, M=1.m and E=e-127. A sign bit of the first data may be a most significant bit (MSB), and a rightmost bit among mantissa bits may be a least significant bit (LSB). Bits of the first data disposed on the relatively left may be more important than bits of the first data disposed on the relatively right side. The priority (ie, order) from MSB to LSB is the sign bit, the exponent bits, the upper bits of the mantissa, and the lower bits of the mantissa.

The values of the upper bits ([31:24]) among the bits of the first data are illustrated in FIG. 2B by way of example. The horizontal axis represents the bit position and the vertical axis represents the ratio of bit 1 to bit 0. For example, the first data of FIGS. 2A and 2B may be data to be stored in the memory device 130 as a neural network such as DNN, CNN, RNN, SNN, etc. is executed using the electronic device 100 and the neural network may be weight parameters of . The first data may be used for calculation of the neural network. For example, the range of the weight parameters may be [2 ^-13 :2 ^{- 2} ]. According to the above-described range, values of some bits of the first data ([30, 29, 28]) may be fixed to [0, 1, 1].

Some bits of the first data ([30, 29, 28]) are message bits constituting the first data. However, since the values of some bits ([30, 29, 28]) of the first data are fixed to [0, 1, 1] in the error correction circuit 111, some bits ( [30, 29, 28]) can be replaced (converted) with parity bits. The error correction circuit 111 may generate second data Data 2 including the remaining bits [31, 27:0] of the first data and parity bits. The positions of the parity bits of the second data may correspond to positions of the bits [30, 29, 28] of the first data, respectively. Values of the message bits [31, 27:0] of the second data may be the same as values of the message bits [31, 27:0] of the first data. The positions of the message bits [31, 27:0] of the second data may correspond to positions of the message bits [31, 27:0] of the first data, respectively. However, the positions of the message bits and the parity bits of the second data are not limited to those illustrated in FIG. 2A .

The error correction circuit 111 may receive and decode the second data read from the memory device 130 after the second data is stored in the memory device 130 . The second data read from the memory device 130 may be the same as the second data transmitted by the PHY 112 to the memory device 130 or may be different due to an error. The error correction circuit 111 may perform an error correction operation on the bits [31, 27, 26, and 25] of the second data using the parity bits. The error correction circuit 111 replaces some bits [30, 29, 28] having fixed values with parity bits, and then the parity bits are stored in the memory device 130 instead of the fixed values and , then the error correction circuit 111 may perform an error correction operation using the parity bits. The error correction circuit 111 may use the values of the bits of the second data ([30, 29, 28]) in an error correction operation and then set, change, or correct them to [0, 1, 1]. .

The error correction circuit 111 makes the remaining bits ([31, 27, 26, 25]) of the first data an error by replacing some bits ([30, 29, 28]) of the first data with parity bits. can be protected from The error correction circuit 111 may select the remaining bits to be protected using the parity bits according to the priority of the bits, that is, their importance. For example, the error correction circuit 111 selects the remaining bits ([31, 27, 26, 25]) from all remaining bits ([31, 27:0]) according to the order of the LSB in the MSB, and selects the parity It can be protected using bits. The positions of the remaining bits to be protected using the parity bits are not limited to those shown in FIG. 2A .

In an embodiment, positions of bits having a fixed value among bits of the first data are not limited to those described with reference to FIGS. 2A and 2B . A position of a bit having a fixed value may vary according to a type of an application program executed using the electronic device 100 , a type of data generated by the application program, a range of data values, and the like.

In an embodiment, the number of bits having a fixed value among the bits of the first data is not limited to those described with reference to FIGS. 2A and 2B . As the number of bits having a fixed value increases, the number of remaining message bits that the error correction circuit 110 can protect may also increase. The number of correctable errors may also be changed according to the type of error correction code used by the error correction circuit 110 . 2A and 2B , the error correction code may be a Hamming code. The error correction circuit 110 may protect the four message bits [31, 27, 26, 25] using the three parity bits [30, 29, 28]. For example, 2 ^k -1 ≥ n+k may hold, where n is the number of message bits and k is the number of parity bits. The error correction circuit 110 may use other error correction codes such as a Bose-Chauduhuri-Hocquenghen (BCH) code, a Reed-Solomon (RS) code, a Viterbi code, a Turbo code, and a low density parity check (LDPC) as well as a Hamming code. may be

FIG. 2C illustrates another example in which the first data of FIG. 1 is converted into second data. FIG. 2C will be described with reference to FIG. 1 . Like FIG. 2A , in FIG. 2C , the first data may be expressed in a single-precision floating-point format, and the number of bits of the first data may be 32. As described above, the bits of the first data arranged on the relatively left side may be more important than the bits of the first data arranged on the relatively right side.

For example, the error correction circuit 111 may replace unimportant low-order bits ([3:0]) of the first data with parity bits. The lower bits ([3:0]) of the first data are message bits constituting the first data. The error correction circuit 111 may generate second data Data 2 including the remaining bits [31:4] of the first data and parity bits. The positions of the parity bits of the second data may respectively correspond to positions of the bits ([3:0]) of the first data. Values of the message bits [31:4] of the second data may be the same as values of the message bits [31:4] of the first data. The positions of the message bits [31:4] of the second data may correspond to positions of the message bits [31:4] of the first data, respectively. However, the positions of the message bits and the parity bits of the second data are not limited to those illustrated in FIG. 2C .

The error correction circuit 111 may receive and decode the second data read from the memory device 130 after the second data is stored in the memory device 130 . The error correction circuit 111 may perform an error correction operation on bits [31:23] of the second data using parity bits. That is, the error correction circuit 111 replaces the lower bits ([3:0]) with parity bits, and then parity bits are replaced with the original values of the lower bits ([3:0]) in the memory device ( 130), and then the error correction circuit 111 may perform an error correction operation using the parity bits.

The error correction circuit 111 may protect the remaining bits ([31:23]) of the first data from errors by replacing the lower bits ([3:0]) of the first data with parity bits. As described above, the error correction circuit 111 may select the remaining bits to be protected using the parity bits according to the priority of the bits, that is, their importance. For example, the error correction circuit 111 selects the remaining bits ([31:23]) from all remaining bits ([31:4]) according to the order of the LSBs in the MSB and protects them using the parity bits. can Here, the positions and the number of lower bits that the error correction circuit 111 replaces with the parity bits, and the positions and the number of message bits to be protected using the parity bits are not limited to those shown in FIG. 2C .

FIG. 3 shows an exemplary block diagram of the electronic device of FIG. 1 in more detail. As described above, the electronic device 100 may include the memory controller 110 and the memory device 130 .

The memory controller 110 includes an error correction circuit 111 , a PHY 112 , a data queue 113 , a request queue 114 , a command generator 115 , a refresh command generator 116 , a multiplexer 117 , and registers. 118 , and a temperature check circuit 119 . The error correction circuit 111 and the PHY 112 have been described with reference to FIGS. 1 and 2A to 2C.

The data queue 113 may store write data to be stored in the memory device 130 . The data queue 113 may provide the stored write data to the error correction circuit 111 . After the read data is transmitted from the memory device 130 and the error correction circuit 111 performs decoding on the read data, the data queue 113 may receive and store the decoded data from the error correction circuit 111 . have.

The request queue 114 may store instructions and addresses issued by a processor (not shown, see 3120 of FIG. 14 ). The request queue 114 may provide the stored commands and addresses to the command generator 115 . In an embodiment, regions for the data queue 113 and the request queue 114 may be allocated in advance in an on-chip memory, that is, a buffer memory, located in a circuit in which the memory controller 110 is implemented. For example, the data queue 113 and the request queue 114 may be implemented in the memory controller 110 using registers, flip-flops, latches, an SRAM device, and the like. As another example, the data queue 113 and the request queue 114 may be implemented on a memory device located outside the memory controller 110 .

The command generator 115 may generate a command or an address to be provided to the memory device 130 . For example, the command may include an activation command, a read command, a write command, a precharge command, an erase command, and the like. The address may indicate a location where data is to be stored in the memory device 130 or may indicate a location of data stored in the memory device 130 . The refresh command generator 116 periodically or aperiodically generates a refresh command to be provided to the memory device 130 in order to maintain data stored in the memory device 130 separately from requests input to the request queue 114 . can do. The refresh command generator 116 may include a counter for counting when to issue a refresh command. The multiplexer 117 may provide either the command generated by the command generator 115 or the command generated by the refresh command generator 116 to the PHY 112 . 3 , the refresh instruction generator 116 and the multiplexer 117 may be implemented in the instruction generator 115 and the instruction generator 115 may generate the refresh instruction.

Registers 118 may store a lookup table (LUT). For example, the lookup table (LUT) may store mapping information between the BER and the refresh rate. The registers 118 may be included in an on-chip memory located in a circuit in which the memory controller 110 is implemented. The temperature check circuit 119 may check the current temperature of the memory device 130 through the PHY 112 . The temperature check circuit 119 provides information for adjusting the refresh rate of the memory device 130 to the command generator 115 based on the lookup table stored in the registers 118 and the current temperature of the memory device 130 . can The refresh command generator 116 may adjust or control the refresh rate of the memory device 130 based on the control of the command generator 115 . For example, the refresh command generator 116 may adjust the cycle for generating the refresh command.

1 , the PHY 112 may receive the second data and transmit the second data to the memory device 130 . The PHY 112 may drive the DQ signals so that bits of the second data are transmitted through the DQ signals (data input/output signals). The PHY 112 may receive read data transmitted from the memory device 130 , that is, logical values of DQ signals according to the read data. The PHY 112 may transmit the command CMD and the address ADD to the memory device 130 according to the command and the address generated by the command generator 115 . The PHY 112 may transmit a command CMD to the memory device 130 according to the refresh command generated by the refresh command generator 116 . PHY 112 may drive command signals or address signals. Logic values of command signals and address signals (ACT_n, RAS_n, CAS_n, WE_n, A0-A17, BA0-BA1, BG0-BG1, etc.) may be specified in the JEDEC standard.

For example, all components of the memory controller 110 may be implemented in an integrated circuit in a hardware manner. As another example, the error correction circuit 111 of the memory controller 110 may be implemented in the memory controller 110 using a software method, a hardware method, or a combination thereof.

The memory device 130 includes a command decoder 131 , a refresh controller 132 , an address demultiplexer 133 , a bank 134 , a row decoder 135 , a column decoder 136 , a write circuit 137 , and a read circuit ( 138 ), a DQ buffer 139 , registers 140 , and a temperature sensor 141 . All of the above-described components may be implemented in a hardware manner in the memory device 130 .

The command decoder 131 may decode a command output from the PHY 112 and may control internal components of the memory device 130 . The command decoder 131 may receive and decode a refresh command and then control the refresh controller 132 . The refresh controller 132 may include a first counter 132_1 , a second counter 132_2 , and a multiplexer 132_4 . The refresh controller 132 may control the first counter 132_1 and the second counter 132_2 based on the control of the command decoder 131 . The first counter 132_1 may generate a row address corresponding to an error-free region of the bank 134 . The second counter 132_2 may generate a row address corresponding to an error region of the bank 134 .

In an embodiment, the first counter 132_1 may generate and update a row address corresponding to an error-free region whenever a refresh command is input to the memory device 130 . The refresh controller 132 may trigger the first counter 132_1 whenever a refresh command is input. On the other hand, the second counter 132_2 may generate and update a row address corresponding to the error region in response to only some of the refresh commands input to the memory device 130 . The refresh controller 132 may operate the second counter 132_2 in response to only some of the input refresh commands and may not operate the second counter 132_2 according to the remaining refresh commands. The interval between the times when the row address corresponding to the error-free zone is updated by the first counter 132_1 may be shorter than the interval between the times when the row address corresponding to the error zone is updated by the second counter 132_2 have. The multiplexer 132_4 may provide one of the row address of the first counter 132_1 and the row address of the second counter 132_2 to the row decoder 135 . 3 , the multiplexer 132_4 may provide the row address of the first counter 132_1 and the row address of the second counter 132_2 together to the row decoder 135 .

The address demultiplexer 133 may provide the address ADD received according to a command to internal components of the memory device 130 based on the control of the command decoder 131 . The address demultiplexer 133 may provide an address transmitted from the PHY 112 along with the activation command as a row address to the row decoder 135 . The address demultiplexer 133 may provide an address transmitted from the PHY 112 along with a read command or a write command to the column decoder 136 as a column address. The address demultiplexer 133 may provide the registers 140 with the address received along with the setup command from the PHY 112 as a setup code. The setting code may also be referred to as an operation code (OPCODE) or an operand.

The bank 134 may include an array of memory cells. The bank 134 may be a unit for classifying memory cells of the memory device 130 . The memory cell array may include memory cells connected to word lines and bit lines (not shown). For convenience of illustration in FIG. 3 , the bank 134 is illustrated as one, but the memory device 130 may include one or more banks 134 .

The memory cells of the bank 134 may be divided into an error-free region and an error region. For example, memory cells allocated to the error-free region and memory cells allocated to the error region may be manufactured to be substantially the same. Under the control of the refresh controller 132 , memory cells arranged in the error-free region may be refreshed more frequently than memory cells allocated to the error region. When the bank 134 includes an error zone (ie, when the memory device 130 operates as an approximate memory), the power consumption of the memory device 130 by the refresh operation is The memory device 130 by a refresh operation when cells are allocated to an error-free region (that is, when there is no error region in the bank 134 and the memory device 130 operates as a general memory rather than an approximate memory) less than the power consumption of The difference between the power consumptions described above may increase as the error zone becomes larger than the error-free zone. The BER of data stored in the memory cells disposed in the error region may be higher due to a slower refresh rate than the BER of data stored in the memory cells disposed in the error-free region.

The row decoder 135 may decode the row address RA based on the control of the command decoder 131 . The row decoder 135 may select or activate at least one word line corresponding to the row address. The row decoder 135 receives the row address output from the PHY 112 , the row address generated by the first counter 132_1 , or the row address generated by the second counter 132_2 as the row address RA. can do. For example, the row decoder 135 may receive a row address according to an activation command from the address demultiplexer 133 . The row decoder 135 may receive a row address according to the refresh command from any one of the first and second counters 132_1 and 132_2 .

The row decoder 135 may refresh the memory cells disposed in the error-free region more frequently than the memory cells disposed in the error region based on the control of the command decoder 131 and the refresh controller 132 . A row address indicating at least one of the word lines of the error-free region may be provided to the row decoder 135 more frequently than a row address indicating at least one or more of the word lines of the error region.

In an embodiment, the memory controller 110 may directly generate a row address designating a word line to be activated by an activation command and provide it to the memory device 130 . Unlike the case of generating the activation command, the memory controller 110 may provide only the refresh command to the memory device 130 and may not directly designate a word line to be refreshed. The memory device 130 may include a refresh controller 132 that internally generates a row address indicating a word line to be refreshed in response to a refresh command. The memory device 130 may operate as an approximate memory. The refresh controller 132 includes a first counter 132_1 generating row addresses representing word lines disposed in the error-free area and a second counter 132_2 generating row addresses representing word lines disposed in the error area. may include

The column decoder 136 may decode the column address CA based on the control of the command decoder 131 . The column decoder 136 may select or activate at least one column selection line corresponding to the column address. At least one or more bit lines may be connected to the column selection line. For example, memory cells corresponding to a row address and a column address may be selected, and data input/output may be performed on the selected memory cells. The column decoder 136 may include a write driver (WDRV) and an input/output sense amplifier (IOSA).

The write driver WDRV may receive write data from the write circuit 137 and write the write data to the selected memory cells based on the control of the command decoder 131 . The input/output sense amplifier IOSA may detect read data of the selected memory cells and provide the read data to the read circuit 138 .

The write circuit 137 may receive and parallelize bits of write data included in DQ signals transmitted from the PHY 112 through the DQ buffer 139 . The write circuit 137 may provide write data to the write driver WDRV. The read circuit 138 may receive and serialize read data from the input/output sense amplifier IOSA. The read circuit 138 may provide read data to the DQ buffer 139 . DQ buffer 139 may receive DQ signals from PHY 112 or output DQ signals to PHY 112 . Since DQ signals are bidirectional signals, the DQ buffer 139 may include both a receiver (not shown) and a transmitter (not shown).

The registers 140 may store a setting code, ie, setting information, provided from the address demultiplexer 133 based on the control of the command decoder 131 . Registers 140 may be referred to as mode registers, general purpose registers, etc., for example. The memory controller 110 may change values stored in the registers 140 and set or adjust an operating condition, an operating mode, etc. of the memory device 130 .

The temperature sensor 141 may detect a current temperature inside the memory device 130 . The temperature sensor 141 may store a value indicating the current temperature in the registers 140 . The memory controller 110 may issue a command for reading the registers 140 . The current temperature value sensed by the temperature sensor 141 and stored in the registers 140 may be transmitted to the memory controller 110 according to the above-described command. For example, the command decoder 131 may decode a command for reading the registers 140 and transmit values stored in the registers 140 to the read circuit 138 . The read circuit 138 may provide the values stored in the registers 140 as read data to the DQ buffer 139 . DQ buffer 139 may transmit DQ signals including values stored in registers 140 to PHY 112 .

4 illustrates an example in which the second data of FIG. 3 is stored in a bank of a memory device. The memory controller 110 may store the second data sets Data 2[0] to Data 2[7] in memory cells corresponding to the error region of the bank 134 . A data set may mean multiple pieces of data, and an index is for distinguishing data. In FIG. 4 , the X axis may indicate a direction in which a word line extends and a direction in which a plurality of bit lines are disposed. In FIG. 4 , the Y axis may indicate a direction in which a bit line extends and a direction in which a plurality of word lines are disposed. For example, each data of the second data set (Data 2[0] to Data 2[7]) may be stored in the error zone of the bank 134 in a row unit. Each data may be stored in memory cells connected to a word line and constituting a page.

In an embodiment, the time taken for all memory cells in the error-free region to be refreshed, tREF, may be k ms (k is an arbitrary number). The time taken for all memory cells in the error region to be refreshed, tREF, may be n X k ms. For example, n may be a natural number of 2 or more. The tREF of the error zone may correspond to an integer multiple of tREF of the error-free zone. The refresh rate of the error-free region may be faster than the refresh rate of the error region.

In an embodiment, the memory controller 110 may determine whether data is to be stored in the error-free area or the error area according to the type of data, the importance of data, the type of the application program, and the like. The memory controller 110 may store data of the neural network in the error region. The memory controller 110 may store program code or data of an application program other than a neural network in an error-free area.

FIG. 5 is an exemplary flowchart for the memory controller of FIG. 3 to store second data in a memory device.

In operation S110 , the error correction circuit 111 of the memory controller 110 may replace some insignificant bits of the first data with parity bits for error correction of important bits of the first data. The error correction circuit 111 may select some non-significant bits to be replaced with parity bits according to the importance of the bits (see Data 1 [31:0] of FIGS. 2A and 2C ).

In operation S120 , the error correction circuit 111 may generate second data including the remaining bits of the first data and parity bits (see Data 2 [31:0] of FIGS. 2A and 2C ). Since the error correction circuit 111 does not add parity bits to the first data and replaces some unimportant bits with parity bits, the number of bits of the second data and the number of bits of the first data may be the same.

In operation S130 , the command generator 115 of the memory controller 110 may generate a command and an address for storing the second data of operation S120 in the memory device 130 . Here, the command may include at least one activation command and at least one write command. The command generator 115 may generate at least one address together with the at least one activation command. The at least one address may indicate at least one word line among word lines connected to memory cells located in an error region of the bank 134 .

6 is an exemplary flowchart for the memory controller of FIG. 3 to adjust an error zone and an error-free zone of the memory device.

In operation S210 , the command generator 115 of the memory controller 110 may generate a start address of the error region. For example, the start address of the error zone may be a row address. The memory controller 110 may generate a command for setting the start address of the error zone in the memory device 130 . An error zone and an error-free zone may be divided based on the start address of the error zone, and the starting address may also be referred to as a reference address.

In operation S220 , a setting command for adjusting the error region and a start address of the error region may be transmitted to the memory device 130 . In an embodiment, the instruction generator 115 may generate or adjust the start address of the error zone according to a request of a user, a processor, or an application program. The value of the start address may be any value between the minimum value and the maximum value of the row address for selecting the word lines of the bank 134 . The memory controller 110 may adjust a ratio of the number of memory cells allocated to the error-free region to the number of memory cells allocated to the error region.

In an embodiment, the start address of the error region may be stored in the registers 140 of the memory device 130 . The first counter 132_1 may generate a row address corresponding to the word lines connected to the memory cells of the error-free region based on the start address of the error region. The second counter 132_2 may generate row addresses corresponding to word lines connected to memory cells of the error region based on the start address of the error region.

In an embodiment, the start address of the error zone may also be stored in the register 118 of the memory controller 110 . The memory controller 110 reads the start address of the error region stored in the registers 140 by transmitting a command for reading the registers 140 to the memory device 130 , and stores the start address in the register 118 of the memory controller 110 . can

In an embodiment, since the number of banks 134 may be one or more, start addresses of error regions of the banks 134 may be the same or different from each other. The memory controller 110 may set the start addresses of the error regions of the banks 134 to be the same or set differently. In either case, the start addresses of the error regions of the banks 134 may be stored in the registers 140 respectively. When the start addresses of the error regions of the banks 134 are set differently, the memory device 130 may include as many refresh controllers 132 as the number of the banks 134 . When the start addresses of the error regions of the banks 134 are set to be identical to each other, one refresh controller 132 may be used to refresh at least two or more banks 134 . Memory cells of at least two or more banks 134 may be refreshed according to a row address generated by one refresh controller 132 .

FIG. 7 shows an exemplary flowchart for adjusting a refresh rate by the memory controller of FIG. 3 according to temperature and BER.

In step S310 , the memory controller 110 may check the current temperature of the memory device 130 . In response to a command from the memory controller 110 , the value corresponding to the current temperature sensed by the temperature sensor 141 and stored in the registers 140 is read through the read circuit 138 and the DQ buffer 139 to the memory controller ( 110) may be provided.

In step S320 , the memory controller 110 may check a desired BER. For example, the desired BER may be determined by a request of a user, a processor, or an application program. The memory controller 110 may receive desired BER information.

In operation S330 , the memory controller 110 may issue a command for adjusting the refresh rate based on the current temperature of the memory device 130 and the desired BER and transmit the command to the memory device 130 . The memory controller 110 may adjust the refresh rate based on a lookup table stored in the registers 118 . The lookup table will be described in detail in FIG. 8 .

For example, the refresh rate may be a ratio of the refresh rate of the error-free region of the bank 134 to the refresh rate of the error region of the bank 134 . As another example, the refresh rate may be a ratio of a time required for all memory cells in the error-free region of the bank 134 to be refreshed to a time required for all memory cells in the error region of the bank 134 to be refreshed.

In an embodiment, the memory controller 110 may generate information about the refresh rate together with a command for adjusting the refresh rate. The memory controller 110 may transmit information regarding the refresh rate to the memory device 130 , and information regarding the refresh rate may be stored in the registers 140 of the memory device 130 . For example, the information about the refresh rate may include information about the refresh rate or refresh time of the error-free zone. The information on the refresh rate may include information on the refresh rate or refresh time of the error zone. The refresh rate and refresh time may indicate how often memory cells are refreshed, and the refresh time may indicate a refresh period. The refresh controller 132 may adjust the refresh rate of the error-free region or adjust the refresh rate of the error region with reference to information about the refresh rate stored in the registers 140 . The refresh controller 132 may adjust a refresh rate in response to a command from the memory controller 110 .

8 shows an example of a lookup table showing the relationship between BER and refresh. The lookup table (LUT) of FIG. 8 shows the relationship between the BER and the refresh time. Refresh times according to BERs may be respectively mapped in the lookup table (LUT). The memory controller 110 may adjust the refresh time of the error-free region by referring to the lookup table (LUT) stored in the registers 118 .

For example, if the BER requested by a user, processor, or application program is 10 ^-6 , the refresh time of the error zone may be ^{2 3} times the refresh time of the error-free zone. The memory controller 110 may check the refresh time according to the BER specified in the lookup table LUT and adjust the refresh rate of the error region. All values of refresh times specified in the lookup table (LUT) are merely exemplary. As the requested BER increases, the refresh time of the error zone may also increase. For another example, if the BER requested by the user, processor, or application program is default, the refresh time of the error zone and the refresh time of the error-free zone may be the same. In this case, the memory device 130 may not operate as an approximate memory device.

Referring to FIG. 8 , the lookup table LUT may include information on refresh times according to BERs in a normal temperature range. The lookup table LUT may include information on refresh times according to BERs in an extended temperature range different from or higher than a normal temperature range. For example, the time the memory cell can hold data in the extended temperature range may be shorter than the time the memory cell can hold data in the normal temperature range. Accordingly, the refresh times in the extended temperature range may be shorter than the refresh times in the normal temperature range.

FIG. 9 is an exemplary flowchart for the memory device of FIG. 3 to perform a refresh command.

In operation S410 , the command decoder 131 of the memory device 130 may decode the refresh command transmitted from the memory controller 110 . The memory controller 110 may repeatedly generate a refresh command. The command decoder 131 of the memory device 130 may decode the repeatedly transmitted refresh command. The command decoder 131 may control the refresh controller 132 and the row decoder 135 .

In operation S420 , the refresh controller 132 may operate the first counter 132_1 based on the control of the command decoder 131 . The first counter 132_1 may generate and update a row address corresponding to the error-free region. The row address generated by the first counter 132_1 in the previous step S420 may be different from the row address generated by the first counter 132_1 in the current step S420.

In operation S430 , the row decoder 135 may receive the row address generated by the first counter 132_1 . The row decoder 135 may activate at least one word line corresponding to the row address and then deactivate it. When the word line is activated and deactivated by the row decoder 135 , memory cells connected to the word line may be refreshed. The memory cells refreshed in step S430 are memory cells arranged in an error-free region. Steps S410, S420, and S430 are steps for refreshing the memory cells disposed in the error-free region.

In operation S440 , the refresh controller 132 may determine whether to skip the refresh command. If the refresh command is not skipped (N) in step S440 , the refresh controller 132 may operate the second counter 132_2 in step S450 . The second counter 132_2 may generate and update a row address corresponding to the error zone. The row address generated by the second counter 132_2 in the previous step S450 may be different from the row address generated by the second counter 132_2 in the current step S450. In operation S460 , the row decoder 135 may receive the row address generated by the second counter 132_2 . The row decoder 135 may activate at least one word line corresponding to the row address and then deactivate it. When the word line is activated and deactivated by the row decoder 135 , memory cells connected to the word line may be refreshed. The memory cells refreshed in step S460 are memory cells arranged in the error region.

If the refresh command is skipped in step S440 (Y), the refresh controller 132 may count the number of skipped refresh commands in step S470. As the number of skipped refresh instructions increases, the refresh rate of the error region may be slowed and the refresh time of the error region may increase. Although not shown in FIG. 3 , the refresh controller 132 may further include a counter for counting the number of skipped refresh commands. The refresh controller 132 may further include a comparator for comparing the number of skipped refresh commands with a reference value. For example, the reference value may be stored in the registers 140 and may be changed by the memory controller 110 in step S330 of FIG. 7 . The reference value may be determined by or included in information about the refresh rate transmitted from the memory controller 110 . For example, in operation S440 , when the number of skipped refresh commands reaches a reference value, the refresh controller 132 may determine not to skip the refresh commands. Steps S410, S440, S450, S460, and S470 are steps for refreshing the memory cells disposed in the error region.

10 is a more detailed exemplary block diagram of the electronic device of FIG. 1 according to another embodiment of the present invention. 11 illustrates an example in which the second data of FIG. 10 is stored in a bank of a memory device. 10 and 11 will be described together. Differences between the electronic device 100 of FIG. 10 and the electronic device 100 of FIG. 3 will be mainly described.

)로 변환할 수 있다. PHY(112)는 제 2 데이터 대신에 제 2 전치 데이터를 메모리 장치(130)로 전송할 수 있다.The memory controller 110 may further include a pre-circuit 120 compared to the memory controller 110 of FIG. 3 . The pre-circuit 120 receives the second data Data 2 encoded by the error correction circuit 111 and converts the second data to the second pre-data (

) can be converted to The PHY 112 may transmit the second prefix data to the memory device 130 instead of the second data.

)는 하나 이상의 페이지들에 저장될 수 있다. 전치 회로(120)는 제 2 데이터가 뱅크(134)의 하나 이상의 페이지들에 저장되도록 제 2 데이터의 행과 열을 변경함으로써 제 2 전치 데이터를 생성할 수 있다.The second transposed data converted by the transpose circuit 120 may be stored in one or more pages of the bank 134 . Referring to FIG. 4 described above, second data (eg, Data 2 [0]) may be stored in one page. On the other hand, referring to FIG. 11 , the second transposed data (eg,

) may be stored in one or more pages. The transpose circuit 120 may generate the second transposed data by changing rows and columns of the second data so that the second data is stored in one or more pages of the bank 134 .

Referring to FIG. 3 described above, the bank 134 is divided into only two zones, an error-free zone and an error zone. 10 and 11 , the bank 134 may be divided into first to third zones (Zone 1 to Zone 3). For example, bank 134 may be divided into multiple regions and the tREFs of the multiple regions may be different. Referring to FIG. 11 , tREF of the second region may be longer than tREF of the first region. The tREF of the third region may be longer than the tREF of the second region. As described above, tREF refers to the time it takes for all memory cells in the corresponding region to be refreshed. For example, the first zone may correspond to the aforementioned error-free zone, and the second and third zones may correspond to zones into which the aforementioned error zone is divided. As another example, all of the first to third regions may correspond to regions in which the aforementioned error region is divided.

Referring to FIG. 11 , the sign bit of the second transposed data may be stored in the first region. Exponential bits of the second transposed data may be stored in the second region. Mantissa bits of the second transposed data may be stored in the third region. For example, the MSB of the second transposed data may be stored in one of the memory cells coupled to the word line of the first region and the LSB of the second transposed data stored in one of the memory cells coupled to the word line of the third region can be If the bank 134 is divided into three or more regions, bits of the second transposed data may also be distributed and stored in three or more regions. The memory controller 110 may change the positions of the bits of the second data by using the preposition circuit 120 , and important bits are stored in a region where tREF is relatively short, and insignificant bits are stored in a region where tREF is relatively long. can be saved.

In an embodiment, the pre-circuit 120 may change logical values of bits of the second data. The time the first logic value is maintained in the memory cell may be longer than the time the second logic value is held in the memory cell. Accordingly, the pre-circuit 120 may compare the number of first logical values of the bits of the second data with the number of second logical values of the bits of the second data. The pre-circuit 120 may invert the logical values of the bits of the second data in units of columns based on the comparison result so that more first logical values than the second logical values are stored in the memory cells. The pre-circuit 120 may invert the bits of the read data transmitted from the memory device 130 again.

The refresh controller 132 of the memory device 130 may further include a third counter 132_3 . The first and second counters 132_1 and 132_2 of FIG. 10 may operate substantially the same as the first and second counters 132_1 and 132_2 of FIG. 3 . The third counter 132_3 may operate substantially the same as the second counter 132_2 . The first counter 132_1 may generate a row address for refreshing memory cells disposed in the first region. The second counter 132_2 may generate a row address for refreshing memory cells disposed in the second region. The third counter 132_3 may generate a row address for refreshing memory cells disposed in the third region. The multiplexer 132_4 may also provide the row address generated by the third counter 132_3 to the row decoder 135 . Periods or times at which the first to third counters 132_1 to 132_3 generate row addresses may be different from each other. That is, the refresh controller 132 may control the first to third counters 132_1 to 132_3 so that tREFs of the first to third regions are different from each other. The refresh controller 132 may include as many counters as the number of regions into which the bank 134 is divided.

12 illustrates the memory device of FIG. 1 according to an embodiment of the present invention. The memory device 1300 may be a memory module. Memory modules conform to JEDEC (Joint electron device engineering council) standards: Dual in-line memory module (DIMM), Registered DIMM (RDIMM), Load reduced DIMM (LRDIMM), Unbuffered DIMM (UDIMM), Fully buffered DIMM (FB-DIMM) ), a small outline DIMM (SO-DIMM), or another memory module (eg, a single in-line memory module (SIMM). The memory device 1300 includes first to eighth memory chips 1310 to 1380 . ) may be included.

Each of the first to eighth memory chips 1310 to 1380 is DDR SDRAM (double data rate synchronous dynamic random access memory), DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, DDR5 SDRAM, LPDDR (low power double data rate) SDRAM, LPDDR2 Various DRAM devices such as SDRAM, LPDDR3 SDRAM, LPDDR4 SDRAM, LPDDR4X SDRAM, LPDDR5 SDRAM, GDDR SGRAM (Graphics double data rate synchronous graphics random access memory), GDDR2 SGRAM, GDDR3 SGRAM, GDDR4 SGRAM, GDDR5 SGRAM, GDDR6 SGRAM, etc. .

Each of the first to eighth memory chips 1310 to 1380 may be the memory device 130 of FIG. 3 or 10 and may include components of the memory device 130 . Each of the first to eighth memory chips 1310 to 1380 may include memory cells corresponding to an error-free region and memory cells corresponding to an error region. The first to eighth memory chips 1310 to 1380 may receive commands and addresses (CMD/ADD) transmitted from the memory controller (refer to 110 of FIGS. 3 and 10 ) in common.

Each of the first to eighth memory chips 1310 to 1380 may transmit eight DQ signals to or receive from the memory controller. The memory device 1300 may transmit a total of 64 DQ signals DQ[63:0] to or receive from the memory controller. For example, when the number of bits of the second data is 32, the second data corresponding to the first word may be stored in the first to fourth memory chips 1310 to 1340 . The second data corresponding to the second word may be stored in the fifth to eighth memory chips 1350 to 1380 . Compared to other memory chips 1320 to 1340 and 1360 to 1380 , the first and fifth memory chips 1310 and 1350 may store relatively important bits, that is, a sign bit and an exponent bit. As described above, the second data may be stored in memory cells corresponding to the error-free regions of the first to eighth memory chips 1310 to 1380 .

13 illustrates the memory device of FIG. 1 according to another embodiment of the present invention. The memory device 2300 may be a memory module similar to the memory device 1300 of FIG. 12 . Differences between the memory device 2300 and the memory device 1300 will be mainly described.

Each of the second to fourth memory chips 2320 to 2340 and the sixth to eighth memory chips 2360 to 2380 may be the memory device 130 of FIG. 3 or 10 , and may include components of the memory device 130 . may include Memory cells of the second to fourth memory chips 2320 to 2340 and the sixth to eighth memory chips 2360 to 2380 may be divided into an error-free region and an error region.

The memory cells of the first and fifth memory chips 2310 and 2350 have an error-free region and an error region, unlike the second to fourth memory chips 2320 to 2340 and the sixth to eighth memory chips 2360 to 2380 . may not be distinguished from All memory cells of the first and fifth memory chips 2310 and 2350 may correspond to an error-free region. For example, the first and fifth memory chips 2310 and 2350 may include components of the memory device 130 except for the second and third counters 132_2 and 132_3 and the multiplexer 132_4 . As another example, the first and fifth memory chips 2310 and 2350 may include all components of the memory device 130 . The memory controller 110 may set the first and fifth memory chips 2310 and 2350 so that the memory cells of the bank 134 of the first and fifth memory chips 2310 and 2350 are all refreshed at the same rate.

Similar to the case of FIG. 12 , each of the first to eighth memory chips 2310 to 2380 may transmit eight DQ signals to or receive from the memory controller. The memory device 2300 may transmit a total of 64 DQ signals DQ[63:0] to or receive from the memory controller. For example, when the number of bits of the second data is 32, the second data corresponding to the first word may be stored in the first to fourth memory chips 2310 to 2340 . The second data corresponding to the second word may be stored in the fifth to eighth memory chips 2350 to 2380 . Compared to other memory chips 2320 to 2340 and 2360 to 2380, the first and fifth memory chips 2310 and 2350 may store relatively significant bits, that is, a sign bit and an exponent bit. Bits stored in the first and fifth memory chips 2310 and 2350 are refreshed at a rate at which bits stored in the second to fourth memory chips 2320 to 2340 and sixth to eighth memory chips 2360 to 2380 are refreshed. may be faster than the

14 is an exemplary block diagram of an electronic device according to another embodiment of the present invention. The electronic device 3000 may include a system-on-chip (SoC) 3100 and a memory device 3300 . The SoC 3100 may include a memory controller 3111 including a PHY 3112 , a processor 3120 , and a memory 3130 . The memory controller 3111 may be the memory controller 110 described above with reference to FIGS. 1 to 11 . The PHY 3112 may be the PHY 112 described above with reference to FIGS. 1 to 11 . The memory device 3300 may be the memory device 130 including memory cells divided into an error-free region and an error region.

The processor 3120 may execute various software (application programs, operating systems, file systems, device drivers, etc.) loaded into the memory 3130 . The processor 3120 may include homogeneous multi-core processors or heterogeneous multi-core processors. For example, the processor 3120 may include a central processing unit (CPU), an image signal processing unit (ISP), a digital signal processing unit (DSP), a graphics processing unit (GPU), a vision processing unit (VPU), and a neural network (NPU). processing unit).

An application program for driving the electronic device 3000 , an operating system, a file system, a device driver, and the like may be loaded into the memory 3130 . For example, the memory 3130 may be an SRAM device implemented inside the SoC 3100 and having a data input/output speed faster than that of the memory device 3300 , using registers, latches, flip-flops, or the like. can be implemented. Memory 3130 may also be referred to as on-chip memory or buffer memory.

The memory 3130 may be a non-transitory computer-readable medium storing program code. The memory 3130 may include random access memory (RAM), flash memory, read only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or It may be any form of storage medium. As illustrated in FIG. 14 , the memory 3130 may be implemented in the SoC 3100 , or, unlike the illustration in FIG. 14 , the memory 3130 is implemented in the electronic device 3000 independently of the SoC 3100 , or Alternatively, it may be a storage medium located outside the electronic device 3000 .

In an embodiment, the program code stored or loaded in the memory 3130 may be executed by the processor 3120 . Based on the control of the processor 3120 executing the program code, the memory controller 3111 may perform steps S110 to S130, S210 to S220, and S310 to S330 of the flowcharts of FIGS. 5 to 7 .

In an embodiment, the program code stored in the memory 3130 may be executed by another processor (not shown) inside the memory controller 3111 that is distinct from the processor 3120 . The processor in the memory controller 3111 may execute a program code and perform steps S110 to S130, S210 to S220, and S310 to S330 of the flowcharts of FIGS. 5 to 7 .

In an embodiment, the memory controller 3111 , the processor 3120 , and the memory 3130 of the SoC 3000 may be connected to each other through a bus. The bus may be of an Advanced Microcontroller Bus Architecture (AMBA) standard bus specification type. A bus type of AMBA may include an Advanced High-Performance Bus (AHB), an Advanced Peripheral Bus (APB), and an Advanced eXtensible Interface (AXI).

15 is an exemplary flowchart illustrating an operation method of the memory controller of FIG. 14 .

In step S1100 , the memory controller 3111 may receive a request from the processor 3120 . The processor 3120 may execute a neural network, such as a DNN, CNN, RNN, or SNN, and an application program. The processor 3120 may provide a request for data to the memory controller 3111 . The processor 3120 may provide data to the memory controller 3111 .

In operation S1200 , the memory controller 3111 may convert the logical address provided from the processor 3120 into a physical address (eg, a bank address, a row address, and a column address) of the memory device 3300 . The memory controller 3111 may check whether the physical address converted from the logical address of the request corresponds to the error zone.

In step S1300 , the memory controller 3111 may check whether data according to the request of step S1100 is cached (stored) in the memory 3130 . The memory 3130 of step S1300 may be an internal cache memory, a buffer memory, or an on-chip memory of the SoC 3000 . If the data according to the request of step S1100 is cached in the memory 3130 (hit, Y), step S1700 may proceed. If the data according to the request of step S1100 is not cached in the memory 3130 (miss, N), step S1400 may proceed.

In operation S1400 , the memory controller 3111 may check whether a flag bit of a cache line (or entry) of the memory 3130 is dirty. When the flag bit is set to dirty (Y), it may mean that data of the cache line and data of the memory device 3300 are different. In operation S1500 , the memory controller 3111 may write data of the cache line to the memory device 3300 . If the flag bit is set to clean rather than dirty (N), the memory controller 3111 may read the memory device 3300 and write the read data to the cache line.

In step S1700 , the memory controller 3111 may access the memory 3130 . In step S1800 , the memory controller 3111 may check whether the request of S1100 is a write. If the request is write (Y), the memory controller 3111 may set the flag bit of the cache line to dirty in step S1900 . If the request is read (N), the memory controller 3111 may return data cached in the memory 3130 to the processor 3120 . Thereafter, the memory controller 3111 may receive a new request (step S1100 ).

16 is an exemplary block diagram of an electronic device according to another embodiment of the present invention. The electronic device 4000 may include an SoC 4100 , a substrate 4200 , and a memory device 4300 .

The SoC 4100 may be disposed on one surface of the substrate 4200 , and solder balls or bumps may be disposed on one surface of the SoC 4100 . The SoC 4100 and the substrate 4200 may be electrically connected to each other through solder balls or bumps. The SoC 4100 may include a memory controller 3111 , a PHY 3112 , a processor 3120 , a memory 3130 of FIG. 13 , and the like. The SoC 4100 may include components of the memory controller 110 . The memory controller of the SoC 4100 may perform the steps of the flowcharts of FIGS. 5 to 7 and 15 .

The substrate 4200 may provide an input/output path between the SoC 4100 and the memory device 4300 . For example, the substrate 4200 may be a printed circuit board, a flexible circuit board, a ceramic substrate, or an interposer. When the substrate 4200 is an interposer, the substrate 4200 may be implemented using a silicon wafer. A plurality of input/output paths (I/O paths) may be implemented in the substrate 4200 . Commands, addresses, and data may be transmitted via input/output paths.

The memory device 4300 may include memory dies 4310 and 4320 and a buffer die 4330 stacked in a vertical direction. The memory device 4300 may be a memory device in which DRAM dies are stacked, such as high bandwidth memory (HBM), HBM2, and HBM3. The memory device 4300 may be disposed on one surface of the substrate 4200 , and solder balls or bumps may be disposed on one surface of the memory device 4300 . The memory device 4300 and the substrate 4200 may be electrically connected to each other through solder balls or bumps.

The through electrodes TSV may provide physical or electrical paths between the memory dies 4310 and 4320 and the buffer die 4330 . For example, the through electrodes TSV may be arranged in a matrix arrangement, and the arrangement position is not limited to that illustrated in FIG. 16 .

The memory die 4310 may include a first region 4314 and a second region 4315 . In the first area 4314 , components of the memory device 130 described with reference to FIG. 3 or 10 may be disposed. In the second region 4315 , through electrodes TSV may be disposed and circuits for transmitting or receiving signals through the through electrodes TSV may be disposed. The memory die 4320 may be implemented substantially the same as the memory die 4310 .

The buffer die 4330 (which may also be referred to as a core die or a logic die) may include a first area 4334 and a second area 4335 . In the first area 4334 , at least one receiver for receiving commands, addresses, and data input/output signals CMD, ADD, and DQ transmitted from the SoC 4100 through input/output paths may be disposed. have. At least one transmitter that transmits the data input/output signal DQ to the SoC 4100 through the input/output paths I/O paths may be disposed in the first area 4334 . In addition, components of the memory device 130 described with reference to FIG. 3 or 10 may be disposed in the first area 4334 . In the second region 4335 , through electrodes TSV may be disposed and circuits for transmitting or receiving signals through the through electrodes TSV may be disposed.

The contents described above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented in the future using the above-described embodiments.

Claims (20)

For the memory controller:
In response to receiving a write command and first data from an external device, generate parity bits from the first data, replace some bits of the first data with the parity bits, and replace the replaced bits from the some bits an error correction circuit configured to generate second data including parity bits and remaining bits of the first data; and
a physical layer configured to receive the second data from the error correction circuitry and to transmit the second data to a memory device;
In response to receiving a read command from the external device, the memory controller reads the second data as third data. The method of claim 1,
The some bits correspond to some bits of exponent bits of the first data expressed in a floating-point format. The method of claim 1,
The some bits correspond to lower bits of the first data. The method of claim 1,
The error correction circuit is further configured to perform an error correction operation on the third data using parity bits of the third data included in the third data transmitted from the memory device. The method of claim 1,
The first data is a memory controller used for calculation of a neural network. delete The method of claim 1,
the memory controller is further configured to adjust a reference address provided to the memory device, and
A memory controller in which the memory cell array of the memory device is divided into a first area and a second area according to the reference address. 8. The method of claim 7,
The refresh rate of the first region is faster than the refresh rate of the second region, and
the physical layer is further configured to transmit an address indicating the second region to the memory device so that the second data is stored in the second region. 8. The method of claim 7,
and the memory controller is further configured to adjust a ratio of a refresh rate of the first region to a refresh rate of the second region based on a bit error rate (BER). A non-transitory computer readable medium storing program code, wherein when the program code is executed by a processor, the processor comprises:
generating parity bits from the first data in response to receiving a first write command and first data from an external device, and replacing some bits of the first data with the parity bits;
generating second data including the parity bits replaced from the partial bits and the remaining bits of the first data; and
generating a second write command for storing the second data in a memory device; and
In response to receiving a read command from the external device, the non-transitory computer-readable medium performs the step of reading the second data. 11. The method of claim 10,
The processor further performs the steps of generating a setting command and a reference address for dividing the memory cell array of the memory device into a first region and a second region, and
wherein the second data is stored in the second region. 12. The method of claim 11,
The processor further performs the step of repeatedly generating a refresh command for the memory device, and
A non-transitory computer-readable medium in which a refresh rate of the first region by the refresh command is faster than a refresh rate of the second region by the refresh command. 12. The method of claim 11,
The processor, based on a bit error rate (BER), generates a setting command for adjusting a ratio of a refresh rate of the first region and a refresh rate of the second region. media. 11. The method of claim 10,
the first data is used for computation of a neural network, and
The some bits correspond to exponent bits of the first data expressed in a floating-point format, or correspond to low-order bits of the first data. a processor configured to generate a write command and first data;
In response to receiving the write command and the first data from the processor, generate parity bits from the first data, replace some bits of the first data with the parity bits, and a memory controller configured to generate second data including the replaced parity bits and remaining bits of the first data; and
a memory device configured to store the second data transmitted from the memory controller;
The memory controller reads the second data in response to receiving a read command from the processor. 16. The method of claim 15,
and the processor is further configured to generate the first data by executing a neural network application. 16. The method of claim 15,
the memory device includes a memory cell array divided into a first region and a second region having a refresh rate lower than a refresh rate of the first region;
the memory controller is further configured to generate a command for storing the second data in the memory device and an address indicative of at least a portion of the second region,
The second data is stored in the second area according to the command and the address. 16. The method of claim 15,
The memory device includes a memory cell array including first memory cells connected to a first word line and second memory cells connected to a second word line;
a most significant bit (MSB) of the second data is stored in one of the first memory cells and a least significant bit (LSB) of the second data is stored in one of the second memory cells, and
The refresh rate of the first memory cells is faster than the refresh rate of the second memory cells. 16. The method of claim 15,
The memory device includes a memory cell array divided into a first region and a second region having a refresh rate lower than a refresh rate of the first region;
and wherein the memory controller includes registers for storing a lookup table in which bit error rates (BERs) and ratios of the refresh rate of the first region and the refresh rate of the second region are mapped. 16. The method of claim 15,
The memory device is an electronic device that is a dynamic random access memory (DRAM) device.

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