CN113540258A - 碳化硅二极管结构及制作方法 - Google Patents
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 124
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 123
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 38
- 239000002131 composite material Substances 0.000 claims abstract description 25
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000002161 passivation Methods 0.000 claims abstract description 19
- 239000010410 layer Substances 0.000 claims description 298
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 82
- 239000000377 silicon dioxide Substances 0.000 claims description 41
- 235000012239 silicon dioxide Nutrition 0.000 claims description 39
- 238000000151 deposition Methods 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 25
- 239000002184 metal Substances 0.000 claims description 25
- 238000000034 method Methods 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 20
- 239000011241 protective layer Substances 0.000 claims description 20
- 239000004642 Polyimide Substances 0.000 claims description 18
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 18
- 238000000576 coating method Methods 0.000 claims description 18
- 238000002955 isolation Methods 0.000 claims description 18
- 229920001721 polyimide Polymers 0.000 claims description 18
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 18
- 238000005530 etching Methods 0.000 claims description 15
- 239000005360 phosphosilicate glass Substances 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 15
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 239000011521 glass Substances 0.000 claims description 13
- 230000008021 deposition Effects 0.000 claims description 11
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 8
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 8
- 229910052799 carbon Inorganic materials 0.000 claims description 8
- 238000001035 drying Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 7
- 238000002513 implantation Methods 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 230000036961 partial effect Effects 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 5
- -1 boron ion Chemical class 0.000 claims description 5
- 238000000227 grinding Methods 0.000 claims description 5
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 230000003647 oxidation Effects 0.000 claims description 5
- 238000007254 oxidation reaction Methods 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 239000001301 oxygen Substances 0.000 claims description 4
- 229910052760 oxygen Inorganic materials 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 239000003292 glue Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 230000002829 reductive effect Effects 0.000 abstract description 12
- 230000007547 defect Effects 0.000 abstract description 9
- 238000000407 epitaxy Methods 0.000 abstract description 3
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 238000004140 cleaning Methods 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 239000000956 alloy Substances 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000861 blow drying Methods 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000011651 chromium Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000001657 homoepitaxy Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000012858 packaging process Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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Abstract
本发明提供了一种碳化硅二极管结构及制作方法,包括碳化硅衬底、碳化硅外延层、正面电极、肖特基势垒层、P型分压环、N型截止环、复合终端钝化层、欧姆接触层以及背面电极;背面电极、欧姆接触层、碳化硅衬底从下往上依次叠加,N型截止环位于P型分压环的外侧;肖特基势垒层和正面电极在碳化硅外延层的上表面从下往上依次叠加,复合终端钝化层设置在碳化硅外延层的上表面,复合终端钝化层将正面电极半包围。通过带有阻挡缓冲层的双层碳化硅外延,减少了碳化硅衬底的缺陷,通过N型截止环,可以有效的截断漏电通道产生的漏电流,能够减少器件边缘漏电量大的情况发生;复合终端钝化层可以对器件形成整体保护,增强了器件可靠性。
Description
技术领域
本发明涉及半导体器件技术领域,具体地,涉及一种碳化硅二极管结构及制作方法。
背景技术
碳化硅是一种由硅和碳构成的化合物半导体材料,具有优越的电学性能,第三代半导体-SIC(碳化硅)因其高禁带宽度、高阻断电压和高热导率等特性,成为制作高温、高频、抗辐射和大功率电力电子器件的理想半导体材料。平面碳化硅器件具有高可靠性特性的重要条件是具有良好的结构与终端保护。
现有公开号为CN109509706A的中国专利,其公开了一种碳化硅二极管的制备方法及由该制备方法制成的碳化硅二极管,该碳化硅二极管包括一碳化硅衬底、一碳化硅外延层、一图形化的场板介质层、一图形化的肖特基接触电极和一欧姆接触电极层;碳化硅外延层设置于碳化硅衬底的正面;在碳化硅外延层内且沿着碳化硅外延层的上表面设置有图形化的离子注入区;碳化硅外延层的上表面设置有图形化的场板介质层,且碳化硅外延层的上表面未图形化的场板介质层覆盖的区域设置有图形化的肖特基接触电极;图形化的场板介质层的上表面的部分区域被图形化的肖特基接触电极覆盖,其余区域裸露;欧姆接触电极层设置于碳化硅衬底的背面。
发明人认为现有技术中的碳化硅二极管容易受到衬底缺陷和界面不稳定性的影响,造成器件的可靠性差,且对于碳化硅器件在反向工作时,尤其在高温条件下工作时,当氧化层上的表面电荷足以引起n型半导体内产生较大漏电通道,器件边缘容易出现漏电大的问题,存在待改进之处。
发明内容
针对现有技术中的缺陷,本发明的目的是提供一种碳化硅二极管结构及制作方法。
根据本发明提供的一种碳化硅二极管结构,包括碳化硅衬底、碳化硅外延层、正面电极、肖特基势垒层、P型分压环、N型截止环、复合终端钝化层、欧姆接触层以及背面电极;所述背面电极、欧姆接触层以及碳化硅衬底从下往上依次叠加,所述碳化硅外延层在碳化硅上方设置有一层或多层,所述P型分压环通过离子注入设置在位于最上层的碳化硅外延层内,所述N型截止环通过离子注入设置在位于最上层的碳化硅外延层内,且所述N型截止环位于P型分压环的外侧;所述肖特基势垒层和正面电极二者在位于最上层的碳化硅外延层的上表面从下往上依次叠加,所述复合终端钝化层设置在位于最上层的碳化硅外延层的上表面,且所述复合终端钝化层将正面电极半包围并使正面电极的上表面的局部裸露。
优选地,所述正面电极的上侧边缘位置形成有配合部,所述复合终端钝化层包括二氧化硅层和磷硅玻璃层,所述二氧化硅层和磷硅玻璃层二者在位于最上层的碳化硅外延层的上表面从下往上依次叠加,且所述磷硅玻璃层的上表面与配合部的下表面贴合。
优选地,所述复合终端钝化层还包括氮化硅层和聚酰亚胺层,所述氮化硅层和聚酰亚胺层二者均在磷硅玻璃层的上表面从下往上依次叠加,且所述氮化硅层和聚酰亚胺层二者均覆盖正面电极上表面的边缘。
优选地,所述碳化硅衬底与碳化硅外延层之间设置有隔离缓冲层。
优选地,所述隔离缓冲层包括N型碳化硅导电材料,厚度在0.5um至2um之间,电阻率在1016-1017之间。
优选地,碳化硅外延层包括第一外延层和第二外延层,所述第一外延层位于第二外延层的下方,所述第一外延层和第二外延层二者均包括碳化硅导电材料;所述第一外延层的厚度在0.5um至5um之间,所述第一外延层的电阻率在1016-1017之间;所述第二外延层的厚度在2um至50um之间,所述第二外延层的电阻率在1015-1016之间。
根据本发明提供的一种碳化硅二极管结构的制作方法,包括权利要求1-6任一项权利要求所述的一种碳化硅二极管结构,制作方法包括如下步骤:S1、准备所述碳化硅衬底,并在所述碳化硅衬底的上表面生长隔离缓冲层;S2、在所述隔离缓冲层的上表面分两次或多次淀积形成多层碳化硅外延层;S3、在位于最上层的所述碳化硅外延层的外表面通过淀积生成二氧化硅保护层,再通过光刻胶的涂布曝光显影工艺进行刻蚀处理形成N型区窗口,之后再通过多次N离子注入形成N型截止环;S4、去除二氧化硅保护层并烘干;S5、在位于最上层的所述碳化硅外延层的外表面通过淀积生成二氧化硅保护层,再通过光刻胶的涂布曝光显影工艺进行刻蚀处理形成P型区窗口,之后再通过多次 P离子注入形成P型分压环;S6、去除二氧化硅保护层并烘干;S7、通过溅射或涂布PR 胶的方式淀积碳膜,之后进行高温退火激活,然后再去除碳膜;S8、在位于最上层的所述碳化硅外延层的上方进行热氧生长二氧化硅层,之后再在二氧化硅层的上方使用炉管或CVD淀积形成磷硅玻璃层;S9、在所述二氧化硅层和磷硅玻璃层上通过光刻胶的涂布曝光显影工艺进行刻蚀,形成电极窗口;S10、在电极窗口处淀积金属形成所述肖特基势垒层;S11、在所述肖特基势垒层上淀积金属或复合金属,并通过光刻胶的涂布曝光显影工艺进行刻蚀形成所述正面电极;S12、在所述磷硅玻璃层的上方依次淀积氮化硅层和聚酰亚胺层,通过光刻胶的涂布曝光显影工艺进行刻蚀使所述正面电极顶部的部分区域裸露;S13、通过研磨将所述碳化硅衬底的厚度减薄到100um-300um;S14、在所述碳化硅衬底的背面淀积金属镍形成所述欧姆接触层;S15、在所述欧姆接触层的背面淀积金属或复合金属形成背面电极。
优选地,对于步骤S3,N型离子注入为氮离子,注入温度为300-700度,注入能量为300-600kev。
优选地,对于步骤S5,P型离子注入为AL离子或硼离子,注入温度为300-700度,注入能量30-800kev。
优选地,对于步骤S8,热氧温度在1300-2000度之间,氧化厚度为10-1000埃;所述磷硅玻璃层的厚度为1000-10000埃。
与现有技术相比,本发明具有如下的有益效果:
1、本发明通过使用带有阻挡缓冲层的双层碳化硅外延,减少了碳化硅衬底缺陷在同质外延时延伸到碳化硅外延中,减少了碳化硅衬底的缺陷,从而有助于提高产品的良品率和可靠性;且通过N型截止环,可以有效的截断漏电通道产生的漏电流,从而有助于减少器件边缘漏电量大的情况发生;
2、本发明通过在终端最外侧增加N型截止环,即耗尽层外的氧化层边缘充当漏电通道截止作用,一方面可以有效的截断漏电通道产生的漏电流,另一方面能够有效防止多种情况下导致的P型分压环的损伤,从而有助于提高碳化硅二极管的使用寿命;
3、本发明通过二氧化硅层、磷硅玻璃层、氮化硅层以及聚酰亚胺层形成了多层复合终端钝化层结构,有助于提高对终端的整体保护效果;并解决了不同薄膜层间存在应力大的问题以及与金属层材料的膨胀系数不匹配的问题、降低了薄膜层间的内应力,提升了产品抗封装能力,降低了晶圆加工以及封装过程中的碎芯率,从而有助于增强器件的可靠性。
附图说明
通过阅读参照以下附图对非限制性实施例所作的详细描述,本发明的其它特征、目的和优点将会变得更明显:
图1为本发明主要体现碳化硅二极管整体的层结构示意图;
图2为本发明主要体现碳化硅二极管制作方法的流程图。
图中所示:
具体实施方式
下面结合具体实施例对本发明进行详细说明。以下实施例将有助于本领域的技术人员进一步理解本发明,但不以任何形式限制本发明。应当指出的是,对本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变化和改进。这些都属于本发明的保护范围。
如图1所示,根据本发明提供的一种碳化硅二极管结构,包括碳化硅衬底10、隔离缓冲层11、碳化硅外延层14、正面电极70、肖特基势垒层40、P型分压环20、N型截止环30、复合终端钝化层99、欧姆接触层100以及背面电极110。
如图1所示,背面电极110、欧姆接触层100以及碳化硅衬底10三者从下往上依次叠加。碳化硅衬底10为N型导电材料制成的层结构,且碳化硅衬底10的厚度在 100-300um之间,优选200um。欧姆接触层100由金属镍在碳化硅衬底10的背面淀积而成,且欧姆接触层100的厚度在50nm到1000nm之间,优选1000nm。背面电极110由金属或复合金属在欧姆接触层100的背面淀积而成,背面电极110包括但不限于钛金属层、镍金属层、银金属层以及连续多层金属组合而成的合金层,且背面电极110的厚度在 1-10um之间,优选5um。
如图1所示,隔离缓冲层11生长在碳化硅衬底10的上表面,隔离缓冲层11为N 型碳化硅导电材料层,隔离缓冲层11的厚度在0.5um至2um之间,优选1um;电阻率在1016-1017之间。碳化硅外延层14在隔离缓冲层11的上表面从下向上依次生长有两层,碳化硅外延层14为N型碳化硅导电材料层,两层碳化硅外延层14分别为第一外延层12 和第二外延层13,第一外延层12位于第二外延层13的下方,且第一外延层12的底面与隔离缓冲层11的顶面接触。
第一外延层12的厚度在0.5um至5um之间,优选5um,且第一外延层12的电阻率在1016-1017之间;第二外延层13的厚度在2um至50um之间,优选20um,第二外延层 13的电阻率在1015-1016之间。使用带有隔离缓冲层11的双层碳化硅外延层14,能够减少碳化硅衬底10缺陷在同质外延时延伸到碳化硅外延层14中,降低了碳化硅衬底10 的缺陷,提升了产品的良品率及可靠性。
P型分压环20和N型截止环30二者均安装在第二外延层13的上侧,且P型分压环 20通过离子注入在第二外延层13内同心安装有三个,N型截止环30通过离子注入在第二外延层13的边缘位置安装有一个,N型截止环30位于三个P型分压环20的外侧,且N型截止环30与三个P型分压环20同心。在第二外延层13最外侧的N型截止环30,能够耗尽层外的氧化层边缘充当漏电通道截止作用,可以有效的截断漏电通道产生的漏电流,并且能够有效的减少多种情况下导致的P型分压环20的损伤。
肖特基势垒层40通过淀积生长在第二外延层13顶壁的中部,肖特基势垒层40包括但不限于钛层、镍层、钼层、铂层、铬层以及合金层。正面电极70在肖特基势垒层 40的上方通过淀积生长而成,正面电极70包括但不限于钛层、镍层、钼层、铂层、铬层以及合金层,正面电极70的厚度在1-10um之间,优选5um,且正面电极70上侧的边缘位置形成有配合部71。
复合终端钝化层99包括二氧化硅层50、磷硅玻璃层60、氮化硅层80以及聚酰亚胺层90,二氧化硅层50磷硅玻璃层60、氮化硅层80以及聚酰亚胺层90四者在第二外延层13的上表面从下往上依次叠加,且复合终端钝化层99将正面电极70半包围并使正面电极70的上表面的局部裸露。磷硅玻璃层60的厚度为1000-10000埃,优选5000 埃,二氧化硅层50的厚度在10-1000埃之间,优选1000埃,且二氧化硅层50的底面与第二外延层13的上表面接触,磷硅玻璃层60的上表面与配合部71的下表面接触。氮化硅层80和聚酰亚胺层90二者均覆盖正面电极70的配合部71的上表面,且氮化硅层80的厚度在1000-10000埃之间,优选5000埃;聚酰亚胺层90的厚度在1um-5um之间,优选3um。
通过在正面电极70的下方设置的二氧化硅层50和磷硅玻璃层60、氮化硅层80以及聚酰亚胺层90四者组成的复合终端钝化层99,提高了对终端的整体保护程度,并解决了不同薄膜层间存在应力大的问题以及与金属层材料的膨胀系数不匹配的问题、降低了薄膜层间的内应力,提升了产品抗封装能力,降低了晶圆加工以及封装过程中的碎芯率,增强了器件的可靠性。
如图2所示,根据本发明提供的一种碳化硅二极管结构的制作方法,包括上述的一种碳化硅二极管结构,制作方法包括如下步骤:
S1、生成隔离缓冲层11:准备碳化硅衬底10,并在碳化硅衬底10的上表面生长隔离缓冲层11,隔离缓冲层11的厚度为1um。
S2、生成碳化硅外延层14:在隔离缓冲层11的上表面分两次淀积形成两层碳化硅外延层14;第一外延层12的厚度为5um,第二外延层13的厚度为20um。
S3、形成N型截止环30:在第二外延层13的外表面通过淀积生成二氧化硅保护层,二氧化硅保护层的厚度在1-2um之间。再通过光刻胶的涂布曝光显影工艺进行刻蚀处理形成N型区窗口,之后再通过多次N离子注入形成N型截止环30;N型离子注入为氮离子,注入温度为300-700度,注入能量为300-600kev。
S4、清除二氧化硅保护层:去除二氧化硅保护层并烘干,去除二氧化硅保护层后可采用清洗液清洗,并采用去离子水进行反复清洗、氮气吹干、烘干等过程。
S5、形成P型分压环20:在第二外延层13的外表面通过淀积生成二氧化硅保护层,二氧化硅保护层的厚度在1-2um之间。再通过光刻胶的涂布曝光显影工艺进行刻蚀处理形成P型区窗口,之后再通过多次P离子注入形成P型分压环20;P型离子注入为AL 离子或硼离子,注入温度为300-700度,注入能量30-800kev。
S6、清除二氧化硅保护层:去除二氧化硅保护层并烘干,去除二氧化硅保护层后可采用清洗液清洗,并采用去离子水进行反复清洗、氮气吹干、烘干等过程。
S7、高温退火激活:通过溅射或涂布PR胶的方式淀积碳膜,碳膜的厚度在10-1000nm,之后进行高温退火激活,高温退火激活的温度在1300-2000度之间,并使用惰性气体做保护气,然后再去除碳膜;
S8、生长二氧化硅层50和磷硅玻璃层60:在位于最上层的碳化硅外延层14的上方进行热氧生长二氧化硅层50,之后再在二氧化硅层50的上方使用炉管或CVD淀积形成磷硅玻璃层60;热氧温度在1300-2000度之间,氧化厚度为10-1000埃;所述磷硅玻璃层60的厚度为1000-10000埃。
S9、形成电极窗口:在二氧化硅层50和磷硅玻璃层60上通过光刻胶的涂布曝光显影工艺进行刻蚀,形成电极窗口。
S10、生长肖特基势垒层40:在电极窗口处淀积金属形成肖特基势垒层40。
S11、生长正面电极70:在肖特基势垒层40上淀积金属或复合金属,并通过光刻胶的涂布曝光显影工艺进行刻蚀形成正面电极70;正面电极70的厚度在1-10um之间。
S12、生长氮化硅层80和聚酰亚胺层90:在磷硅玻璃层60的上方依次淀积氮化硅层80和聚酰亚胺层90,通过光刻胶的涂布曝光显影工艺进行刻蚀使正面电极70顶部的部分区域裸露;氮化硅层80的厚度在1000-10000埃之间,聚酰亚胺层90的厚度在 1um-5um之间。
S13、研磨碳化硅衬底10:通过研磨将碳化硅衬底10的厚度减薄到100um-300um。
S14、形成欧姆接触层100:在碳化硅衬底10的背面淀积金属镍形成所述欧姆接触层100,欧姆接触层100的厚度在50nm-1000nm之间。
S15、形成背面电极110:在欧姆接触层100的背面淀积金属或复合金属形成背面电极110,背面电极110的厚度在1-10um之间。
工作原理
工作中工作人员依次通过生成隔离缓冲层11、生成碳化硅外延层14、形成N型截止环30、清除二氧化硅保护层、形成P型保护环、清除二氧化硅保护层、高温退火激活、生长二氧化硅层50和磷硅玻璃层60、形成电极窗口、生长肖特基势垒层40、生长正面电极70、生长氮化硅层80和聚酰亚胺层90、研磨碳化硅衬底10、形成欧姆接触层100、形成背面电极110等步骤制作具有隔离缓冲层11的双层碳化硅外延层14,并在第二外延层13内设置有N型截止环30,从而降低了碳化硅衬底10的缺陷,提高了产品的良品率以及可靠性,且可以有效的截断漏电通道产生的漏电流,并且能够有效防止多种情况下导致的P型分压环20的损伤。
在本申请的描述中,需要理解的是,术语“上”、“下”、“前”、“后”、“左”、“右”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示的方位或位置关系为基于附图所示的方位或位置关系,仅是为了便于描述本申请和简化描述,而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作,因此不能理解为对本申请的限制。
以上对本发明的具体实施例进行了描述。需要理解的是,本发明并不局限于上述特定实施方式,本领域技术人员可以在权利要求的范围内做出各种变化或修改,这并不影响本发明的实质内容。在不冲突的情况下,本申请的实施例和实施例中的特征可以任意相互组合。
Claims (10)
1.一种碳化硅二极管结构,其特征在于,包括碳化硅衬底(10)、碳化硅外延层(14)、正面电极(70)、肖特基势垒层(40)、P型分压环(20)、N型截止环(30)、复合终端钝化层(99)、欧姆接触层(100)以及背面电极(110);
所述背面电极(110)、欧姆接触层(100)以及碳化硅衬底(10)从下往上依次叠加,所述碳化硅外延层(14)在碳化硅上方设置有一层或多层,所述P型分压环(20)通过离子注入设置在位于最上层的碳化硅外延层(14)内,所述N型截止环(30)通过离子注入设置在位于最上层的碳化硅外延层(14)内,且所述N型截止环(30)位于P型分压环(20)的外侧;
所述肖特基势垒层(40)和正面电极(70)二者在位于最上层的碳化硅外延层(14)的上表面从下往上依次叠加,所述复合终端钝化层(99)设置在位于最上层的碳化硅外延层(14)的上表面,且所述复合终端钝化层(99)将正面电极(70)半包围并使正面电极(70)的上表面的局部裸露。
2.如权利要求1所述的一种碳化硅二极管结构,其特征在于,所述正面电极(70)的上侧边缘位置形成有配合部(71),所述复合终端钝化层(99)包括二氧化硅层(50)和磷硅玻璃层(60),所述二氧化硅层(50)和磷硅玻璃层(60)二者在位于最上层的碳化硅外延层(14)的上表面从下往上依次叠加,且所述磷硅玻璃层(60)的上表面与配合部(71)的下表面贴合。
3.如权利要求2所述的一种碳化硅二极管结构,其特征在于,所述复合终端钝化层(99)还包括氮化硅层(80)和聚酰亚胺层(90),所述氮化硅层(80)和聚酰亚胺层(90)二者均在磷硅玻璃层(60)的上表面从下往上依次叠加,且所述氮化硅层(80)和聚酰亚胺层(90)二者均覆盖正面电极(70)上表面的边缘。
4.如权利要求1所述的一种碳化硅二极管结构,其特征在于,所述碳化硅衬底(10)与碳化硅外延层(14)之间设置有隔离缓冲层(11)。
5.如权利要求4所述的一种碳化硅二极管结构,其特征在于,所述隔离缓冲层(11)包括N型碳化硅导电材料,厚度在0.5um至2um之间,电阻率在1016-1017之间。
6.如权利要求1所述的一种碳化硅二极管结构,其特征在于,所述碳化硅外延层(14)包括第一外延层(12)和第二外延层(13),所述第一外延层(12)位于第二外延层(13)的下方,所述第一外延层(12)和第二外延层(13)二者均包括碳化硅导电材料;
所述第一外延层(12)的厚度在0.5um至5um之间,所述第一外延层(12)的电阻率在1016-1017之间;
所述第二外延层(13)的厚度在2um至50um之间,所述第二外延层(13)的电阻率在1015-1016之间。
7.一种碳化硅二极管结构的制作方法,其特征在于,包括权利要求1-6任一项权利要求所述的一种碳化硅二极管结构,制作方法包括如下步骤:
S1、准备所述碳化硅衬底(10),并在所述碳化硅衬底(10)的上表面生长隔离缓冲层(11);
S2、在所述隔离缓冲层(11)的上表面分两次或多次淀积形成多层碳化硅外延层(14);
S3、在位于最上层的所述碳化硅外延层(14)的外表面通过淀积生成二氧化硅保护层,再通过光刻胶的涂布曝光显影工艺进行刻蚀处理形成N型区窗口,之后再通过多次N离子注入形成N型截止环(30);
S4、去除二氧化硅保护层并烘干;
S5、在位于最上层的所述碳化硅外延层(14)的外表面通过淀积生成二氧化硅保护层,再通过光刻胶的涂布曝光显影工艺进行刻蚀处理形成P型区窗口,之后再通过多次P离子注入形成P型分压环(20);
S6、去除二氧化硅保护层并烘干;
S7、通过溅射或涂布PR胶的方式淀积碳膜,之后进行高温退火激活,然后再去除碳膜;
S8、在位于最上层的所述碳化硅外延层(14)的上方进行热氧生长二氧化硅层(50),之后再在二氧化硅层(50)的上方使用炉管或CVD淀积形成磷硅玻璃层(60);
S9、在所述二氧化硅层(50)和磷硅玻璃层(60)上通过光刻胶的涂布曝光显影工艺进行刻蚀,形成电极窗口;
S10、在电极窗口处淀积金属形成所述肖特基势垒层(40);
S11、在所述肖特基势垒层(40)上淀积金属或复合金属,并通过光刻胶的涂布曝光显影工艺进行刻蚀形成所述正面电极(70);
S12、在所述磷硅玻璃层(60)的上方依次淀积氮化硅层(80)和聚酰亚胺层(90),通过光刻胶的涂布曝光显影工艺进行刻蚀使所述正面电极(70)顶部的部分区域裸露;
S13、通过研磨将所述碳化硅衬底(10)的厚度减薄到100um-300um;
S14、在所述碳化硅衬底(10)的背面淀积金属镍形成所述欧姆接触层(100);
S15、在所述欧姆接触层(100)的背面淀积金属或复合金属形成背面电极(110)。
8.如权利要求7所述的一种碳化硅二极管结构的制作方法,其特征在于,对于步骤S3,N型离子注入为氮离子,注入温度为300-700度,注入能量为300-600kev。
9.如权利要求7所述的一种碳化硅二极管结构的制作方法,其特征在于,对于步骤S5,P型离子注入为AL离子或硼离子,注入温度为300-700度,注入能量30-800kev。
10.如权利要求7所述的一种碳化硅二极管结构的制作方法,其特征在于,对于步骤S8,热氧温度在1300-2000度之间,氧化厚度为10-1000埃;所述磷硅玻璃层(60)的厚度为1000-10000埃。
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