CN113540104A

CN113540104A - Memory device

Info

Publication number: CN113540104A
Application number: CN202110375096.XA
Authority: CN
Inventors: 孙文堂; 许家荣; 陈学威
Original assignee: eMemory Technology Inc
Current assignee: eMemory Technology Inc
Priority date: 2020-04-13
Filing date: 2021-04-08
Publication date: 2021-10-22
Anticipated expiration: 2041-04-08
Also published as: CN113540104B; TW202139434A; TWI757145B

Abstract

The invention discloses a memory device, which comprises a first well, a second well, a third well, a floating gate layer, a first doped region, a second doped region, a third doped region, a groove isolation layer and a word line contact. The second well is located on the first well and includes a first portion and a second portion. The third well includes a first portion and a second portion on the first portion and the second portion of the second well, respectively. The first doped region, the second doped region, and the third doped region are located in the first portion of the third well. The trench isolation layer is used to isolate the first portion and the second portion of the second well and to isolate the first portion and the second portion of the third well. The word line contact is disposed on the second portion of the third well region for receiving a word line voltage.

Description

Memory device

Technical Field

The present invention relates to memory devices, and more particularly, to memory devices including a plurality of wells created using the same mask.

Background

As electronic products continue to advance, the importance of memory also continues to increase. Regarding the characteristics of memory devices, there are common demands for reducing the area occupied by the memory, increasing the speed of access, reducing power consumption, and the like.

However, it is not easy to achieve the above goal. At present, a conventional memory device in the field usually includes at least two transistors, and an additional erase gate is needed to operate normally, so that the device area is difficult to be reduced. In order to manufacture the above structure, two or more masks are required to be used compared to the standard device, so that the manufacturing cost is difficult to be reduced.

Therefore, the prior art still lacks a suitable solution to achieve the effects of saving area, increasing access speed, reducing process cost and saving power consumption.

Disclosure of Invention

A memory device comprising a first well; the second trap is positioned on the first trap and comprises a first part and a second part; a third well comprising a first portion and a second portion, the first portion being located on the first portion of the second well, the second portion being located on the second portion of the second well; a floating gate layer over the third well; a first doped region located in the first portion of the third well; a second doped region located in the first portion of the third well; a third doped region located in the first portion of the third well and adjacent to the first doped region; a trench isolation layer to isolate the first portion and the second portion of the second well and to isolate the first portion and the second portion of the third well; and a word line contact disposed on the second portion of the third well region for receiving a word line voltage.

Drawings

FIG. 1 is a top view of a memory device in an embodiment.

Fig. 2 is a cross-sectional view of the memory device of fig. 1 along line 2-2'.

Fig. 3 to 7 are waveform diagrams illustrating that the word line voltage is increased from the first voltage to the second voltage when the write operation is performed in different embodiments.

FIG. 8 is a flow chart of a method of fabricating a memory device according to an embodiment.

Wherein the reference numerals are as follows:

100 memory device

110 first well

120 second well

1201,1301 first part

1202,1302 second part

130 third well

140 fourth well

155 floating gate layer

161 first doped region

162 second doped region

163 third doped region

170 trench isolation layer

191 first oxide layer

192 second oxide layer

2-2' tangent line

800 method of manufacture

810 to 840

A first overlap area

B second overlap area

BL bit line contact

Length of L channel

SL source line contact

Periods T1, T2, T3, T4, T5, T91, T92, T93, T11, T12

TP, TP1, TP2, TP3, TP4 and TP5 pause intervals

VA, VB, VC, VD, VE voltages

VBL bit line voltage

VH second voltage

VL first voltage

VSL source line voltage

VW1 first well voltage

VW2 second well voltage

VWL word line voltage

W1 first well contact

W2 second well contact

WL word line contact

Detailed Description

In order to address the above-mentioned problems, embodiments provide a memory device and an operating method thereof, so as to achieve the effects of saving area, increasing access speed, reducing manufacturing cost, and saving power. FIG. 1 is a top view of a memory device 100, in an embodiment. Fig. 2 is a cross-sectional view of the memory device 100 of fig. 1 along line 2-2'. Fig. 1 and 2 are simplified schematic diagrams for illustrating an embodiment, but not for showing and limiting the detailed construction of the device.

The memory device 100 includes a first well 110, a second well 120, a third well 130, a floating gate layer 155, a first doped region 161, a second doped region 162, a third doped region 163, and a trench isolation layer 170. The second well 120 is located on the first well 110 and includes a first portion 1201 and a second portion 1202. The third well 130 includes a first portion 1301 and a second portion 1302, wherein the first portion 1301 is located on the first portion 1201 of the second well 120, and the second portion 1302 is located on the second portion 1202 of the second well 120. The floating gate layer 155 is located over the third well 130. The first doped region 161, the second doped region 162 and the third doped region 163 are located in the first portion 1301 of the third well 130, and the third doped region 163 is adjacent to the first doped region 161. The trench isolation layer 170 is used to isolate the first portion 1201 and the second portion 1202 of the second well 120, and isolate the first portion 1301 and the second portion 1302 of the third well 130. The trench isolation layer 170 may be a shallow trench isolation layer.

According to an embodiment, the first well 110 may be a p-type well, and the second well 120 and the third well 130 may be n-type wells. The memory device 100 may be a non-volatile memory.

As shown in fig. 2, according to the embodiment, the memory device 100 may further include a fourth well 140 selectively located below the first well 110 and having a doping type different from that of the first well; for example, the fourth well 140 may be a deep n-well. The fourth well 140 may be used when circuits other than a memory are manufactured.

According to an embodiment, as shown in fig. 2, the memory device 100 further includes a first oxide layer 191 and a second oxide layer 192. The first oxide layer 191 is located between the first portion 1301 of the third well 130 and the floating gate layer 155, and the second oxide layer 192 is located between the second portion 1302 of the third well 130 and the floating gate layer 155.

As shown in fig. 1 and 2, the floating gate layer 155 and the first portion 1301 of the third well 130 have a first overlapping area a, and the floating gate layer 155 and the second portion 1302 of the third well 130 have a second overlapping area B; and the first overlapping area a is smaller than the second overlapping area B. For example, the ratio of the first overlapping area a to the second overlapping area B may be approximately 1 to 5, or 1 to 10. According to an embodiment, the second overlapping area B corresponds to the second oxide layer 192, and the second oxide layer 192 may be a coupling gate layer, also called a control gate layer, of the memory device 110.

As shown in fig. 2, the memory device 100 may further include a source line contact (contact) SL, a bit line contact BL, and a word line contact WL. The source line contact SL is disposed at a contact surface between the first doped region 161 and the third doped region 163, coupled to a source line, and configured to receive a source line voltage VSL. The bit line contact BL is disposed on the second doped region 162, coupled to the bit line, and configured to receive the bit line voltage VBL. The word line contact WL is disposed on the second portion 1302 of the third well 130, coupled to the word line, and configured to receive a word line voltage VWL.

The memory device 100 may optionally further include a first well contact W1 coupled to the first well 110 for receiving a first well voltage VW 1. The memory device 100 may optionally further comprise a second well contact W2 coupled to the first portion 1201 of the second well 120 and configured to receive a second well voltage VW 2.

Since the second overlapping area B is sufficient to form a good planar-type capacitor, in the embodiment, when performing a write operation, the word line voltage VWL may use a ramp voltage (ramp voltage) to increase the write speed and reduce the write current, thereby achieving both the access speed and the power consumption saving. The waveform of the ramp-up voltage will be described later.

For example, the first and second

doped regions

161 and 162 may be p-type doped regions (which may be denoted as p +), and the third doped region 163 may be an n-type doped region (which may be denoted as n +).

In fig. 2, the first doped region 161, the second doped region 162 and the channel between the first doped region 161 and the second doped region 162 may form a transistor structure (e.g., a PNP transistor). As shown in fig. 2, each memory cell in the memory device 100 may include only one transistor, and thus may be referred to as a 1T structure. The memory device 100 of the embodiment may thus have a smaller size compared to a conventional memory cell, which often has to comprise at least two transistors, hence the 2T structure. In addition, by using the first well 110, the second well 120 and the third well 130, the channel length L between the first doped region 161 and the second doped region 162 can be shorter than that of the standard device, thereby further reducing the area of the memory device 100.

Table 1 shows the operating voltages described in fig. 2 and 3. As shown in Table 1, operating the memory device 100 may be as follows.

When performing a write operation, the adjustable word line voltage VWL is raised (ramp) from a first voltage to a second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, and the bit line voltage VBL and the first well voltage VW1 are adjusted to the reference voltage VF.

When a read operation is performed, the source line voltage VSL is adjusted to the read voltage Vrd, the bit line voltage VBL is adjusted to a low voltage (e.g., 0.4 volts), the word line voltage VWL is adjusted to a fixed voltage, and the first well voltage VW1 is adjusted to the reference voltage VF.

When performing an erase operation, the source line voltage VSL is adjusted to the erase voltage Vee, the bit line voltage is adjusted to the floating voltage VFL, and the word line voltage VWL and the first well voltage VW1 are adjusted to the reference voltage VF.

(Table 1, voltage values in parentheses are only examples)

In fig. 2 and table 1, the write operation, the erase operation, and the read operation are not performed simultaneously. According to an embodiment, the low voltage described in table 1 may be lower than the read voltage Vrd, the read voltage Vrd may be lower than the write voltage Vpp, and the write voltage Vpp may be less than the erase voltage Vee. The thicker the oxide layers (e.g., the first oxide layer 191 and the second oxide layer 192), the higher the erase voltage Vee and the write voltage Vpp.

Table 2 shows the operating voltages of fig. 2 in another embodiment. As shown in Table 2, operating the memory device 100 may be as follows.

When performing a write operation, the word line voltage VWL is adjusted to be raised from the first voltage to the second voltage, the source line voltage VSL is adjusted to be the write voltage Vpp, and the bit line voltage VBL and the first well voltage VW1 are adjusted to be the reference voltage VF.

When performing an erase operation, the source line voltage VSL is adjusted to the erase voltage Vee, the bit line voltage VBL is adjusted to the reference voltage VF, and the word line voltage VWL and the first well voltage VW1 are adjusted to fixed voltages (e.g., between +1 volt and-2 volts).

When a read operation is performed, the source line voltage VSL is adjusted to the read voltage Vrd, the bit line voltage VBL is adjusted to a low voltage (e.g., 0.4 volts), the word line voltage VWL is adjusted to a fixed voltage (e.g., between 0 volts and 5 volts), and the first well voltage VW1 is adjusted to the reference voltage VF.

(Table 2, voltage values in parentheses are only examples)

In fig. 2 and 2, the write operation, the erase operation, and the read operation are not performed simultaneously, and the erase operation is a Channel Hot Hole (CHH) erase operation. According to an embodiment, the low voltage described in Table 2 can be lower than the read voltage Vrd, the write voltage Vpp can be close to the erase voltage Vee, and the fixed voltage can be between a positive voltage and a negative voltage (e.g., +1 volt and-2 volts).

Table 3 shows the operating voltages of FIG. 2 in another embodiment. As shown in Table 3, operating the memory device 100 may be as follows.

When performing a write operation, the word line voltage VWL is adjusted to be raised from a first voltage to a second voltage, the source line voltage VSL is adjusted to be the write voltage Vpp, the bit line voltage VBL and the first well voltage VW1 are adjusted to be the reference voltage VF, and the second well voltage VW2 is adjusted (e.g., same as the write voltage Vpp).

When performing an erase operation, the source line voltage VSL is adjusted to the erase voltage Vee, the bit line voltage VBL is adjusted (e.g., the same as the erase voltage Vee), the word line voltage VWL is adjusted to a fixed voltage, the first well voltage VW1 is adjusted to a fixed voltage, and the second well voltage VW2 is adjusted to the reference voltage VF.

When a read operation is performed, the source line voltage VSL is adjusted to the read voltage Vrd, the bit line voltage VBL is adjusted to a low voltage, the word line voltage VWL is adjusted to a fixed voltage, the first well voltage VW1 is adjusted to the reference voltage VF, and the second well voltage VW2 (e.g., the same as the read voltage Vrd) is adjusted.

(Table 3, voltage values in parentheses are only examples)

In fig. 2 and 3, the write operation, the erase operation, and the read operation are not performed simultaneously, and the erase operation may be a band-to-band hot hole (BBHH) erase operation. According to an embodiment, the low voltage described in table 3 may be less than the read voltage Vrd, and the read voltage Vrd may be less than the write voltage Vpp. In an erase operation, the source line voltage VSL, the bit line voltage VBL, the word line voltage VWL, and the first well voltage VW1 may be negative voltages. According to an embodiment, the source line voltage VSL may be substantially equal to the second well voltage VW2 when performing a write operation and performing a read operation.

According to the embodiment, the reference voltage VF described in table 1, table 2 and table 3 can be zero voltage or ground voltage. In tables 1, 2 and 3, the voltage values in parentheses are only examples to help understanding the principles of the embodiments, and do not limit the scope of the embodiments; the voltage values used may be adjusted according to requirements, manufacturing processes and statistical results. Each of the write voltage Vpp, the erase voltage Vee, and the read voltage Vrd described above may be different in the case of table 1, table 2, and table 3.

Fig. 3-7 are waveforms illustrating that the word line voltage VWL is raised (ramp) from the first voltage to the second voltage when the write operation is performed in tables 1, 2, and 3 according to various embodiments. According to an embodiment, the waveform of the word line voltage VWL rising from the first voltage VL to the second voltage VH when the write operation is performed may include a straight-rising waveform, a stepped waveform, and/or an arc-shaped waveform. The first voltage VL and the second voltage VH in fig. 3 to 7 may correspond to the first voltage and the second voltage in the tables 1 to 3.

In fig. 6 to 10, the first voltage VL may be an initial voltage at which the word line voltage VWL starts to rise, and according to an embodiment, the first voltage VL may be set to be lower than the source line voltage VSL by a predetermined value when the write operation is performed; the predetermined value may be, for example, 0.5 volts to 2 volts.

The write operation can be accelerated when the word line voltage VWL rises faster, but the probability of occurrence of stuck-at fault also rises, so the slope of the rising waveform of the word line voltage VWL can be adjusted according to the actual situation to achieve both the speed and accuracy of the operation.

As shown in fig. 3 and 5, the waveform in which the word line voltage VWL rises may include a straight-line waveform. As shown in fig. 4 and 6, the waveform of the rising word line voltage VWL may include an arc-shaped waveform. As shown in fig. 7, the waveform in which the word line voltage VWL rises may include a stepped waveform.

According to an embodiment, the waveform of the word line voltage VWL rising from the first voltage to the second voltage when the write operation is performed may include at least one pause period, as shown in FIG. 5, FIG. 6, and FIG. 7. The method of operating the memory device 100 further includes verifying whether the potential of the word line reaches a predetermined potential during the pause interval.

For example, in fig. 5 and 6, it can be verified whether the potential of the word line reaches a predetermined potential during the pause interval TP. For example, in FIG. 7, the word line voltage VWL can be raised in a ladder waveform from the first voltage VL to the voltage VA in the time period T1, and it is verified whether the potential of the word line reaches the predetermined potential or not in the pause interval TP 1. If not, the word line voltage VWL can be raised to the voltage VB at the subsequent time period T2, and whether the potential of the word line reaches the predetermined potential is verified at the pause interval TP 2. Similarly, the word line voltage VWL can be raised to the voltage VC at time T3, the word line potential can be verified at pause interval TP3, the word line voltage VWL can be raised to the voltage VD at time T4, the word line potential can be verified at pause interval TP4, the word line voltage VWL can be raised to the voltage VE at time T5, and the word line potential can be verified at pause interval TP 5. In FIG. 7, during the pause interval TP5, the word line voltage VWL is not raised if the potential of the word line is verified to reach the predetermined potential, i.e., the second voltage VH.

In fig. 5 to 7, the time for each voltage application can be adjusted. For example, the lengths of the periods T91, T92, and T93 of fig. 6 may be the same or different; the lengths of the periods T11 and T12 of fig. 10 may be the same or different.

FIG. 8 is a flow chart of a method 800 of fabricating the memory device 100 according to an embodiment. The manufacturing method 800 may include at least the following steps:

step 810: performing an oxidation process to generate a first oxide layer 191 and a second oxide layer 192;

step 820: generating at least one trench isolation layer;

step 830: executing a planarization program; and

step 840: using the same mask, a plurality of ion implantations are performed to create the first well 110, the second well 120, and the third well 130, respectively.

According to an embodiment, the first well 110, the second well 120, and the third well 130 may be created by ion implantation using the same mask after performing an oxidation process, creating a trench isolation layer (e.g., the trench isolation layer 170), and performing a planarization process (e.g., a Chemical Mechanical Planarization (CMP)). Compared to the standard device manufacturing, the masks used to create the first well 110, the second well 120, and the third well 130 are additional masks, and according to the embodiment, only one additional mask is needed to form the first well 110, the second well 120, and the third well 130, so the manufacturing process can be simplified. After the first well 110, the second well 120 and the third well 130 are created, ion implantation may be performed to create wells for logic devices. According to an embodiment, an ion implantation may be further performed to create the fourth well 140.

According to an embodiment, a Thinning down process may be further performed to reduce the thickness of the first oxide layer 191 and the second oxide layer 192, thereby reducing the source line voltage VSL required for performing the write operation and the erase operation.

As shown in table 1, if the thicknesses of the first oxide layer 191 and the second oxide layer 192 are reduced during the manufacturing process, the write voltage Vpp can be reduced, for example, to less than 5.5 volts, and the erase voltage Vee can be reduced, for example, to less than 13 volts. The reduced thickness of the first oxide 191 and the second oxide 192 of the memory device 100 may be greater than the oxide thickness of the core (core) device and less than the oxide thickness of the input/output (I/O) device.

In summary, the memory device 100 according to the embodiment can make the memory cell include only a single transistor by using the first well 110, the second well 120 and the third well 130, and the channel length of the transistor can be shortened, so that the size of the memory cell can be reduced. Since the write current can be reduced, the power consumption can be effectively reduced. Since the coupling gate of the memory device 100 has good plate capacitance, the word line voltage VWL can use a rising waveform, thereby speeding up the write operation. By using the first well 110, the second well 120 and the third well 130, the punch-through problem can be effectively prevented, thereby improving the reliability. The first well 110, the second well 120 and the third well 130 can be formed by using the same mask, so that the cost and complexity of the manufacturing process can be effectively reduced. According to the experiment, after 10000 times of accesses, the operation current and voltage are not significantly reduced, so the endurance is very good. By the operation method provided by the embodiment, the potential of the word line can be verified in real time when the word line voltage VWL is increased, so that the operation and verification are convenient. The memory device 100 supports a variety of operating principles and is highly flexible in operation. Thus, embodiments of the present invention provide memory devices and methods of manufacture that are useful for reducing many of the long-term challenges in the art.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A memory device, the memory device comprising:

a first well;

the second trap is positioned on the first trap and comprises a first part and a second part;

a third well comprising a first portion and a second portion, the first portion being located on the first portion of the second well, the second portion being located on the second portion of the second well;

a floating gate layer over the third well;

a first doped region located in the first portion of the third well;

a second doped region located in the first portion of the third well;

a third doped region located in the first portion of the third well and adjacent to the first doped region;

a trench isolation layer to isolate the first portion and the second portion of the second well and to isolate the first portion and the second portion of the third well; and

a word line contact disposed on the second portion of the third well region for receiving a word line voltage.

2. The memory device of claim 1, wherein the first well is a p-type well, and the second well and the third well are n-type wells.

3. The memory device of claim 1, further comprising:

and the fourth well is positioned below the first well and has a doping type different from that of the first well.

4. The memory device of claim 1, wherein the floating gate layer and the first portion of the third well have a first overlap area; the floating gate layer and the second portion of the third well have a second overlapping area; and the first overlapping area is smaller than the second overlapping area.

5. The memory device of claim 1, further comprising:

a first oxide layer between the first portion of the third well and the floating gate layer; and

a second oxide layer between the second portion of the third well and the floating gate layer.

6. The memory device of claim 5, further comprising:

and the source line contact is arranged on the contact surface between the first doped region and the third doped region and used for receiving a source line voltage.

7. The memory device of claim 6, further comprising:

and the bit line contact is arranged on the second doped region and used for receiving bit line voltage.

8. The memory device of claim 7, further comprising:

the first well contact is arranged in the first well to receive a first well voltage.

9. The memory device of claim 8, further comprising:

a second well contact disposed in the first portion of the second well to receive a second well voltage.

10. The memory device of claim 1, wherein the first doped region and the second doped region are p-type doped regions, and the third doped region is an n-type doped region.