TW202139434A - Memory device and manufacturing method thereof - Google Patents

Abstract

A memory device includes a first well, a second well, a third well, a floating gate layer, a first doped region, a second doped region, a third doped region, a trench isolation layer and a word line contact. The second well is on the first well and includes a first portion and a second portion. The third well includes a first portion and a second portion respectively on the first portion and the second portion of the second well. The first doped region, the second doped region and the third doped region are located at the first portion of the third well. The trench isolation layer is used to isolate the first portion and the second portion of the second well and isolate the first portion and the second portion of the third well. The word line contact is disposed on the second portion of the third well and used to receive a word line voltage.

Description

Memory device and manufacturing method thereof

The present invention relates to a memory device and a manufacturing method thereof, and particularly refers to a memory device including a plurality of wells generated using the same photomask and a manufacturing method thereof.

With the continuous advancement of electronic products, the importance of memory is also increasing. Regarding the characteristics of memory devices, common requirements are expected to reduce the area occupied by the memory, increase the access speed, and reduce power consumption.

However, achieving the above goals is not easy. The conventional memory devices in this field often need to include at least two transistors, and need to be equipped with additional erasing gates for normal operation, so the area of the device is difficult to reduce. In order to manufacture the above structure, compared to manufacturing standard components, two or more photomasks are additionally used, which makes it difficult to reduce the manufacturing process cost.

Therefore, there is still a lack of suitable solutions in this field to achieve the effects of saving area, improving access speed, reducing manufacturing cost, and saving power consumption.

The embodiment provides a memory device including a first well, a second well, a third well, a floating gate layer, a first doped region, a second doped region, a third doped region, a trench isolation layer, and a word Element line contact. The second well is located on the first well and includes a first part and a second part. The third well includes a first portion located on the first portion of the second well, and a second portion located on the second portion of the second well. The floating gate layer is located above the third well. The first doped region is located in the first part of the third well. The second doped region is located in the first part of the third well. The third doped region is located in the first part of the third well and is adjacent to the first doped region. The trench isolation layer is used to isolate the first part and the second part of the second well, and isolate the first part and the second part of the third well. The character line contact is arranged on the second part of the third well area, and is used for receiving a character line voltage.

The embodiment further provides a method of manufacturing a memory device, including performing an oxidation process to generate a first oxide layer and a second oxide layer; generating at least one trench isolation layer; performing a planarization process; and using the same light Cover, perform multiple ion implantation to generate a first well, a second well and a third well respectively. The second well is located on the first well, the third well is located on the second well, the trench isolation layer isolates a first part and a second part of the second well, and the trench isolation layer isolates A first part and a second part of the third well.

In order to solve the above-mentioned problems, the embodiments provide a memory device and a manufacturing method thereof, so as to save area, increase access speed, reduce manufacturing cost, and save power. Figure 1 is a top view of the memory device 100 in the embodiment. Fig. 2 is a cross-sectional view of the memory device 100 in Fig. 1 along the line 2-2'. Fig. 1 and Fig. 2 are simplified schematic diagrams to illustrate the embodiment, rather than to show and limit the detailed structure of the device.

The memory device 100 includes a first well 110, a second well 120, a third well 130, a floating gate layer 155, a first doped region 161, a second doped region 162, a third doped region 163, and trench isolation层170. The second well 120 is located on the first well 110 and includes a first part 1201 and a second part 1202. The third well 130 includes a first portion 1301 and a second portion 1302, wherein the first portion 1301 is located on the first portion 1201 of the second well 120, and the second portion 1302 is located on the second portion 1202 of the second well 120. The floating gate layer 155 is located above the third well 130. The first doped region 161, the second doped region 162 and the third doped region 163 are located in the first portion 1301 of the third well 130, and the third doped region 163 is adjacent to the first doped region 161. The trench isolation layer 170 is used to isolate the first part 1201 and the second part 1202 of the second well 120 and to isolate the first part 1301 and the second part 1302 of the third well 130. The trench isolation layer 170 may be a shallow trench isolation layer.

According to an embodiment, the first well 110 may be a p-type well, and the second well 120 and the third well 130 may be n-type wells. The memory device 100 may be a non-volatile memory.

As shown in FIG. 2, according to the embodiment, the memory device 100 may optionally further include a fourth well 140, which is located below the first well 110 and has a doping type different from that of the first well; for example, the first well 140 The four well 140 may be a deep n-type well. When manufacturing circuits other than memory, the fourth well 140 can be used.

According to an embodiment, as shown in FIG. 2, the memory device 100 further includes a first oxide layer 191 and a second oxide layer 192. The first oxide layer 191 is located between the first portion 1301 of the third well 130 and the floating gate layer 155, and the second oxide layer 192 is located between the second portion 1302 of the third well 130 and the floating gate layer 155.

As shown in Figures 1 and 2, the floating gate layer 155 and the first part 1301 of the third well 130 have a first overlap area A, and the floating gate layer 155 and the second part 1302 of the third well 130 have a second Overlap area B; and the first overlap area A is smaller than the second overlap area B. For example, the ratio of the first overlap area A to the second overlap area B may be approximately 1:5, or 1:10. According to an embodiment, the second overlap area B corresponds to the second oxide layer 192, and the second oxide layer 192 may be a coupling gate layer of the memory device 110, also called a control gate layer.

As shown in FIG. 2, the memory device 100 may further include a source line contact SL, a bit line contact BL, and a word line contact WL. The source line contact SL is disposed on the contact surface between the first doped region 161 and the third doped region 163, is coupled to the source line, and is used for receiving the source line voltage VSL. The bit line contact BL is disposed on the second doped region 162, is coupled to the bit line, and is used for receiving the bit line voltage VBL. The word line contact WL is disposed on the second part 1302 of the third well region 130, is coupled to the word line, and is used for receiving the word line voltage VWL.

The memory device 100 may optionally further include a first well contact W1 coupled to the first well 110 and used for receiving the first well voltage VW1. The memory device 100 may optionally further include a second well contact W2, coupled to the first part 1201 of the second well 120, and used for receiving the second well voltage VW2.

Since the second overlap area B is sufficient to form a good planar-type capacitor, in the embodiment, when the writing operation is performed, the word line voltage VWL can use a ramping voltage to increase the writing speed , And reduce the write current, thereby accelerating access and saving power consumption at the same time. The waveform of the ramp voltage will be described later.

For example, the first doped region 161 and the second doped region 162 may be p-type doped regions (may be expressed as p+), and the third doped region 163 may be n-type doped regions (may be expressed as n+ ).

In Figure 2, the first doped region 161, the second doped region 162, and the channel between the first doped region 161 and the second doped region 162 can form a transistor structure (for example, a PNP transistor). As shown in FIG. 2, in the memory device 100, each memory cell can only include one transistor, so it can be called a 1T structure. Compared with conventional memory cells that often include at least two transistors (hence the 2T structure), the memory device 100 of the embodiment can therefore have a smaller size. In addition, by using the first well 110, the second well 120, and the third well 130, the channel length L between the first doped region 161 and the second doped region 162 can be shorter than the channel length of a standard device. The area of the memory device 100 can be further reduced.

Table 1 shows the operating voltages described in Figures 2 and 3. As shown in Table 1, the operation of the memory device 100 can be as follows.

When a write operation is performed, the adjustable word line voltage VWL rises from the first voltage (ramp) to the second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, and the bit line voltage VBL and the first well are adjusted The voltage VW1 is the reference voltage VF.

When performing a read operation, the source line voltage VSL can be adjusted to the read voltage Vrd, the bit line voltage VBL is adjusted to a low voltage (for example, 0.4 volts), the word line voltage VWL is adjusted to a fixed voltage, and the first well is adjusted The voltage VW1 is the reference voltage VF.

When performing an erase operation, the source line voltage VSL can be adjusted to the erase voltage Vee, the bit line voltage is adjusted to the floating voltage VFL, and the word line voltage VWL and the first well voltage VW1 are adjusted to the reference voltage VF. Source line voltage VSL Bit line voltage VBL Character line voltage VWL The first well voltage VW1 Write operation Write voltage Vpp (for example, 5.5 volts) Reference voltage VF (for example, 0 volts) Rise from the first voltage (for example, 4.3 volts) to the second voltage (for example, 7.5 volts) Reference voltage VF (for example, 0 volts) Erase operation Erase voltage Vee (for example, 13 volts) Floating voltage VFL Reference voltage VF (for example, 0 volts) Reference voltage VF (for example, 0 volts) Read operation Read voltage Vrd (for example, 2.2 volts) Low voltage (for example, 0.4 volts) Fixed voltage (for example, between 0 and 5 volts) Reference voltage VF (for example, 0 volts)

(In Table 1, the voltage values in parentheses are just examples)

In Figure 2 and Table 1, the write operation, erase operation, and read operation will not be executed at the same time. According to embodiments, the low voltage described in Table 1 can be lower than the read voltage Vrd, the read voltage Vrd can be lower than the write voltage Vpp, and the write voltage Vpp can be less than the erase voltage Vee. When the oxide layer (such as the first oxide layer 191 and the second oxide layer 192) is thicker, the erase voltage Vee and the write voltage Vpp are higher.

Table 2 shows the operating voltage described in Figure 2 in another embodiment. As shown in Table 2, the operation of the memory device 100 can be as follows.

When the write operation is performed, the word line voltage VWL is adjusted from the first voltage to the second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, and the bit line voltage VBL and the first well voltage VW1 are adjusted as a reference Voltage VF.

When the erase operation is performed, the source line voltage VSL is adjusted to the erase voltage Vee, the bit line voltage VBL is adjusted to the reference voltage VF, and the word line voltage VWL and the first well voltage VW1 are adjusted to a fixed voltage (for example, between Between +1 volt and -2 volt).

When performing a read operation, adjust the source line voltage VSL to the read voltage Vrd, adjust the bit line voltage VBL to a low voltage (for example, 0.4 volts), and adjust the word line voltage VWL to a fixed voltage (for example, between 0 volts and 5 volts), and adjust the first well voltage VW1 to the reference voltage VF. Source line voltage VSL Bit line voltage VBL Character line voltage VWL The first well voltage VW1 Write operation Write voltage Vpp (for example, 5.5 volts) Reference voltage VF (for example, 0 volts) Rise from the first voltage (for example, 4.3 volts) to the second voltage (for example, 7.5 volts) Reference voltage VF (for example, 0 volts) Erase operation Erase voltage Vee (for example, a fixed voltage between 5 volts and 6 volts) Reference voltage VF (for example, 0 volts) Fixed voltage (for example, between +1 volt and -2 volt) Fixed voltage (for example, the same as the word line voltage VWL) Read operation Read voltage Vrd (for example, 2.2 volts) Low voltage (for example, 0.4 volts) Fixed voltage (for example, between 0 and 5 volts) Reference voltage VF (for example, 0 volts)

(In Table 2, the voltage values in parentheses are just examples)

In Figure 2 and Table 2, the write operation, erase operation, and read operation will not be performed at the same time, and the erase operation is a channel hot hole (CHH) erase operation. According to embodiments, the low voltage described in Table 2 can be lower than the read voltage Vrd, the write voltage Vpp can be close to the erase voltage Vee, and the fixed voltage can be between a positive voltage and a negative voltage (for example, +1 volt and- 2 volts).

Table 3 shows the operating voltage of Figure 2 in another embodiment. As shown in Table 3, the operation of the memory device 100 can be as follows.

When the write operation is performed, the word line voltage VWL is adjusted from the first voltage to the second voltage, the source line voltage VSL is adjusted to the write voltage Vpp, and the bit line voltage VBL and the first well voltage VW1 are adjusted as the reference voltage VF, and adjust the second well voltage VW2 (for example, the same as the write voltage Vpp).

When performing an erase operation, adjust the source line voltage VSL to the erase voltage Vee, adjust the bit line voltage VBL (for example, the same as the erase voltage Vee), adjust the word line voltage VWL to a fixed voltage, and adjust the first well The voltage VW1 is a fixed voltage, and the adjusted second well voltage VW2 is the reference voltage VF.

When performing a read operation, adjust the source line voltage VSL to the read voltage Vrd, adjust the bit line voltage VBL to a low voltage, adjust the word line voltage VWL to a fixed voltage, adjust the first well voltage VW1 to the reference voltage VF, And adjust the second well voltage VW2 (for example, the same as the read voltage Vrd). Source line voltage VSL Bit line voltage VBL Character line voltage VWL The first well voltage VW1 Second well voltage VW2 Write operation Write voltage Vpp (for example, 5.5 volts) Reference voltage VF (for example, 0 volts) Rise from the first voltage (for example, 4.3 volts) to the second voltage (for example, 7.5 volts) Reference voltage VF (for example, 0 volts) For example, the same as the write voltage Vpp Erase operation Erase voltage Vee (for example -5.5 volts) For example, the same as the erase voltage Vee Fixed voltage (for example, between -5 volts and -6 volts) Fixed voltage (for example, between -5 volts and -6 volts) Reference voltage VF (for example, 0 volts) Read operation Read voltage Vrd (for example, 2.2 volts) Low voltage (for example, 0.4 volts) Fixed voltage (for example, between 0 and 5 volts) Reference voltage VF (for example, 0 volts) For example, the same as the read voltage Vrd

(In Table 3, the voltage values in parentheses are just examples)

In Figure 2 and Table 3, the write operation, erase operation, and read operation will not be performed at the same time. The erase operation can be a band-to-band hot hole (BBHH) erase operation. According to an embodiment, the low voltage described in Table 3 can be less than the read voltage Vrd, and the read voltage Vrd can be less than the write voltage Vpp. During the erasing operation, the source line voltage VSL, the bit line voltage VBL, the word line voltage VWL, and the first well voltage VW1 may be negative voltages. According to an embodiment, when performing a writing operation and performing a read operation, the source line voltage VSL may be substantially equal to the second well voltage VW2.

According to the embodiment, the reference voltage VF described in Table 1, Table 2, and Table 3 may be zero voltage or ground voltage. In Table 1, Table 2, and Table 3, the voltage values in parentheses are just examples to help understand the principles of the embodiments, not to limit the scope of the embodiments; the used can be adjusted according to requirements, manufacturing processes and statistical results The voltage value. Each of the above-mentioned write voltage Vpp, erase voltage Vee, and read voltage Vrd may be different in the case of Table 1, Table 2, and Table 3.

Figures 3 to 7 show that according to different embodiments, in Table 1, Table 2, and Table 3, when the write operation is performed, the word line voltage VWL rises from the first voltage (ramp) to the second voltage Waveform graph. According to an embodiment, when the writing operation is performed, the waveform of the word line voltage VWL rising from the first voltage VL to the second voltage VH may include a linear rising waveform, a ladder waveform, and/or an arc waveform. The first voltage VL and the second voltage VH in Figs. 3 to 7 may correspond to the first voltage and the second voltage in the first to third tables.

In FIGS. 6 to 10, the first voltage VL may be the initial voltage at which the word line voltage VWL starts to rise. According to an embodiment, when the write operation is performed, the first voltage VL may be set to be higher than the source line voltage VSL is lower by a predetermined value; the predetermined value may be, for example, 0.5 volts to 2 volts.

When the word line voltage VWL rises faster, the writing operation can be accelerated. However, the possibility of a stuck-at fault will also increase. Therefore, the word line voltage VWL can be adjusted according to the actual situation. The slope of the rising waveform can balance the speed and accuracy of the operation.

As shown in FIGS. 3 and 5, the rising waveform of the word line voltage VWL may include a linear waveform. As shown in Figs. 4 and 6, the rising waveform of the word line voltage VWL may include an arc-shaped waveform. As shown in Fig. 7, the rising waveform of the word line voltage VWL may include a ladder waveform.

According to an embodiment, when the writing operation is performed, the waveform of the word line voltage VWL rising from the first voltage to the second voltage may include at least one pause period, as shown in FIGS. 5, 6 and 7. The operating method of the memory device 100 further includes verifying whether the potential of the word line reaches a predetermined potential in the pause interval.

For example, in FIGS. 5 and 6, it can be verified in the pause interval TP whether the potential of the word line reaches a predetermined potential. For example, in Figure 7, the word line voltage VWL can be raised from the first voltage VL to the voltage VA in a ladder waveform during the time period T1, and it is verified whether the potential of the word line reaches a predetermined potential during the pause interval TP1. If not, the word line voltage VWL can be raised to the voltage VB in the subsequent period T2, and it is verified whether the potential of the word line reaches the predetermined potential in the pause period TP2. In the same way, the word line voltage VWL can be raised to the voltage VC in the time period T3, the word line voltage can be verified in the pause period TP3, the word line voltage VWL can be raised to the voltage VD in the time period T4, and the characters can be verified in the pause period TP4 The potential of the line, the word line voltage VWL is raised to the voltage VE in the period T5, and the potential of the word line is verified in the pause period TP5. In Figure 7, in the pause interval TP5, it is verified that the potential of the word line has reached the predetermined potential, that is, the second voltage VH, and the word line voltage VWL can no longer be increased.

In Figures 5 to 7, the time of each voltage application can be adjusted. For example, the lengths of the periods T91, T92, and T93 in Fig. 6 may be the same or different; the lengths of the periods T11 and T12 in Fig. 10 may be the same or different.

FIG. 8 is a flowchart of a manufacturing method 800 of the memory device 100 in the embodiment. The manufacturing method 800 may include at least the following steps:

Step 810: Perform an oxidation process to generate a first oxide layer 191 and a second oxide layer 192;

Step 820: Generate at least one trench isolation layer;

Step 830: Execute the flattening process; and

Step 840: Using the same mask, perform multiple ion implantation to generate the first well 110, the second well 120, and the third well 130 respectively.

According to an embodiment, after performing an oxidation process, generating a trench isolation layer (such as trench isolation layer 170), and performing a planarization process (such as a chemical mechanical planarization process, CMP), the same mask can be used for ion implantation, To generate the first well 110, the second well 120, and the third well 130. Compared with manufacturing standard components, the photomasks used to generate the first well 110, the second well 120, and the third well 130 are additional photomasks. According to the embodiment, only one additional photomask can be used to form the first well 110, The second well 120 and the third well 130 can simplify the manufacturing process. After the first well 110, the second well 120, and the third well 130 are generated, ion implantation can be performed to generate the wells required by the logic element. According to an embodiment, ion implantation may be additionally performed to generate the fourth well 140.

According to the embodiment, a thinning down process can be performed to reduce the thickness of the first oxide layer 191 and the second oxide layer 192, thereby reducing the source line voltage required for the writing and erasing operations VSL.

For example, in Table 1 above, if the thickness of the first oxide layer 191 and the second oxide layer 192 is reduced during the manufacturing process, the writing voltage Vpp can be reduced, for example, less than 5.5 volts, and the erasing voltage Vee can be Decrease, for example, less than 13 volts. After the thicknesses of the first oxide layer 191 and the second oxide layer 192 of the memory device 100 are reduced, the thickness can be greater than the oxide layer thickness of the core device and smaller than the oxide layer thickness of the input/output (I/O) device.

In general, by using the first well 110, the second well 120, and the third well 130 of the memory device 100 provided by the embodiment, the memory unit can only include a single transistor, and the channel length of the transistor can be shortened. Therefore, the size of the memory unit can be reduced. Because the write current can be reduced, power consumption can be effectively reduced. Since the coupling gate of the memory device 100 has a good plate capacitance, the word line voltage VWL can use a rising waveform, thereby speeding up the writing operation. By using the first well 110, the second well 120, and the third well 130, the breakdown problem can be effectively prevented, so the reliability can be improved. The first well 110, the second well 120, and the third well 130 can be produced using the same mask, so the cost and complexity of the manufacturing process can be effectively reduced. According to experiments, the operating current and voltage of the memory device 100 have not decreased significantly after 10,000 accesses, so the durability is very good. With the operation method provided by the embodiment, the potential of the word line can be verified immediately when the word line voltage VWL is increased, which is convenient for operation and verification. The memory device 100 can support a variety of operating principles, so it has a high degree of flexibility in operation. Therefore, the memory device and the manufacturing method provided by the embodiments are actually helpful for reducing many long-term problems in the field. The foregoing descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made in accordance with the scope of the patent application of the present invention shall fall within the scope of the present invention.

100: Memory device 110: First Well 120: Second Well 1201, 1301: Part One 1202, 1302: part two 130: The Third Well 140: The Fourth Well 155: Floating gate layer 161: first doped region 162: second doped region 163: third doped region 170: trench isolation layer 191: first oxide layer 192: second oxide layer 2-2': Tangent 800: manufacturing method 810 to 840: steps A: The first overlap area B: second overlap area BL: bit line contact L: Channel length SL: Source line contact T1, T2, T3, T4, T5, T91, T92, T93, T11, T12: time period TP, TP1, TP2, TP3, TP4, TP5: pause interval VA, VB, VC, VD, VE: voltage VBL: bit line voltage VH: second voltage VL: first voltage VSL: Source line voltage VW1: voltage of the first well VW2: second well voltage VWL: Character line voltage W1: The first well contact W2: second well contact WL: Character line contact

Figure 1 is a top view of the memory device in the embodiment. Fig. 2 is a cross-sectional view of the memory device of Fig. 1 along the line 2-2'. 3 to 7 are waveform diagrams of the word line voltage rising from the first voltage to the second voltage when the write operation is performed in different embodiments. Fig. 8 is a flowchart of the manufacturing method of the memory device in the embodiment.

100: Memory device

110: First Well

120: Second Well

1201, 1301: Part One

1202, 1302: part two

130: The Third Well

140: The Fourth Well

155: Floating gate layer

161: first doped region

162: second doped region

163: third doped region

170: trench isolation layer

191: first oxide layer

192: second oxide layer

BL: bit line contact

L: Channel length

SL: Source line contact

VBL: bit line voltage

VSL: Source line voltage

VW1: voltage of the first well

VW2: second well voltage

VWL: Character line voltage

W1: The first well contact

W2: second well contact

WL: Character line contact

Claims (13)

A memory device including: A first well A second well, located on the first well, including a first part and a second part; A third well, including a first part and a second part, the first step is located on the first part of the second well, and the second part is located on the second part of the second well; A floating gate layer located above the third well; A first doped region located in the first part of the third well; A second doped region located in the first part of the third well; A third doped region located in the first part of the third well and adjacent to the first doped region; A trench isolation layer for isolating the first part and the second part of the second well, and isolating the first part and the second part of the third well; and A character line contact is arranged on the second part of the third well area for receiving a character line voltage. The memory device according to claim 1, wherein the first well is a p-type well, and the second well and the third well are n-type wells. The memory device described in claim 1, further comprising: A fourth well is located below the first well and has a doping type different from that of the first well. The memory device according to claim 1, wherein the floating gate layer and the first part of the third well have a first overlap area; the floating gate layer and the second part of the third well have a second Overlapping area; and the first overlapping area is smaller than the second overlapping area. The memory device described in claim 1, further comprising: A first oxide layer located between the first part of the third well and the floating gate layer; and A second oxide layer is located between the second part of the third well and the floating gate layer. The memory device according to claim 5, further comprising: A source line contact is arranged on a contact surface between the first doped region and the third doped region for receiving a source line voltage. The memory device according to claim 6, further comprising: A bit line contact is arranged on the second doped area for receiving a bit line voltage. The memory device according to claim 7, further comprising: A first well contact is arranged on the first well to receive a first well voltage. The memory device according to claim 8, further comprising: A second well contact is arranged on the first part of the second well to receive a second well voltage. The memory device according to claim 1, wherein the first doped region and the second doped region are p-type doped regions, and the third doped region is an n-type doped region. A manufacturing method of a memory device includes: Performing an oxidation process to generate a first oxide layer and a second oxide layer; Generating at least one trench isolation layer; Perform a flattening process; and Use a mask to perform multiple ion implantation to generate a first well, a second well and a third well respectively; The second well is located on the first well, the third well is located on the second well, the trench isolation layer isolates a first part and a second part of the second well, and the trench isolation layer isolates A first part and a second part of the third well. The manufacturing method according to claim 11, further comprising: A thinning process is performed to reduce the thickness of the first oxide layer and the second oxide layer. The manufacturing method according to claim 11, further comprising: Perform ion implantation to generate a fourth well, wherein the fourth well is located below the first well and has a different doping type from the first well.

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