CN113517343A - Method for manufacturing transistor, basic memory cell, and dynamic random access memory - Google Patents
Method for manufacturing transistor, basic memory cell, and dynamic random access memory Download PDFInfo
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- CN113517343A CN113517343A CN202110410507.4A CN202110410507A CN113517343A CN 113517343 A CN113517343 A CN 113517343A CN 202110410507 A CN202110410507 A CN 202110410507A CN 113517343 A CN113517343 A CN 113517343A
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- columnar body
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 17
- 239000000463 material Substances 0.000 claims description 10
- 239000003990 capacitor Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052710 silicon Inorganic materials 0.000 claims description 6
- 239000010703 silicon Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 239000007769 metal material Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 description 8
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000001704 evaporation Methods 0.000 description 3
- 230000008020 evaporation Effects 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000005289 physical deposition Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000005034 decoration Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Abstract
The invention provides a manufacturing method of a transistor, the transistor, a basic memory cell and a dynamic random access memory. The method comprises the following steps: forming a conductive channel attached to the insulating side wall, wherein the conductive channel comprises a columnar body and end parts on two sides, and at least one end part is arranged in a protruding manner; forming a gate insulating layer which semi-surrounds the columnar body on the side surface of the columnar body, and exposing two ends of the conductive channel; forming a gate electrode covering the gate insulating layer on the side surface of the columnar body; a source electrode and a drain electrode are formed at both end portions of the conductive channel. The technical scheme is that the transistor in the horizontal direction in the prior art is improved to be in the vertical direction, so that the area occupied by a single transistor in the horizontal direction is reduced, the number of the transistors in a unit area is increased, and the transistor density is improved.
Description
Technical Field
The present invention relates to the field of semiconductor processes, and more particularly, to a method for manufacturing a transistor, a basic memory cell, and a dynamic random access memory.
Background
The basic unit of the dynamic random access memory is shown in FIG. 1A, and the memory is formed by the array structure shown in FIG. 1B. The basic unit is commonly referred to as the 1T1C structure. The 1T, i.e., the transistor, mainly has two structures, i.e., a planar transistor shown in fig. 2A and a buried channel array transistor shown in fig. 2B. In the transistors with the two structures, the source electrode and the drain electrode are distributed on two sides of the grid electrode in the horizontal plane direction, so that the area occupied by the transistors in the horizontal direction is larger.
Because the bit line and the storage device of the dynamic random access memory are respectively connected with one of the source electrode and the drain electrode, the transistors with the two structures are used for manufacturing the memory, the capacitors of the bit line and the storage device are both positioned on the same side of the grid electrode and are both positioned on the same surface of the wafer in the processing technology, so that the whole technology has higher complexity, especially has extremely high requirements on photoetching and related technologies, the control difficulty of the technological process is higher, and the failure rate is higher.
Therefore, how to make up for the shortcomings of the prior art and achieve breakthrough in transistor density and process manufacturing difficulty is a problem that needs to be solved in the prior art.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method for manufacturing a transistor, a basic memory cell, and a dynamic random access memory, which can improve the density of the transistor and reduce the process manufacturing difficulty.
In order to solve the above problems, the present invention provides a method for manufacturing a transistor, comprising the steps of: forming a conductive channel attached to the insulating side wall, wherein the conductive channel comprises a columnar body and end parts on two sides, and at least one end part is arranged in a protruding manner; forming a gate insulating layer which semi-surrounds the columnar body on the side surface of the columnar body, and exposing two ends of the conductive channel; forming a gate electrode covering the gate insulating layer on the side surface of the columnar body; a source electrode and a drain electrode are formed at both end portions of the conductive channel.
In order to solve the above problem, the present invention provides a transistor including: insulating the side wall; the conductive channel is attached to the insulating side wall and comprises a columnar body and end parts on two sides, wherein at least one end part is arranged in a protruding mode; a gate insulating layer on the side of the columnar body and semi-surrounding the columnar body; a gate electrode on a side of the gate insulating layer covering the gate insulating layer; and a source electrode and a drain electrode covering both end portions.
In order to solve the above problem, the present invention provides a basic memory cell of a dynamic random access memory, including a transistor and a capacitor, the transistor including: insulating the side wall; the conductive channel is attached to the insulating side wall and comprises a columnar body and end parts on two sides, wherein at least one end part is arranged in a protruding mode; a gate insulating layer on the side of the columnar body and semi-surrounding the columnar body; a gate electrode on a side of the gate insulating layer covering the gate insulating layer; and a source electrode and a drain electrode covering both end portions.
In order to solve the above problems, the present invention provides a dynamic random access memory, which includes a plurality of basic memory cells, wherein each basic memory cell includes a transistor and a capacitor, and the transistor includes an insulating spacer; the conductive channel is attached to the insulating side wall and comprises a columnar body and end parts on two sides, wherein at least one end part is arranged in a protruding mode; a gate insulating layer on the side of the columnar body and semi-surrounding the columnar body; a gate electrode on a side of the gate insulating layer covering the gate insulating layer; and a source electrode and a drain electrode covering both end portions.
The transistor is improved from a horizontal transistor in the prior art to a vertical transistor, so that the area occupied by a single transistor in the horizontal direction is reduced, the number of transistors in a unit area is increased, and the transistor density is improved; the transistor channel and the gate semi-surround the transistor along the horizontal direction, so that the control capability of the gate is increased, and the performance of the transistor is improved; the source electrode and the drain electrode at two ends of the transistor are respectively processed and generated on two surfaces of a single wafer and are not directly connected with the substrate, and the transistor can be attached to another wafer through a bonding process subsequently, so that the structure is flexible, and the transistor is easy to process and manufacture.
Drawings
FIG. 1A is a prior art DRAM cell.
FIG. 1B is a prior art DRAM array structure.
Fig. 2A and 2B are schematic diagrams illustrating a planar transistor structure in a dynamic random access memory according to the prior art.
Fig. 3 is a schematic diagram illustrating steps of a method for manufacturing a transistor according to an embodiment of the present invention.
Fig. 4A to 4E are process diagrams illustrating a method for manufacturing a transistor according to an embodiment of the invention.
Fig. 5A to 5B are process diagrams illustrating a method for manufacturing a transistor according to an embodiment of the invention.
Detailed Description
The following detailed description of the embodiments of the transistor fabrication method, the transistor, the basic memory cell, and the dynamic random access memory according to the present invention will be made with reference to the accompanying drawings.
FIG. 3 is a schematic diagram of the implementation steps of a specific embodiment of the transistor manufacturing method of the present invention, including: step S30, forming an insulating side wall; step S30, forming a conductive channel on the side wall of the insulating side wall, wherein the conductive channel comprises a columnar body and end parts on two sides, and at least one end part is arranged in a protruding manner; step S31, forming a gate insulating layer which semi-surrounds the columnar body on the side surface of the columnar body, and exposing two ends of the conductive channel; step S32 of forming a gate electrode on a side surface of the gate insulating layer so as to cover the gate insulating layer; step S34, forming a source electrode and a drain electrode at both ends of the conductive channel.
FIGS. 4A to 4E are schematic views showing the above steps.
Referring to step S30, as shown in fig. 4A, insulating spacers 49 are formed. The material of the insulating sidewall 49 may be any metal conductive material or polysilicon material, including but not limited to metals used for an integrated circuit interconnection structure, such as aluminum, copper, etc., and the forming method may be sputtering, physical deposition, evaporation, etc.
Referring to step S31, as shown in fig. 4B, a conductive trench 40 is formed at the sidewall of the insulating sidewall 49, wherein the conductive trench 40 includes a columnar body 401 and two upper ends 402 and two lower ends 403. In the present embodiment, the lower end 403 is protruded. In other embodiments, the upper end 402 or both ends may be protruded. In this embodiment, the pillar-shaped conductive channel 40 is formed in a silicon substrate (not shown), which is preferably a doped monocrystalline silicon material, such as N-type or P-type monocrystalline silicon. In other embodiments, the formation of a conductive channel within a substrate of any one of the common semiconductor materials may also be employed. In the present embodiment, the columnar body 401 of the conductive channel 40 is a prism, in particular, a quadrangular prism structure. In other embodiments, cylinders, triangular prisms, pentagonal prisms, and any shape of cylinder should be considered as possible.
Referring to step S32, as shown in fig. 4C, a gate insulating layer 41 is formed on the side of the columnar body 401 to half-surround the conductive channel 40 and expose two ends of the conductive channel 40. The material of the gate insulating layer 41 is preferably selected from any one of silicon oxide, silicon nitride, and silicon oxynitride, and any common insulating material including, but not limited to, oxide should be considered as an optional material for forming the gate insulating layer 41.
As shown in fig. 4D, referring to step S33, a gate electrode 42 is formed on the side of the columnar body 401 to cover the gate insulating layer 41. The material of the gate electrode 42 may be any metal conductive material or polysilicon material, including but not limited to aluminum, copper, and other metals used for the interconnect structure of the integrated circuit, and the forming method may be sputtering, physical deposition, evaporation, and the like.
As shown in fig. 4E, referring to step S34, a source electrode 43 and a drain electrode 44 are formed at both end portions of the conductive channel 40. The material of the source electrode 43 and the drain electrode 44 can be any metal conductive material, including but not limited to aluminum, copper, and other metals used for the interconnect structure of the integrated circuit, and the forming method can be sputtering, physical deposition, evaporation, and the like. In this embodiment, the source electrode 43 is disposed above the substrate, and the drain electrode 44 is disposed below the substrate. In this step, the source electrode 43 is formed on the front surface of the silicon substrate, and the drain electrode 44 on the back surface may be formed by first thinning the silicon substrate to a predetermined thickness and then fabricating the drain electrode 44.
The transistor formed after the above process is implemented is a transistor with a vertical structure, and includes: insulating side walls 49; the conductive channel 40 is arranged on the side wall of the insulating side wall 49, the conductive channel 40 includes a columnar body 401, and an upper end 402 and a lower end 403 on two sides, and in the present embodiment, the lower end 403 is protruded; the gate insulating layer 41 of the columnar body 401 is surrounded by the side of the columnar body 401; a gate electrode 42 on a side surface of the gate insulating layer 41 to cover the gate insulating layer 41; and a source electrode 43 and a drain electrode 44 at both ends of the conductive channel 40.
The above steps S30 and S31, i.e. the methods shown in fig. 4A and fig. 4B, can be replaced by: forming a conductive channel; and forming an insulating side wall at one side of the conductive channel. Referring to fig. 5A, a conductive channel 50 is formed, and referring to fig. 5B, an insulating sidewall 59 is formed at one side of the conductive channel 50. The subsequent steps are similar to the previous embodiment and are omitted here.
The transistor is improved from a horizontal transistor in the prior art to a vertical transistor, so that the area occupied by a single transistor in the horizontal direction is reduced, the number of transistors in a unit area is increased, and the transistor density is improved; the transistor channel and the gate semi-surround the transistor along the horizontal direction, so that the control capability of the gate is increased, and the performance of the transistor is improved; the lower end part and the corresponding leakage electrode are arranged in a protruding mode, and can be further directly interconnected with adjacent transistors through transverse or longitudinal extension to form a memory array, so that a metal interconnection structure is prevented from being manufactured again, and process steps are saved; the insulating side wall can provide mechanical support for the vertical channel, so that the transverse size of the channel is reduced, and the control capability of the grid electrode on the channel is improved; the source electrode and the drain electrode at two ends of the transistor are respectively processed and generated on two surfaces of a single wafer and are not directly connected with the substrate, and the transistor can be attached to another wafer through a bonding process subsequently, so that the structure is flexible, and the transistor is easy to process and manufacture.
The above structure can be used to construct the basic memory cell of a dynamic random access memory. The basic memory cell comprises a transistor and a capacitor, the so-called 1T1C configuration. The transistor includes: insulating side walls 49; the conductive channel 40 is arranged on the side wall of the insulating side wall 49, the conductive channel 40 includes a columnar body 401, and an upper end 402 and a lower end 403 on two sides, and in the present embodiment, the lower end 403 is protruded; the gate insulating layer 41 of the columnar body 401 is surrounded by the side of the columnar body 401; a gate electrode 42 on a side surface of the gate insulating layer 41 to cover the gate insulating layer 41; and a source electrode 43 and a drain electrode 44 at both ends of the conductive channel 40.
The above structure can be further used to form a dynamic random access memory, which includes a plurality of basic memory cells including a transistor and a capacitor, so-called 1T1C structure. The transistor includes: insulating side walls 49; the conductive channel 40 is arranged on the side wall of the insulating side wall 49, the conductive channel 40 includes a columnar body 401, and an upper end 402 and a lower end 403 on two sides, and in the present embodiment, the lower end 403 is protruded; the gate insulating layer 41 of the columnar body 401 is surrounded by the side of the columnar body 401; a gate electrode 42 on a side surface of the gate insulating layer 41 to cover the gate insulating layer 41; and a source electrode 43 and a drain electrode 44 at both ends of the conductive channel 40.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (13)
1. A method of manufacturing a transistor, comprising the steps of:
forming a conductive channel attached to the insulating side wall, wherein the conductive channel comprises a columnar body and end parts on two sides, and at least one end part is arranged in a protruding manner;
forming a gate insulating layer which semi-surrounds the columnar body on the side surface of the columnar body, and exposing two ends of the conductive channel;
forming a gate electrode covering the gate insulating layer on the side surface of the gate insulating layer;
a source electrode and a drain electrode are formed at both end portions of the conductive channel.
2. The method of claim 1, wherein the conductive channel attached to the insulating sidewall is formed by:
forming an insulating side wall;
and forming a conductive channel at the side wall of the insulating side wall.
3. The method of claim 1, wherein the conductive channel attached to the insulating sidewall is formed by:
forming a conductive channel;
and forming an insulating side wall at one side of the conductive channel.
4. The method of claim 1, wherein the columnar structure of the columnar body is selected from any one of a cylinder and a prism.
5. The method according to claim 1, wherein the gate insulating layer is made of a material selected from any one of silicon oxide, silicon nitride, and silicon oxynitride.
6. The method of claim 1, wherein the gate electrode, the source electrode, and the drain electrode are made of a metal material.
7. A transistor, comprising:
insulating the side wall;
the conductive channel is attached to the insulating side wall and comprises a columnar body and end parts on two sides, wherein at least one end part is arranged in a protruding mode;
a gate insulating layer on the side of the columnar body and semi-surrounding the columnar body;
a gate electrode on a side of the gate insulating layer covering the gate insulating layer; and
and a source electrode and a drain electrode covering both end portions.
8. The transistor according to claim 7, wherein the columnar structure of the columnar body is selected from any one of a cylinder and a prism.
9. The transistor according to claim 7, wherein a material of the gate insulating layer is selected from any one of silicon oxide, silicon nitride, and silicon oxynitride.
10. The transistor of claim 7, wherein the gate electrode, the source electrode, and the drain electrode are made of a metal material.
11. A basic memory cell of a dynamic random access memory, comprising a transistor and a capacitor, wherein the transistor comprises:
insulating the side wall;
the conductive channel is attached to the insulating side wall and comprises a columnar body and end parts on two sides, wherein at least one end part is arranged in a protruding mode;
a gate insulating layer on the side of the columnar body and semi-surrounding the columnar body;
a gate electrode on a side of the gate insulating layer covering the gate insulating layer; and
and a source electrode and a drain electrode covering both end portions.
12. A dynamic random access memory comprising an array of a plurality of elementary memory cells, said elementary memory cells comprising a transistor and a capacitor, wherein said transistor comprises:
insulating the side wall;
the conductive channel is attached to the insulating side wall and comprises a columnar body and end parts on two sides, wherein at least one end part is arranged in a protruding mode;
a gate insulating layer on the side of the columnar body and semi-surrounding the columnar body;
a gate electrode on a side of the gate insulating layer covering the gate insulating layer; and
and a source electrode and a drain electrode covering both end portions.
13. The dram of claim 12, wherein the array of elementary memory cells comprises two adjacent transistors, the ends of the two adjacent transistors protruding from each other being connected to each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110410507.4A CN113517343A (en) | 2021-04-16 | 2021-04-16 | Method for manufacturing transistor, basic memory cell, and dynamic random access memory |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110410507.4A CN113517343A (en) | 2021-04-16 | 2021-04-16 | Method for manufacturing transistor, basic memory cell, and dynamic random access memory |
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| CN113517343A true CN113517343A (en) | 2021-10-19 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097412A (en) * | 2009-12-10 | 2011-06-15 | 南亚科技股份有限公司 | Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same |
| US20120052640A1 (en) * | 2010-08-31 | 2012-03-01 | Mark Fischer | Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays |
| CN102544013A (en) * | 2010-12-15 | 2012-07-04 | 力晶科技股份有限公司 | Dynamic random access memory cell and array with vertical channel transistors |
| CN110024133A (en) * | 2016-12-24 | 2019-07-16 | 英特尔公司 | Vertical transistor devices and technology |
-
2021
- 2021-04-16 CN CN202110410507.4A patent/CN113517343A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102097412A (en) * | 2009-12-10 | 2011-06-15 | 南亚科技股份有限公司 | Embedded bit line structure, field effect transistor structure with the same and method of fabricating the same |
| US20120052640A1 (en) * | 2010-08-31 | 2012-03-01 | Mark Fischer | Methods Of Forming Pluralities Of Vertical Transistors, And Methods Of Forming Memory Arrays |
| CN102544013A (en) * | 2010-12-15 | 2012-07-04 | 力晶科技股份有限公司 | Dynamic random access memory cell and array with vertical channel transistors |
| CN110024133A (en) * | 2016-12-24 | 2019-07-16 | 英特尔公司 | Vertical transistor devices and technology |
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