CN113517255B - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN113517255B
CN113517255B CN202110444203.XA CN202110444203A CN113517255B CN 113517255 B CN113517255 B CN 113517255B CN 202110444203 A CN202110444203 A CN 202110444203A CN 113517255 B CN113517255 B CN 113517255B
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substrate
pad
conductive
bonding
post
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CN113517255A (en
Inventor
张丽霞
刘杰
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, comprising the following steps: the substrate and the bonding pad are positioned on the substrate, and the substrate exposes the surface of the bonding pad; a bonding post located on the surface of the bonding pad far from the substrate and contacting the bonding pad; a first device on the substrate and spaced apart from the bond post; a bonding pad located on the surface of the first device far from the substrate; a lead wire connecting the pad and the bond post; and a protective dielectric layer extending along the sidewalls of the bond post. The embodiment of the invention is beneficial to improving the connection strength between the lead and the bonding post and the welding pad, and enhancing the protection effect on the bonding post so as to improve the stability of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The embodiment of the invention relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
With the progress of technology, the integration level and the integration level of semiconductor packages are gradually increased, and electronic devices are being developed toward miniaturization, high speed, high reliability, low cost and low power consumption. Connections in semiconductor packages are typically made by wire bonding. Wire Bonding (Wire Bonding) is the interconnection of the I/O terminals of a chip with corresponding package leads or pads on a substrate with wires. In the solid phase welding process, heating, pressurizing and ultrasonic energy are adopted to destroy the surface oxide layer and pollution, generate plastic deformation, and the interface is in close contact to generate electron sharing and atomic diffusion to form welding spots.
However, as the package integration level increases, the distance between the I/O end of the chip and the bonding pad on the package lead or the substrate is further reduced, and since the I/O end of the chip is higher than the bonding pad on the package lead or the substrate, when the metal wire forms a first bonding point on the I/O end of the chip and forms a second bonding point on the bonding pad of the package lead or the substrate, the height difference between the first bonding point and the second bonding point is larger and the distance between the first bonding point and the second bonding point is smaller, so that the bending degree of the metal wire is larger, and the first bonding point and the second bonding point are easy to crack, thereby affecting the stability of the semiconductor structure.
Disclosure of Invention
The technical problem solved by the embodiment of the invention is to provide a semiconductor structure and a manufacturing method thereof, which are beneficial to improving the connection strength between a lead and a bonding post and the bonding pad and improving the stability of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate and a bonding pad on the substrate, wherein the substrate exposes the surface of the bonding pad; a bond post located on a surface of the bond pad remote from the substrate and in contact with the bond pad; a first device on the substrate and spaced apart from the bond post; the welding pad is positioned on the surface of the first device away from the substrate; a wire connecting the pad and the bond post; and the protective dielectric layer extends along the side wall of the joint column.
Correspondingly, the embodiment of the invention also provides a manufacturing method of the semiconductor structure, which comprises the following steps: providing a substrate, wherein the substrate is provided with a bonding pad, and the substrate exposes the surface of the bonding pad; forming bond posts on a surface of the bond pad remote from the substrate; forming a protective dielectric layer on the side wall of the joint column; forming a first device on the substrate, wherein a surface of the first device away from the substrate is provided with a welding pad, and the first device and the bonding post are mutually spaced; and connecting the bonding post and the welding pad by adopting a lead.
Compared with the related art, the technical scheme provided by the embodiment of the invention has the following advantages:
in the technical scheme, the substrate is provided with the bonding post electrically connected with the bonding pad, and two ends of the lead are respectively in contact electrical connection with the bonding post and the bonding pad on the first device so as to realize the transmission of electric signals between the substrate and the first device. The bonding pad is provided with the bonding post, so that in the direction of the substrate pointing to the first device, the height difference between two ends of the lead connecting the bonding post and the bonding pad is reduced, the bending radian of the lead is reduced, and even under the condition that the distance between the two ends of the lead is reduced, the bending radian of the lead can be relieved by reducing the height difference between the two ends of the lead, thereby being beneficial to improving the connection strength between the lead and the bonding post and the bonding pad, and improving the stability of the semiconductor structure. In addition, the protective medium layer extends along the side wall of the joint column, so that the protective medium layer at least surrounds the side wall of the joint column, is favorable for preventing the side wall of the joint column from being oxidized or corroded, plays a supporting role on the joint column, and is favorable for preventing the joint column from being offset and toppled relative to the substrate under the influence of external force.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which are not intended to be limiting in scale unless specifically stated otherwise.
Fig. 1 to fig. 3 are schematic cross-sectional views of a semiconductor structure according to an embodiment of the invention;
fig. 4 to 9 are schematic cross-sectional views of a semiconductor structure according to another embodiment of the present invention;
fig. 10 to 18 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure according to another embodiment;
fig. 19 to 23 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to another embodiment.
Detailed Description
As known from the background art, the connection strength between the I/O terminals of the leads and the chip and the package pins or pads on the substrate needs to be improved, and the stability of the semiconductor structure needs to be improved.
It has been found by analysis that the spacing between the I/O terminals of the chip and the package pins or pads on the substrate is inevitably further reduced in order to pursue higher package integration. At this time, the height difference between the I/O terminal of the chip and the bonding pad on the package lead or the substrate may further increase the bending degree of the lead connecting the I/O terminal of the chip and the bonding pad on the package lead or the substrate, so that the lead is more likely to crack at the I/O terminal of the chip and the bonding pad on the package lead or the substrate due to the excessive bending degree.
In order to solve the above-mentioned problems, the present application provides a semiconductor structure and a method for manufacturing the same, in which a bond post is disposed on a bond pad, so that in a direction of a substrate pointing to a first device, a height difference between two ends of a lead connecting the bond post and the bond pad is reduced, and a bending radian of the lead is reduced, and even if a distance between the two ends of the lead is reduced, the bending radian of the lead is relieved by reducing the height difference between the two ends of the lead, thereby being beneficial to improving a connection strength between the lead and the bond post and the bond pad, and improving stability of the semiconductor structure. In addition, the protective medium layer extends along the side wall of the joint column, so that the protective medium layer at least surrounds the side wall of the joint column, is favorable for preventing the side wall of the joint column from being oxidized or corroded, plays a supporting role on the joint column, and is favorable for preventing the joint column from being offset relative to the substrate and preventing the joint column from toppling under the influence of external force.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, it will be understood by those of ordinary skill in the art that in various embodiments of the present application, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the claimed technical solution of the present application can be realized without these technical details and various changes and modifications based on the following embodiments.
An embodiment of the present invention provides a semiconductor structure, and the following describes the semiconductor structure according to an embodiment of the present invention in detail with reference to the accompanying drawings. Fig. 1 to 3 are schematic cross-sectional views of a semiconductor structure according to an embodiment of the invention.
Referring to fig. 1, a semiconductor structure includes: a substrate 100 and a bonding pad 110 disposed on the substrate 100; a bonding post 102 located on a surface of the bonding pad 110 away from the substrate 100 and contacting the bonding pad 110; a first device 101 on the substrate 100 and spaced apart from the bond post 102; a pad 111 located on a surface of the first device 101 away from the substrate 100; a wire 103, the wire 103 connecting the pad 111 and the bond post 102; a protective dielectric layer 112 extends along the sidewalls of the bond post 102.
Specifically, the substrate 100 exposes a surface of the bonding pad 110, and the bond post 102 is in electrical contact with the bonding pad 110 such that electrical signals can be transferred between the substrate 100 and the bonding pad 111 through the bond post 102 and the wire 103.
In addition, the side of the substrate 100 away from the bonding pad 110 may also have a package pad 120 for positioning when the substrate 100 is connected to other structures. The bonding pad 110 and the package pad 120 may be made of at least one of conductive materials such as gold, aluminum, copper, gold-based alloy, or aluminum-based alloy. In particular, an aluminum-based alloy refers to a material comprising more than 50% aluminum, for example, aluminum material may be doped with silicon (e.g., 1% silicon).
The difference in height between the top surface of the bond post 102 and the top surface of the bond pad 111 is no greater than the thickness of the bond pad 111 in the direction in which the substrate 100 is directed toward the first device 101. In this way, controlling the height difference between the two end points of the wire 103 connecting the bond post 102 and the pad 111 to fluctuate within the thickness range of the pad 111 is advantageous in ensuring a lower height difference between the two end points of the wire 103, thereby facilitating to ease the degree of bending of the wire 103, thereby facilitating to improve the connection strength between the wire 103 and the bond post 102 and the pad 111, so as to improve the stability of the semiconductor structure.
Further, one end of the wire 103 is in contact electrical connection with the pad 11 to form a first bonding point a, the other end of the wire 103 is in contact electrical connection with the bond post 102 to form a second bonding point b, and the first bonding point a is not lower than the second bonding point b.
In other embodiments, the first bonding point may be slightly lower than the second bonding point, so long as the difference in height between the first bonding point and the second bonding point is not greater than the thickness of the bonding pad.
In some examples, with continued reference to fig. 1, the first bond site a is a wedge-shaped bond site, and a portion of the wire 103 proximate to the first bond site a extends in a direction parallel to the top surface of the bond pad 111, with the top surface of the bond post 102 being flush with the top surface of the bond pad 111. In addition, the second bond site b is also a wedge-shaped bond site, and a portion of the wire 103 adjacent to the second bond site b extends in a direction parallel to the top surface of the bond post 102.
In the wedge bonding, when a part of the wire 103 near the first bonding point a extends along a direction parallel to the top surface of the bonding pad 111, an included angle between the tangential direction of the wire 103 at the first bonding point a and the top surface of the bonding pad 111 is smaller than 45 degrees, for example, when the top surface of the bonding post 102 is level with the top surface of the bonding pad 111, the first bonding point a and the second bonding point b are in the same plane, so that an included angle between the tangential direction of the wire 103 at the second bonding point b and the top surface of the bonding post 102 is also smaller than an acute angle, and the bending degree of the wire 103 is relieved, so that the acting force of the wire 103 at the first bonding point a is reduced, and the acting force of the wire 103 at the second bonding point b is reduced, thereby further reducing the cracking probability of the first bonding point a and the second bonding point b.
In still other examples, referring to fig. 2, the first bond site a includes a ball bond site, and a portion of the wire 103 proximate to the first bond site a extends in a direction perpendicular to the top surface of the bond pad 111, with the top surface of the bond post 102 being higher than the top surface of the bond pad 111. In addition, the second bond site b is also a wedge-shaped bond site, and a portion of the wire 103 adjacent to the second bond site b extends in a direction parallel to the top surface of the bond post 102.
In ball bonding, a portion of the wire 103 near the first bonding point a extends in a direction perpendicular to the top surface of the bonding pad 111, so that the angle between the tangential direction of the wire 103 at the first bonding point a and the top surface of the bonding pad 111 is a larger acute angle, for example, the acute angle is larger than 45 °, when the top surface of the bonding post 102 is higher than the top surface of the bonding pad 111, the angle between the tangential direction of the wire 103 at the second bonding point b and the top surface of the bonding post 102 can be reduced, so that the included angle is a smaller acute angle, thereby relieving the bending degree of the wire 103, reducing the magnitude of the force generated by the wire 103 at the first bonding point a, and reducing the magnitude of the force generated by the wire 103 at the second bonding point b, thereby further reducing the probability of cracking of the first bonding point a and the second bonding point b.
In other embodiments, the second bond point may also be a ball bond point.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of the area I in fig. 2. The bond post 102 has a recess on a side thereof remote from the substrate 100, the recess being filled with a bonding agent 149, and in particular, the recess may be filled with the bonding agent 149; the orthographic projection of the second bond site b on the substrate 100 covers the orthographic projection of the groove on the substrate 100.
The material of the bond post 102 and the wire 103 may be at least one of a conductive material such as gold, aluminum, copper, a gold-based alloy, or an aluminum-based alloy.
In addition, since the bond post 102 and the wire 103 form an alloy interface at the second bond site b, they are easily oxidized, which may result in a decrease in the connection strength of the wire 103 to the bond post 102 at the second bond site b. And grooves are formed in the areas, corresponding to the second bonding points b, of the bonding posts 102, and the grooves are filled with bonding agents 149, so that excellent bonding effect of the bonding agents 149 is facilitated, the connection strength between the second bonding points b and the bonding posts 102 is improved, and the probability of cracking of the second bonding points b is further reduced. Wherein the material of the cement 149 comprises an epoxy, a silicone, or polyvinyl acetate.
In this embodiment, in the direction in which the substrate 100 points to the first device 101, the cross-sectional shape of the bond post 102 is rectangular, and then the bond post 102 may have a cylindrical structure, an elliptical cylindrical structure, or a square cylindrical structure. In other embodiments, the cross-sectional shape of the joint post may be a regular trapezoid, so that the joint post may have a truncated cone structure, which is beneficial to increasing the contact area between the joint post and the substrate, enhancing the supporting effect of the substrate on the joint post, and improving the stability of the joint post.
In this embodiment, the lead 103 includes a lead neck portion c, where the lead 103 is bent to extend upward along the first bonding point a, and a space is provided between the protective dielectric layer 112 and the first device 101, where the lead neck portion c is located.
Since the wire neck portion c is located at the bend where the wire 103 extends upward along the first bonding point a, the wire neck portion c is the highest point of the wire 103 in the direction in which the substrate 100 is directed toward the first device 101.
When the bond post 102 and the pad 111 are connected by the wire 103, a first force acting in a direction away from the pad 111 is generated at a first bond point a, and a second force acting in a direction away from the bond post 102 is generated at a second bond point b. Since the wire neck portion c is located in the space between the protective dielectric layer 112 surrounding the sidewall of the bond post 102 and the pad 111, it is beneficial to reduce the angle between the tangential direction of the wire 103 at the first bonding point a and the top surface of the pad 111, and reduce the angle between the tangential direction of the wire 103 at the second bonding point b and the top surface of the bond post 102, and ease the bending degree of the wire 103, so that it is beneficial to reduce the magnitude of the first acting force generated by the wire 103 at the first bonding point a, and reduce the magnitude of the second acting force generated by the wire 103 at the second bonding point b, so as to further reduce the probability of cracking of the first bonding point a and the second bonding point b.
In addition, the lead neck portion c is located in the interval between the protective dielectric layer 112 and the bonding pad 111, and the difference in height between the first bonding point a and the second bonding point b is smaller, so that the interval between the protective dielectric layer 112 and the bonding pad 111 can be reduced under the condition that the bending degree of the lead 103 is smaller, so as to improve the packaging density of the semiconductor structure, and meanwhile, ensure good connection strength between the lead 103 and the bonding post 102 and the bonding pad 111.
In this embodiment, the protective dielectric layer 112 extends along the sidewall of the bond post 102 and surrounds the sidewall of the bond pad 110 in addition to the sidewall of the bond post 102, which is beneficial to avoid oxidation or corrosion of the sidewall of the bond post 102 and the sidewall of the bond pad 110, and to support the bond post 102 and the bond pad 110, to avoid deflection of the bond post 102 and the bond pad 110 relative to the substrate 100 and to avoid tilting of the bond post 102 and the bond pad 110 under the influence of external forces. Wherein the material of the protective dielectric layer 112 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
In other embodiments, the protective dielectric layer may also be located at the second bonding point, i.e., the protective dielectric layer is also located at the top surface of the bond post, which is advantageous to avoid oxidation or corrosion of the second bonding point, so as to ensure good connection strength of the wire at the top surface of the bond post, or the protective dielectric layer may also be located only on the sidewall of the bond post.
The semiconductor structure further includes: and a plastic layer 104, wherein the plastic layer 104 fills the space between the protective dielectric layer 112 and the bonding pad 111 and covers the lead neck part c.
The molding layer 104 covers the lead neck c, which is beneficial to protecting the lead 103 from being interfered by other structures, and in addition, the molding layer 104 has good supporting and reinforcing effects on the lead neck c, which is beneficial to further reducing the cracking probability of the first bonding point a and the second bonding point b. The material of the plastic layer 104 includes an electrically insulating material such as a polymer molding resin or a low temperature thermal glass composite material.
In addition, the plastic layer 104 also wraps the first device 101, the bonding post 102 and the protective dielectric layer 112, so as to protect the first device 101, the bonding post 102 and the protective dielectric layer 112 from being interfered by other structures.
In this embodiment, an adhesive layer 105 may be further provided between the first device 101 and the substrate 100 to enhance the connection strength between the first device 101 and the substrate 100.
In this embodiment, the first device 101 may be a control device or a memory device. In other embodiments, the function of the first device is not limited, and the first device is a semiconductor device commonly used in a semiconductor structure.
In summary, the bond pad 110 has the bond post 102 thereon, which is advantageous for reducing the height difference between the two ends of the wire 103 connecting the bond post 102 and the bond pad 111 in the direction of the substrate 100 toward the first device 101, thereby reducing the bending degree of the wire 103, and even if the spacing between the protective dielectric layer 112 and the bond pad 111 is reduced, the bending degree of the wire 103 can be relieved by the reduced height difference between the two ends of the wire 103, thereby reducing the probability of cracking of the first bond point a and the second bond point b. In addition, the protective dielectric layer 112 surrounding the sidewalls of the bond post 102 and the bond pad 110 has a good supporting effect on the bond post 102 and the bond pad 110, which is beneficial to prevent the bond post 102 and the bond pad 110 from being deflected relative to the substrate 100 and from being toppled over by external forces, and to prevent the sidewalls of the bond post 102 and the bond pad 110 from being oxidized or corroded.
Yet another embodiment of the present invention provides a semiconductor structure that is substantially the same as the previous embodiment, with the main differences including the second device being further provided on a side of the first device remote from the substrate. The following will describe in detail the method for fabricating a semiconductor structure according to another embodiment of the present invention with reference to the drawings, and the same or corresponding parts as those of the foregoing embodiments may be referred to for details of the foregoing embodiments, which are not repeated herein.
Fig. 4 to 9 are schematic cross-sectional views of a semiconductor structure according to another embodiment of the present invention.
Referring to fig. 4, the semiconductor includes: the substrate 200 and the bonding pad 210 on the substrate 200, and the substrate 200 exposes the surface of the bonding pad 210; a bonding post 202 located on a surface of the bonding pad 210 remote from the substrate 200 and contacting the bonding pad 210; a first device 201 on the substrate 200 and spaced apart from the bond post 202; a bonding pad 211 located on a surface of the first device 201 away from the substrate 200; a wire 203, the wire 203 connecting the pad 211 and the bond post 202; a protective dielectric layer 212 extends along the sidewalls of the bond post 202.
On the basis, the semiconductor structure further comprises: a second device 206 located on a side of the first device 201 remote from the substrate 200; a conductive pad 230 disposed on the substrate 200, wherein the substrate 200 exposes a surface of the conductive pad 230, and the conductive pad 230 is spaced apart from the bonding pad 210; a pad 216 located on a surface of the second device 206 remote from the substrate 200; a conductive pillar 207 located on a surface of the conductive pad 230 away from the substrate 200 and in contact with the conductive pad 230, wherein a top surface of the conductive pillar 207 is not lower than a top surface of the bonding pillar 202 in a direction in which the substrate 200 is directed toward the first device 201; a protective support layer 217 extending along sidewalls of the conductive pillars 207; and one end of the conductive wire 208 is in contact electrical connection with the bonding pad 216, and the other end of the conductive wire 208 is in contact electrical connection with the conductive post 207.
Specifically, the conductive posts 207 are in contact electrical connection with the conductive pads 230 such that electrical signals can pass between the substrate 200 and the conductive posts 207.
In this embodiment, the first device 201 is a control device, and the second device 206 is a memory device. In other embodiments, the functions of the first device and the second device are not limited, and the first device and the second device are semiconductor devices commonly used in semiconductor structures.
Specifically, one end of the conductive line 208 is bonded to the pad 216 to form a third bond point f, and the other end of the conductive line 208 is electrically connected to the conductive post 207 to form a fourth bond point g.
In this embodiment, the third bonding point f and the fourth bonding point g are wedge-shaped bonding points, and in other embodiments, the third bonding point and the fourth bonding point may be ball-shaped bonding points, or the third bonding point is a wedge-shaped bonding point, the fourth bonding point is a ball-shaped bonding point, or the third bonding point is a ball-shaped bonding point, and the fourth bonding point is a wedge-shaped bonding point.
In this embodiment, the side of the conductive post 207 away from the substrate 200 may also have a groove, and the groove is filled with bonding agent; the orthographic projection of the fourth bond point g on the substrate 200 covers the orthographic projection of the groove on the substrate 200.
Further, in a direction in which the substrate 200 is directed to the first device 201, the conductive pillar 207 has a rectangular cross-sectional shape, and the conductive pillar 207 may have a cylindrical structure, an elliptical cylindrical structure, or a square cylindrical structure. In other embodiments, the cross-sectional shape of the conductive post may be a regular trapezoid, and the conductive post may have a truncated cone structure.
The conductive posts 207 and the conductive wires 208 may be made of at least one of gold, aluminum, copper, a gold-based alloy, an aluminum-based alloy, and the like.
The conductive line 208 includes a conductive line neck portion h at a bent portion of the conductive line 208 extending upward along the third bond point f, with a space between the conductive post 207 and the pad 216, and the conductive line neck portion h is located in the space.
When the conductive line 208 is used to connect the conductive post 207 to the pad 216 on the second device 206, a third force is generated at a third bond point f that acts in a direction away from the pad 216, and a fourth force is generated at a fourth bond point g that acts in a direction away from the conductive post 207. Since the conductive wire neck h is located in the interval between the conductive post 207 and the pad 216, it is beneficial to reduce the angle between the tangential direction of the conductive wire 208 at the third bonding point f and the top surface of the pad 216, and reduce the angle between the tangential direction of the conductive wire 208 at the fourth bonding point g and the top surface of the conductive post 207, so as to ease the bending degree of the conductive wire 208, and thus, it is beneficial to reduce the magnitude of the third acting force generated by the conductive wire 208 at the third bonding point f, and reduce the magnitude of the fourth acting force generated by the conductive wire 208 at the fourth bonding point g, so as to further reduce the probability of cracking of the third bonding point f and the fourth bonding point g.
In this embodiment, the protection supporting layer 217 extends along the sidewall of the conductive pillar 207 and surrounds the sidewall of the conductive pad 230 in addition to the sidewall of the conductive pillar 207, which is beneficial to avoid oxidation or corrosion of the sidewall of the conductive pillar 207 and the sidewall of the conductive pad 230, and to support the conductive pillar 207 and the conductive pad 230, to avoid the conductive pillar 207 and the conductive pad 230 from being deflected relative to the substrate 200 and to avoid the conductive pillar 207 and the conductive pad 230 from tilting under the influence of external force. Wherein the material of the protective support layer 217 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
In other embodiments, the protection support layer may also be located at the fourth bonding point, that is, the protection support layer is also located at the top surface of the conductive pillar, which is favorable to avoid oxidation or corrosion of the fourth bonding point, so as to ensure good connection strength of the conductive wire at the top surface of the conductive pillar, or the protection support layer may also be located only on the side wall of the conductive pillar.
In this embodiment, the orthographic projection of the area surrounded by the bond post 202, the protective dielectric layer 212, the wire 203, and the first device 201 on the substrate 200 is a first projection, the orthographic projection of the second device 206 on the substrate 200 is a second projection, the second projection covers the first projection, and the orthographic projection of the combination of the conductive post 207 and the protective support layer 217 on the substrate 200 is a third projection, which is located outside the first projection.
In addition, a plastic layer 204 is disposed between the first device 201 and the second device 206, and the plastic layer 204 encapsulates the first device 201, the bond post 202, the protective dielectric layer 212, and the lead 203. When the second projection covers the first projection, the bottom surface of the second device 206 is prevented from contacting the lead 203 when the second device 206 is formed on the first device 201 due to the existence of the molding layer 204, resulting in damage to the lead 203.
It should be noted that, in other embodiments, the front projection of the first device on the substrate may be smaller than the front projection of the second device on the substrate, so that the plastic sealing layer only needs to cover the first device, the bonding post, the protective dielectric layer and the lead, and a good protective effect can be achieved on the lead, so that the second device is prevented from contacting the lead.
The semiconductor structure further includes: the sealing layer 209, the sealing layer 209 covers the second device 206, the conductive pillars 207, the protective support layer 217, and the conductive lines 208. The sealing layer 209 covers the conductive wire neck h, which is beneficial to protecting the conductive wire 208 from being interfered by other structures, and in addition, the sealing layer 209 has good supporting and reinforcing effects on the conductive wire neck h, which is beneficial to further reducing the cracking probability of the third bonding point f and the fourth bonding point g. The material of the sealing layer 209 includes an electrically insulating material such as a polymer molding resin or a low temperature thermal glass composite material.
Further, the front projection of the sealing layer 209 on the substrate 200 covers the substrate 200, and has good protection effect on the substrate 200.
In some examples, the second device 206 is composed of a single chip, and the semiconductor structure will be described below in conjunction with fig. 4 and 5.
In one example, referring to fig. 4, the top surface of the bond post 202 is flush with the top surface of the conductive post 207, and the bond post 202 is of a single layer structure.
In yet another example, referring to fig. 5, in a direction in which the substrate 200 is directed toward the first device 201, a height difference between a top surface of the conductive post 207 and a top surface of the pad 216 is not greater than a thickness of the pad 216.
Specifically, the top surface of the conductive post 207 is flush with the top surface of the pad 216, which is beneficial to ensuring that the third bonding point f and the fourth bonding point g are co-located on a plane, so that an included angle between the tangential direction of the conductive wire 208 at the third bonding point f and the top surface of the pad 216 is a small acute angle, for example, the acute angle is smaller than 45 °, and an included angle between the tangential direction of the conductive wire 208 at the fourth bonding point g and the top surface of the conductive post 207 is also a small acute angle, so as to ease the bending degree of the conductive wire 208, reduce the amount of force generated by the conductive wire 208 at the third bonding point f, and reduce the amount of force generated by the conductive wire 208 at the fourth bonding point g, thereby further reducing the probability of cracking of the third bonding point f and the fourth bonding point g.
In other embodiments, the top surface of the conductive pillar may be slightly lower than the top surface of the pad, or the top surface of the conductive pillar may be slightly higher than the top surface of the pad, so as to ensure that there is a lower height difference between the third bonding point and the fourth bonding point.
In still other examples, the second device 206 includes a package of a plurality of stacked chips, and the chips are stacked in sequence along the direction of the substrate 200 toward the first device 201, each chip having pads 216 exposed at a surface of the chip remote from the substrate 200. The semiconductor structure will be described below with reference to fig. 6 and 9.
It should be noted that, the second device 206 illustrated in fig. 6 to 9 includes three chips stacked in sequence, and adjacent chips are connected together by an adhesive layer 219. In other embodiments, the number of chips is not limited, and the connection manner between adjacent chips is not limited.
In one example, referring to fig. 6, at least one pad 216 of a different chip is electrically connected to the same conductive post 207, the top surface of the conductive post 207 is flush with the top surface of the bonding post 202, and the conductive post 207 is of a single-layer structure.
Specifically, the pads 216 on different chips are electrically connected to the same conductive post 207 through different conductive lines 208. The conductive pillars 207 on the conductive pads 230 are beneficial to reducing the height difference between the third bonding point f and the fourth bonding point g to different extents, so that the bending radian of the conductive wires 208 can be reduced to different extents, and the cracking probability of the third bonding point f and the fourth bonding point g can be reduced.
In yet another example, referring to fig. 7, at least one pad 216 of a different chip is electrically connected to the same conductive post 207, and the chip next to the second device 206 is an underlying chip 226, and the difference in height between the top surface of the conductive post 207 and the top surface of the pad 216 on the underlying chip 226 is no greater than the thickness of the pad 216 in the direction of the substrate 200 toward the first device 201.
Specifically, the top surface of the conductive post 207 is flush with the top surface of the bonding pad 216 on the bottom chip 226, which is favorable for ensuring that the third bonding point f and the fourth bonding point g on the bonding pad 216 on the bottom chip 226 are co-located on a plane, so that the included angle between the tangential direction of the conductive wire 208 at the third bonding point f and the top surface of the bonding pad 216 is a smaller acute angle, and the included angle between the tangential direction of the fourth bonding point g, which is connected with the same conductive wire 208 as the third bonding point f, and the top surface of the conductive post 207 is also a smaller acute angle, thereby further relieving the bending degree of the conductive wire 208, and further reducing the cracking probability of the third bonding point f and the fourth bonding point g.
In addition, the top surface of the conductive post 207 is flush with the top surface of the bonding pad 216 on the bottom chip 226, which is beneficial to reducing the length of the conductive wire 208, thereby reducing the resistance of the conductive wire 208 and improving the transmission rate of the electrical signal on the conductive wire 208; on the other hand, it is advantageous to prevent a short circuit between adjacent conductive lines 208.
In other embodiments, the top surface of the conductive pillar may be slightly lower than the top surface of the pad on the bottom chip, or the top surface of the conductive pillar may be slightly higher than the top surface of the pad on the bottom chip, so as to ensure that the third bonding point and the fourth bonding point have a lower height difference.
In another example, referring to fig. 8, in a direction in which the substrate 200 is directed to the first device 201, a height difference between a top surface of the conductive post 207 electrically connected to the same conductive line 208 and a top surface of the pad 216 is not greater than a thickness of the pad 216.
Specifically, in the conductive pillars 207 and the pads 216 electrically connected to the same conductive line 208, the top surfaces of the conductive pillars 207 are flush with the top surface of the pads 216, which is beneficial to further relieving the bending degree of each conductive line 208, so as to further reduce the cracking probability of the third bonding point f and the fourth bonding point g. In addition, the different conductive lines 208 lie in different planes, which is advantageous for further preventing shorting between adjacent conductive lines 208.
In other embodiments, in the conductive post and the pad electrically connected to the same conductive line, the top surface of the conductive post may be slightly lower than the top surface of the pad, or the top surface of the conductive post may be slightly higher than the top surface of the pad, so as to ensure that the third bonding point and the fourth bonding point have a lower height difference.
In yet another example, referring to fig. 9, the second device 206 exposes a sidewall of the pad 216, a metal layer is disposed between the pads 216 on adjacent second devices 206 for electrically connecting the pads 216 on adjacent second devices 206, the pads 216 and the metal layer together form an electrical connection structure, and one end of the conductive line 208 is in contact electrical connection with a top surface of the electrical connection structure.
In this embodiment, the bonding pad 216 and the metal layer are integrally formed, so that different chips can be electrically connected with the same conductive post 207 through the same conductive wire 208, which is beneficial to reducing the number of conductive wires 208. In addition, the top surface of the conductive post 207 and the top surface of the electrical connection structure may be flush, which is beneficial to reducing the length of the conductive wire 208, thereby reducing the resistance of the conductive wire 208; on the other hand, it is advantageous to alleviate the degree of bending of the conductive line 208, thereby reducing the probability of cracking of the third bonding point f and the fourth bonding point g.
In the above example, the conductive pillars 207 may have a single-layer structure or a stacked-layer structure. Moreover, the protection support layer 217 corresponds to the conductive posts 207 surrounded by the protection support layer 217 one by one, and the top surface of the protection support layer 217 is flush with the top surface of the conductive post 207 corresponding to the protection support layer 217, so as to comprehensively protect and support the side walls of the conductive posts 217.
In summary, the bonding pad 210 has the bonding post 202, which is beneficial to reducing the height difference between the two ends of the wire 203 connecting the bonding post 202 and the bonding pad 211, thereby reducing the bending degree of the wire 203, so as to ensure good connection strength between the wire 203 and the bonding post 202 and the bonding pad 211. In addition, the conductive pillars 207 on the conductive pads 230 are beneficial to reduce the height difference between the third bonding point f and the fourth bonding point g, thereby reducing the bending degree of the conductive lines 208, and thus reducing the probability of cracking of the third bonding point f and the fourth bonding point g. Also, since the degree of bending of the conductive line 208 can be reduced, the overall thickness of the semiconductor structure can be reduced, so that the semiconductor structure is developed toward a smaller size.
In addition, the protective support layer 217 surrounding the side walls of the conductive pillars 207 and the side walls of the conductive pads 230 has a good supporting effect on the conductive pillars 207 and the conductive pads 230, and is advantageous in preventing the side walls of the conductive pillars 207 and the side walls of the conductive pads 230 from being oxidized or corroded.
Correspondingly, another embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which is used for forming the semiconductor structure described in the above embodiment.
Fig. 10 to 18 are schematic structural diagrams corresponding to each step in the method for forming a semiconductor structure according to the present embodiment.
Referring to fig. 10 to 17, the method of fabricating a semiconductor structure includes: providing a substrate 100, wherein the substrate 100 is provided with a bonding pad 110; forming bond posts 102 on a surface of the bond pad 110 remote from the substrate 100; a protective dielectric layer 112 is formed on the sidewalls of the bond post 102.
Specifically, forming the bond post 102 and the protective dielectric layer 112 includes the steps of:
referring to fig. 10, a sacrificial layer 129 is formed on a substrate 100 having a bonding pad 110 and a package pad 120 thereon, and the substrate 100 exposes surfaces of the bonding pad 110 and the package pad 120. Specifically, the substrate 100 has a first surface and a second surface opposite to each other, the bonding pad 110 is located on the first surface, and the package pad 120 is located on the second surface. The material of the sacrificial layer 129 may be at least one of silicon oxide, silicon nitride, or silicon oxynitride.
Referring to fig. 11, a mask layer 139 having openings is formed on a substrate 100, and a space for accommodating a first device 101 is reserved between adjacent openings. The material of the mask layer 139 may be photoresist.
Referring to fig. 12, the sacrificial layer 129 is patterned using the mask layer 139 as a mask to form a via 10 exposing the bond pad 110 on the substrate 100; the mask layer 139 is removed.
Referring to fig. 13, a bonding post 102 filled with the through hole 10 is formed, and the material of the bonding post 102 is at least one of a conductive material such as gold, aluminum, copper, a gold-based alloy, or an aluminum-based alloy.
In some examples, referring to fig. 14, a portion of the sacrificial layer 129 (referring to fig. 13) is removed, the sacrificial layer 129 remaining around the sidewalls of the bond post 102 is a protective dielectric layer 112, the adhesive layer 105 is applied to the first device 101 near the bottom surface of the substrate 100, and then the first device 101 coated with the adhesive layer 105 is placed on the surface of the substrate 100. In addition, the first device 101 is positioned in the space between adjacent bond posts 102 with a space between the first device 101 and each bond post 102 for providing sufficient clearance for subsequent electrical connection of the bond pad 111 on the first device 101 and the bond post 102 using a wire. In other examples, an adhesive layer may also be applied to the substrate and then the first device may be secured to the adhesive layer.
Referring to fig. 15, a wire 103 is used to connect a bond post 102 and a pad 111, one end of the wire 103 is electrically connected to the first device 101 to form a first bond point a, and the other end of the wire 103 is electrically connected to the bond post 102 to form a second bond point b.
Further, the step of connecting the bond post 102 and the pad 111 by the wire 103 may further include: referring to fig. 16, fig. 16 is a schematic cross-sectional view of the region II of fig. 15, in which a groove is formed on the joint post 102; filling the groove with a bonding agent 149; one end of the wire 103 is bonded to the top surface of the bond post 102 and the top surface of the bonding agent 149, and the other end of the wire 103 is bonded to the pad 111.
In other embodiments, after the second bond site is formed on the bond post by the wire, a dielectric layer is also formed on the top surface of the bond post and around the second bond site, the dielectric layer and the sacrificial layer remaining around the bond post sidewall in the previous step together forming a protective dielectric layer.
Referring to fig. 15 and 1 in combination, a molding layer 104 is formed on a side of the first device 101 remote from the substrate 100, the molding layer 104 encapsulating the first device 101, the bond posts 102, and the leads 103. Specifically, the molding layer 104 is located away from the top surface of the substrate 100 and above the neck portion c of the lead 103, so as to prevent the lead 103 from being damaged during the subsequent other process steps. In addition, the molding layer 104 may also be used to prevent the first device 101 and the bond post 102 from being damaged.
In still other examples, referring to fig. 17, sacrificial layer 129 is again patterned, forming a positioning slot between adjacent bond posts 102 for receiving first device 101; an adhesive layer 105 is applied to the first device 101 near the bottom surface of the substrate 100, and then the first device 101 coated with the adhesive layer 105 is placed on the bottom of the positioning groove. Since the positioning groove for accommodating the first device 101 is formed in advance on the sacrifice layer 129 before the first device 101 is mounted on the substrate 100, accurate positioning of the mounting position of the first device 101 is facilitated.
Referring to fig. 18, a wire 103 is used to connect a bond post 102 and a pad 111, one end of the wire 103 is electrically connected to a first device 101 to form a first bond point a, and the other end of the wire 103 is electrically connected to the bond post 102 to form a second bond point b, which is not lower than the first bond point a in a direction in which the substrate 100 points to the first device 101.
Since the wire 103 generates a larger extrusion force to the pad 111 at the first bonding point a when bonding with the pad 111 on the first device 101, the wire 103 generates a larger extrusion force to the bonding post 102 at the second bonding point b when bonding with the top surface of the bonding post 102, and the side walls of the bonding post 102 and the first device 101 are both wrapped with the sacrificial layer 129, so that the bonding post 102 and the first device 101 have good supporting effect, and the position of the bonding post 102 and the first device 101 on the substrate 100 is prevented from being offset or toppled after the bonding post 102 and the first device 101 are subjected to the extrusion force, thereby being beneficial to improving the yield of the formed semiconductor structure.
In this example, the step of connecting the bond post 102 and the pad 111 by the wire 103 may further include: forming a groove on the joint post 102; filling the grooves with bonding agent; one end of the wire 103 is bonded to the top surface of the bond post 102 and the top surface of the bond, and the other end of the wire 103 is bonded to the pad 111.
Referring to fig. 18 and 1 in combination, a portion of the sacrificial layer 129 is removed, and the sacrificial layer 129 remaining around the sidewalls of the bond post 102 is the protective dielectric layer 112.
Further, a molding layer 104 is formed on a side of the first device 101 away from the substrate 100, and the molding layer 104 encapsulates the first device 101, the protective dielectric layer 112, the bond post 102, and the lead 103. Specifically, the molding layer 104 is located away from the top surface of the substrate 100 and above the neck portion c of the lead 103, so as to prevent the lead 103 from being damaged during the subsequent other process steps. In addition, the molding layer 104 may also be used to prevent the first device 101, the protective dielectric layer 112, and the bond post 102 from being damaged.
In summary, in the semiconductor structure formed by the above method, the bond post 102 is formed on the bond pad 110, which is beneficial to reduce the bending degree of the wire 103, thereby reducing the probability of cracking the first bond point a and the second bond point b. In addition, forming the protective dielectric layer 112 on the sidewall of the bond post 102 is beneficial to avoiding the bond post 102 from being deflected or toppled over relative to the substrate 100 due to external forces.
Still another embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which is used to form the semiconductor structure described in the foregoing still another embodiment.
Fig. 19 to 23 are schematic structural diagrams corresponding to each step in the method for forming a semiconductor structure according to the present embodiment.
Referring to fig. 19 to 22, the method for fabricating the semiconductor structure includes: the substrate 200 has conductive pads 230 spaced apart from the bonding pads 210, and the substrate 200 exposes the surfaces of the conductive pads 230; in forming the bonding post 202 and the protective dielectric layer 212, the conductive post 207 and the protective support layer 217 are also formed to be spaced apart from the bonding post 202.
In this embodiment, forming the bonding post 202, the protective dielectric layer 212, the conductive post 207, and the protective support layer 217 includes the steps of:
referring to fig. 19, the bonding pad 210 and the conductive pad 230 are located on the same side of the substrate 200, a sacrificial layer 229 is formed on the substrate 200, and the sacrificial layer 229 covers the bonding pad 210 and the conductive pad 230.
Mask layer 239 having an opening is formed on substrate 200, and the front projection of the opening on substrate 200 coincides with the front projection of bond pad 210 or conductive pad 230 on substrate 200. The material of mask layer 239 may be photoresist.
Referring to fig. 20, the sacrificial layer 229 is patterned using the mask layer 239 (refer to fig. 19) as a mask to form the via hole 20 exposing the bonding pad 210 and the conductive pad 230 on the substrate 200; mask layer 239 is removed.
Referring to fig. 21, the bonding post 202 and the conductive post 207 filled with the through hole 20 are formed, wherein the bonding post 202 is in contact with the bonding pad 210, the conductive post 207 is in contact with the conductive pad 230, the materials of the bonding post 202 and the conductive post 207 are the same, and the materials of the bonding post 202 and the conductive post 207 are at least one of conductive materials such as gold, aluminum, copper, or a composite material of silicon and aluminum.
In other embodiments, a sacrificial layer is formed on a substrate; patterning the sacrificial layer to form a first through hole exposing the bonding pad and the conductive pad on the substrate, and then forming a bonding post and a bottom conductive post filled in the first through hole; forming an isolation layer on one side of the sacrificial layer away from the substrate, wherein the isolation layer covers the joint column and the bottom conductive column; patterning the isolation layer to form a second through hole exposing the bottom conductive post; and forming a top conductive column filled in the second through hole, wherein the bottom conductive column and the top conductive column jointly form the conductive column.
Referring to fig. 22, a portion of the sacrificial layer 229 (refer to fig. 21) is removed, the sacrificial layer 229 remaining around the sidewalls of the bond post 202 is the protective dielectric layer 212, and the sacrificial layer 229 remaining around the sidewalls of the conductive post 207 is the protective support layer 217.
Further, a first device 201 is formed on the substrate 200; the method steps for connecting the bond post 202 and the bonding pad 211 by using the wire 203 are the same as those of the above embodiment, and will not be described here.
In other embodiments, when the conductive column is formed by the bottom conductive column and the top conductive column, part of the sacrificial layer and part of the isolation layer are removed first, the sacrificial layer surrounding the side wall of the bonding column is a protective medium layer, and the sacrificial layer surrounding the side wall of the conductive column and the isolation layer form a protective supporting layer together; a first device is then formed on the substrate and the bond posts and pads are connected using wires.
After forming the first device 201, the steps of:
with continued reference to fig. 22, a molding layer 204 is formed on the side of the first device 201 remote from the substrate 200, the molding layer 204 encapsulating the first device 201, the protective dielectric layer 212, the bond posts 202, and the leads 203. Specifically, there is a space between the molding layer 204 and the conductive pillars 207.
Referring to fig. 23, an adhesive layer (not shown) is applied to the side of the plastic layer 204 remote from the substrate 200, and then the second device 206 is fixed on the adhesive layer, and the front projection of the second device 206 on the substrate 200 covers the front projection of the plastic layer 204 on the substrate 200.
Further, the conductive wire 208 is used to connect the conductive post 207 and the pad 216 on the second device 206, one end of the conductive wire 208 is electrically connected to the pad 216 on the second device 206 to form a third bonding point f, and the other end of the conductive wire 208 is electrically connected to the conductive post 207 to form a fourth bonding point g.
In this embodiment, the step of electrically connecting the conductive wire 208 with the conductive post 207 to form the fourth bonding point g may also include: forming a groove on the conductive post 207; filling the grooves with bonding agent; one end of the conductive wire 208 is bonded to the top surface of the conductive post 207 and the top surface of the bonding agent.
In other embodiments, after the conductive line forms the fourth bond point on the conductive pillar, a dielectric layer is further formed on the top surface of the conductive pillar and around the fourth bond point, and the dielectric layer and the sacrificial layer remaining around the sidewall of the conductive pillar in the previous step together form a protective support layer.
Referring to fig. 23 and 4 in combination, a sealing layer 209 is formed on a side of the second device 206 remote from the substrate 200, and the sealing layer 209 wraps the second device 206, the conductive pillars 207, the protective support layer 217, and the conductive lines 208. Specifically, the sealing layer 209 is far away from the top surface of the substrate 200 and is higher than the conductive line neck portion h of the conductive line 208, so as to prevent the conductive line 208 from being damaged when other process steps are performed later. In addition, the sealing layer 209 may also be used to prevent the second device 206, the conductive post 207, and the protective support layer 217 from being damaged.
In this embodiment, the second device 206 is constituted by a single chip. In other embodiments, the second device may be a package including a plurality of chip stacks, and the chips are sequentially stacked along a direction in which the substrate points to the first device. In the direction perpendicular to the surface of the substrate, the height of the conductive column can be adjusted according to different connection modes between different chips and the conductive column, so that the height difference between the third bonding point and the fourth bonding point is reduced, and the connection strength between the conductive wire and the second device and the conductive column is improved.
In summary, in the semiconductor structure formed by the above method, the bonding post 202 is formed on the bonding pad 210, and the conductive post 207 is formed on the conductive pad 230, which is beneficial to reducing the bending degree of the lead 203 and the conductive wire 208, so as to ensure good connection strength between the lead 203 and the bonding post 202 and the bonding pad 211, and good connection strength between the conductive wire 208 and the conductive post 207 and the bonding pad 216. In addition, forming the protective dielectric layer 212 on the side wall of the bonding post 202 and forming the protective support layer 217 on the side wall of the conductive post 207 is beneficial to avoiding the bonding post 202 and the conductive post 207 from being deviated relative to the substrate 200 due to external force and to avoid the bonding post 202 and the conductive post 207 from toppling over.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of carrying out the invention and that various changes in form and details may be made therein without departing from the spirit and scope of the invention. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention is therefore intended to be limited only by the appended claims.

Claims (13)

1. A semiconductor structure, comprising:
a substrate and a bonding pad on the substrate;
a bond post located on a surface of the bond pad remote from the substrate and in contact with the bond pad;
a first device on the substrate and spaced apart from the bond post;
the welding pad is positioned on the surface of the first device away from the substrate;
a wire connecting the pad and the bond post;
a protective dielectric layer extending along sidewalls of the bond post;
a second device located on a side of the second control device remote from the substrate;
a conductive pad on the substrate, wherein the substrate exposes the surface of the conductive pad, and the conductive pad and the bonding pad are spaced from each other;
a bonding pad located on a surface of the second device away from the substrate;
a conductive pillar located on a surface of the conductive pad away from the substrate and in contact with the conductive pad, and having a top surface not lower than the top surface of the bonding pillar in a direction in which the substrate is directed toward the first device;
a protective support layer extending along a sidewall of the conductive pillar;
and one end of the conductive wire is electrically connected with the bonding pad, and the other end of the conductive wire is electrically connected with the conductive column.
2. The semiconductor structure of claim 1, wherein a difference in height between the bond post top surface and the bond pad top surface in a direction in which the substrate is directed toward the first device is no greater than a thickness of the bond pad.
3. The semiconductor structure of claim 2, wherein one end of the wire is electrically connected to the bond pad to form a first bond site, and the other end of the wire is electrically connected to the bond post to form a second bond site, the first bond site being not lower than the second bond site.
4. The semiconductor structure of claim 3, wherein the protective dielectric layer is disposed at the second bond site.
5. The semiconductor structure of claim 3, wherein the wire includes a wire neck portion at a bend of the wire extending up the first bond site, the protective dielectric layer and the first device having a space therebetween, the wire neck portion being located in the space.
6. The semiconductor structure of claim 5, further comprising: and the plastic sealing layer fills the space and covers the lead neck.
7. The semiconductor structure of claim 1, wherein the protective dielectric layer further surrounds sidewalls of the bond pad in a direction in which the substrate is directed toward the first device.
8. The semiconductor structure of claim 1, wherein an orthographic projection of an area enclosed by the bond post, the protective dielectric layer, the wire, and the first device on the substrate is a first projection, an orthographic projection of the second device on the substrate is a second projection, the second projection covers the first projection, and a combined orthographic projection of the conductive post and the protective support layer on the substrate is a third projection, the third projection being outside the first projection;
the semiconductor structure further includes: and the sealing layer covers the second device, the conductive column, the protective supporting layer and the conductive wire.
9. The semiconductor structure of claim 1, wherein the second device comprises a package of a plurality of stacked chips, and wherein the plurality of chips are stacked in sequence along a direction of the substrate toward the first device.
10. The semiconductor structure of claim 9, wherein a difference in height between a top surface of the conductive stud and a top surface of the pad, which are electrically connected to the same conductive line, is not greater than a thickness of the pad in a direction in which the substrate is directed toward the first device.
11. The semiconductor structure of claim 1, wherein a side of the bond post remote from the substrate has a recess, the recess being filled with a bonding agent; the wire is electrically connected with the bonding post to form a second bonding point, and the orthographic projection of the second bonding point on the substrate covers the orthographic projection of the groove on the substrate.
12. A method of fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a bonding pad;
forming bond posts on a surface of the bond pad remote from the substrate;
forming a protective dielectric layer on the side wall of the joint column;
forming a first device on the substrate, wherein a surface of the first device away from the substrate is provided with a welding pad, and the first device and the bonding post are mutually spaced;
connecting the bonding post and the welding pad by adopting a lead;
the substrate is provided with conductive pads which are mutually spaced from the bonding pads, and the surface of the conductive pads is exposed by the substrate; when the bonding post and the protective medium layer are formed, a conductive post and a protective supporting layer which are mutually separated from the bonding post are also formed, and the specific forming steps comprise:
Forming a sacrificial layer on the substrate, the sacrificial layer covering the bonding pad and the conductive pad;
patterning the sacrificial layer to form a through hole exposing the bonding pad and the conductive pad;
forming the bonding posts and the conductive posts filling the through holes, wherein the conductive posts are contacted with the conductive pads;
removing part of the sacrificial layer, wherein the residual sacrificial layer surrounding the side wall of the bonding post is the protective medium layer, and the residual sacrificial layer surrounding the side wall of the conductive post is the protective supporting layer;
after forming the first device, further comprising:
forming a plastic sealing layer on one side of the first device away from the substrate, wherein the plastic sealing layer wraps the first device, the bonding post and the lead;
forming a second device on a side of the molding layer away from the substrate;
and connecting the conductive column and the second device by adopting a conductive wire.
13. The method of fabricating a semiconductor structure as defined in claim 12, wherein the step of connecting the bond post and the bond pad using the wire comprises:
forming a groove on one side of the joint column away from the substrate;
filling the grooves with bonding agent;
One end of the wire is bonded to the pad, and the other end of the wire is bonded to the bond post top surface and the cement top surface.
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