CN113517255A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

Info

Publication number
CN113517255A
CN113517255A CN202110444203.XA CN202110444203A CN113517255A CN 113517255 A CN113517255 A CN 113517255A CN 202110444203 A CN202110444203 A CN 202110444203A CN 113517255 A CN113517255 A CN 113517255A
Authority
CN
China
Prior art keywords
bonding
pad
substrate
conductive
bond
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202110444203.XA
Other languages
Chinese (zh)
Other versions
CN113517255B (en
Inventor
张丽霞
刘杰
应战
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to CN202110444203.XA priority Critical patent/CN113517255B/en
Publication of CN113517255A publication Critical patent/CN113517255A/en
Application granted granted Critical
Publication of CN113517255B publication Critical patent/CN113517255B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H01L2224/48229—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item the bond pad protruding from the surface of the item

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The embodiment of the invention provides a semiconductor structure and a manufacturing method thereof, wherein the semiconductor structure comprises the following steps: the substrate is exposed out of the surface of the bonding pad; the bonding column is positioned on the surface of the bonding pad far away from the substrate and is contacted with the bonding pad; a first device on the substrate and spaced apart from the bond post; the welding pad is positioned on the surface of the first device far away from the substrate; the lead wire is connected with the welding pad and the bonding column; and the protective dielectric layer extends along the side wall of the bonding column. The embodiment of the invention is beneficial to improving the connection strength between the lead and the bonding column and between the lead and the bonding pad, and enhancing the protection effect on the bonding column so as to improve the stability of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The embodiment of the invention relates to the field of semiconductors, in particular to a semiconductor structure and a manufacturing method thereof.
Background
As the integration level and the integration level of semiconductor packages are gradually increased with the progress of technology, electronic devices are developed in the direction of miniaturization, high speed, high reliability, low cost, and low power consumption. Connections in semiconductor packages are typically made by wire bonding. Wire Bonding (Wire Bonding) is the interconnection of I/O terminals of a chip with corresponding package leads or pads on a substrate using wires. In the solid-phase welding process, heating, pressurizing and ultrasonic energy are adopted to destroy surface oxide layers and pollution, plastic deformation is generated, and the interface is in close contact with each other to generate electron sharing and atomic diffusion to form welding spots.
However, as the package integration is improved, the distance between the I/O terminal of the chip and the package lead or the pad on the substrate is further reduced, and since the I/O terminal of the chip is higher than the package lead or the pad on the substrate, when the wire forms the first bonding point on the I/O terminal of the chip and the second bonding point on the package lead or the pad of the substrate, the height difference between the first bonding point and the second bonding point is larger and the distance between the first bonding point and the second bonding point is smaller, so that the wire is bent to a larger extent, and the first bonding point and the second bonding point are prone to crack, which affects the stability of the semiconductor structure.
Disclosure of Invention
The technical problem to be solved by the embodiments of the present invention is to provide a semiconductor structure and a method for manufacturing the same, which are beneficial to improving the connection strength between a lead and a bonding post and between the lead and a bonding pad and improving the stability of the semiconductor structure.
To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: the substrate is exposed out of the surface of the bonding pad; the bonding column is positioned on the surface of the bonding pad far away from the substrate and is in contact with the bonding pad; a first device on the substrate and spaced apart from the bond post; the welding pad is positioned on the surface of the first device far away from the substrate; a lead connecting the pad and the bond post; a protective dielectric layer extending along sidewalls of the bond post.
Correspondingly, an embodiment of the present invention further provides a method for manufacturing a semiconductor structure, including: providing a substrate, wherein the substrate is provided with a bonding pad, and the surface of the bonding pad is exposed out of the substrate; forming a bonding column on the surface of the bonding pad far away from the substrate; forming a protective dielectric layer on the side wall of the bonding column; forming a first device on the substrate, wherein the surface of the first device, which is far away from the substrate, is provided with a welding pad, and the first device and the bonding column are mutually spaced; and connecting the bonding column and the welding pad by adopting a lead.
Compared with the related art, the technical scheme provided by the embodiment of the invention has the following advantages:
in the above technical solution, the substrate has a bonding post electrically connected to the bonding pad, and two ends of the lead are respectively in contact and electrical connection with the bonding post and the bonding pad on the first device, so as to realize transmission of electrical signals between the substrate and the first device. The bonding column is arranged on the bonding pad, so that in the direction of the substrate pointing to the first device, the height difference between two end points of the lead wire for connecting the bonding column and the bonding pad is favorably reduced, the bending radian of the lead wire is reduced, and even under the condition that the distance between two end points of the lead wire is reduced, the bending radian of the lead wire can be relieved by reducing the height difference between two end points of the lead wire, so that the connection strength between the lead wire and the bonding column and the bonding pad is favorably improved, and the stability of the semiconductor structure is improved. In addition, the protective dielectric layer extends along the side wall of the joint column, the protective dielectric layer at least surrounds the side wall of the joint column, so that the side wall of the joint column is prevented from being oxidized or corroded, the joint column is supported, and the joint column is prevented from shifting and toppling relative to the substrate when being influenced by external force.
Drawings
One or more embodiments are illustrated by corresponding figures in the drawings, which are not to scale unless specifically noted.
Fig. 1 to fig. 3 are schematic cross-sectional views of a semiconductor structure according to an embodiment of the present invention;
fig. 4 to 9 are schematic cross-sectional views of a semiconductor structure according to another embodiment of the present invention;
fig. 10 to 18 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to another embodiment;
fig. 19 to 23 are schematic structural views corresponding to steps in a method for forming a semiconductor structure according to yet another embodiment.
Detailed Description
As known from the background art, the connection strength between the lead and the I/O terminal of the chip and the package pin or the pad on the substrate needs to be improved, and the stability of the semiconductor structure needs to be improved.
Analysis shows that the distance between the I/O terminals of the chip and the package pins or pads on the substrate is inevitably further reduced in pursuit of higher package integration. At this time, the height difference between the I/O terminal of the chip and the package pin or the pad on the substrate further increases the bending degree of the lead connecting the I/O terminal of the chip and the package pin or the pad on the substrate, so that the lead is more likely to crack at the I/O terminal of the chip and the package pin or the pad on the substrate due to the excessive bending degree.
In order to solve the above problems, embodiments of the present invention provide a semiconductor structure and a method for fabricating the same, in which a bonding post is disposed on a bonding pad, so that a height difference between two end points of a lead connecting the bonding post and the bonding pad is advantageously reduced and a bending curvature of the lead is reduced in a direction in which a substrate is directed to a first device. In addition, the protective dielectric layer extends along the side wall of the joint column, the protective dielectric layer at least surrounds the side wall of the joint column, so that the side wall of the joint column is prevented from being oxidized or corroded, the joint column is supported, and the joint column is prevented from shifting relative to the substrate and toppling over when being influenced by external force.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that in various embodiments of the invention, numerous technical details are set forth in order to provide a better understanding of the present application. However, the technical solution claimed in the present application can be implemented without these technical details and various changes and modifications based on the following embodiments.
An embodiment of the present invention provides a semiconductor structure, which will be described in detail below with reference to the accompanying drawings. Fig. 1 to fig. 3 are schematic cross-sectional views of a semiconductor structure according to an embodiment of the invention.
Referring to fig. 1, a semiconductor structure includes: a substrate 100 and a bonding pad 110 on the substrate 100; a bonding post 102 located on a surface of the bonding pad 110 away from the substrate 100 and contacting the bonding pad 110; a first device 101 on the substrate 100 and spaced apart from the bond post 102; a pad 111 located on a surface of the first device 101 away from the substrate 100; a lead 103, the lead 103 connecting the pad 111 and the bond post 102; a protective dielectric layer 112 extending along the sidewalls of the bond post 102.
Specifically, the substrate 100 exposes the surface of the bonding pad 110, and the bonding post 102 is in contact with and electrically connected to the bonding pad 110, so that an electrical signal can be transmitted between the substrate 100 and the bonding pad 111 through the bonding post 102 and the wire 103.
In addition, the side of the substrate 100 away from the bonding pads 110 may further have package pads 120 for positioning the substrate 100 when it is connected to other structures. The bonding pad 110 and the package pad 120 may be made of at least one of conductive materials such as gold, aluminum, copper, gold-based alloy, or aluminum-based alloy. Specifically, an aluminum-based alloy refers to a material that contains more than 50% aluminum, for example, an aluminum material may be doped with silicon (e.g., 1% silicon).
The height difference between the top surface of the bonding post 102 and the top surface of the pad 111 in the direction in which the substrate 100 points toward the first device 101 is not greater than the thickness of the pad 111. Thus, the height difference between the two end points of the lead 103 connecting the bonding column 102 and the pad 111 is controlled to fluctuate within the thickness range of the pad 111, which is beneficial to ensuring that the two end points of the lead 103 have a lower height difference, thereby being beneficial to relieving the bending degree of the lead 103, being beneficial to improving the connection strength between the lead 103 and the bonding column 102 and the pad 111, and improving the stability of the semiconductor structure.
Further, one end of the wire 103 is in contact with the pad 11 and electrically connected to form a first bonding point a, the other end of the wire 103 is in contact with the bonding post 102 and electrically connected to form a second bonding point b, and the first bonding point a is not lower than the second bonding point b.
In other embodiments, the first bonding point may be slightly lower than the second bonding point, and it is only necessary to ensure that the height difference between the first bonding point and the second bonding point is not greater than the thickness of the pad.
In some examples, with continued reference to fig. 1, the first bond site a is a wedge bond site, a portion of the lead 103 proximate the first bond site a extends in a direction parallel to a top surface of the pad 111, and a top surface of the bond post 102 is flush with the top surface of the pad 111. Further, the second bond point b is also a wedge bond point, and a portion of the wire 103 near the second bond point b extends in a direction parallel to the top surface of the bond post 102.
In wedge bonding, a portion of the wire 103 near the first bond point a extends in a direction parallel to the top surface of the pad 111, and an included angle between a tangential direction of the wire 103 at the first bond point a and the top surface of the pad 111 is a small acute angle, for example, the acute angle is smaller than 45 °, and when the top surface of the bond post 102 is flush with the top surface of the pad 111, it is beneficial to ensure that the first bond point a and the second bond point b are located on a same plane, so that an included angle between the tangential direction of the wire 103 at the second bond point b and the top surface of the bond post 102 is also a small acute angle, thereby alleviating a bending degree of the wire 103, reducing a magnitude of a force generated by the wire 103 at the first bond point a, and reducing a magnitude of a force generated by the wire 103 at the second bond point b, and further reducing a probability of cracking of the first bond point a and the second bond point b.
In still other examples, referring to fig. 2, the first bond site a comprises a ball bond site, a portion of the lead 103 proximate the first bond site a extends in a direction perpendicular to a top surface of the pad 111, and the top surface of the bond post 102 is higher than the top surface of the pad 111. Further, the second bond point b is also a wedge bond point, and a portion of the wire 103 near the second bond point b extends in a direction parallel to the top surface of the bond post 102.
In ball bonding, a portion of the wire 103 near the first bonding point a extends in a direction perpendicular to the top surface of the pad 111, and an included angle between a tangential direction of the wire 103 at the first bonding point a and the top surface of the pad 111 is a large acute angle, for example, the acute angle is greater than 45 °, and when the top surface of the bond post 102 is higher than the top surface of the pad 111, an included angle between a tangential direction of the wire 103 at the second bonding point b and the top surface of the bond post 102 can be reduced, so that the included angle is a small acute angle, thereby alleviating a bending degree of the wire 103, reducing a magnitude of a force generated by the wire 103 at the first bonding point a, and reducing a magnitude of a force generated by the wire 103 at the second bonding point b, and further reducing a probability of cracking of the first bonding point a and the second bonding point b.
In other embodiments, the second bond site may also be a ball bond site.
Referring to fig. 3, fig. 3 is a schematic cross-sectional view of a region I in fig. 2. The side of the bond post 102 away from the substrate 100 has a groove filled with a bonding agent 149, specifically, the groove can be filled with the bonding agent 149; an orthogonal projection of the second bond site b on the substrate 100 covers an orthogonal projection of the recess on the substrate 100.
The bonding post 102 and the lead 103 may be made of at least one of conductive materials such as gold, aluminum, copper, gold-based alloy, or aluminum-based alloy.
In addition, since the bond post 102 and the wire 103 may form an alloy interface at the second bond point b, they are easily oxidized, which may cause the connection strength of the wire 103 with the bond post 102 at the second bond point b to be reduced. The area of the bonding column 102 corresponding to the second bonding point b is provided with a groove, and the groove is filled with the bonding agent 149, so that the excellent bonding effect of the bonding agent 149 is facilitated, the connection strength between the second bonding point b and the bonding column 102 is improved, and the probability of cracking of the second bonding point b is further reduced. The material of the bonding agent 149 includes epoxy resin, silicone, or polyvinyl acetate.
In the present embodiment, the cross-sectional shape of the bond post 102 is rectangular in the direction in which the substrate 100 points toward the first device 101, and the bond post 102 may be a cylindrical structure, an elliptical-cylindrical structure, or a square-cylindrical structure. In other embodiments, the cross-sectional shape of the bonding post may also be a regular trapezoid, and the bonding post may be a circular truncated cone structure, which is beneficial to increase the contact area between the bonding post and the substrate, enhance the supporting effect of the substrate on the bonding post, and is beneficial to improve the stability of the bonding post.
In this embodiment, the lead 103 includes a lead neck portion c, the lead neck portion c is located at a bending position where the lead 103 extends upward along the first bonding point a, a space is provided between the protective dielectric layer 112 and the first device 101, and the lead neck portion c is located in the space.
Since the lead neck c is located at a bending position where the lead 103 extends upward along the first bonding point a, the lead neck c is the highest point of the lead 103 in a direction in which the substrate 100 points to the first device 101.
When the bond post 102 and the pad 111 are connected by the wire 103, a first force acting in a direction away from the pad 111 is generated at the first bond site a, and a second force acting in a direction away from the bond post 102 is generated at the second bond site b. Because the neck c of the lead is positioned in the space between the protective dielectric layer 112 surrounding the side wall of the bonding post 102 and the bonding pad 111, the included angle between the tangential direction of the lead 103 at the first bonding point a and the top surface of the bonding pad 111 and the included angle between the tangential direction of the lead 103 at the second bonding point b and the top surface of the bonding post 102 are reduced, the bending degree of the lead 103 is relieved, the size of a first acting force generated by the lead 103 at the first bonding point a is reduced, the size of a second acting force generated by the lead 103 at the second bonding point b is reduced, and the probability of cracking of the first bonding point a and the second bonding point b is further reduced.
In addition, the lead neck portion c is located in the space between the protective dielectric layer 112 and the pad 111, and the height difference between the first bonding point a and the second bonding point b is small, so that the space between the protective dielectric layer 112 and the pad 111 can be reduced under the condition that the bending degree of the lead 103 is small, the packaging density of the semiconductor structure is improved, and meanwhile, the good connection strength between the lead 103 and the bonding post 102 and the pad 111 is ensured.
In this embodiment, the protective dielectric layer 112 extends along the sidewalls of the bond post 102 and surrounds the sidewalls of the bond pad 110 in addition to the sidewalls of the bond post 102, so as to prevent the sidewalls of the bond post 102 and the bond pad 110 from being oxidized or corroded, and to support the bond post 102 and the bond pad 110, so as to prevent the bond post 102 and the bond pad 110 from shifting relative to the substrate 100 and from falling down when being affected by an external force. The material of the protective dielectric layer 112 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
In other embodiments, the protective dielectric layer may also be located at the second bonding point, that is, the protective dielectric layer is also located on the top surface of the bonding post, which is beneficial to prevent the second bonding point from being oxidized or corroded, so as to ensure good connection strength of the wire at the top surface of the bonding post, or the protective dielectric layer may also be located only on the sidewall of the bonding post.
The semiconductor structure further includes: and the plastic packaging layer 104, wherein the plastic packaging layer 104 fills the space between the protective dielectric layer 112 and the bonding pad 111 and covers the neck part c of the lead.
The plastic package layer 104 covers the lead neck c, which is beneficial to protecting the lead 103 from being interfered by other structures, and in addition, the plastic package layer 104 has a good supporting and reinforcing effect on the lead neck c, which is beneficial to further reducing the probability of cracking of the first bonding point a and the second bonding point b. The material of the molding layer 104 includes an electrical insulating material such as a polymer resin or a low temperature thermal glass composite material.
In addition, the molding compound layer 104 also wraps the first device 101, the bond post 102, and the protective dielectric layer 112 to protect the first device 101, the bond post 102, and the protective dielectric layer 112 from interference from other structures.
In this embodiment, an adhesive layer 105 may be further provided between the first device 101 and the substrate 100 to enhance the connection strength between the first device 101 and the substrate 100.
In this embodiment, the first device 101 may be a control device or a memory device. It should be noted that, in other embodiments, the function of the first device is not limited, and the first device is a semiconductor device commonly used in a semiconductor structure.
In summary, the bonding pad 110 has the bonding post 102 thereon, and in the direction in which the substrate 100 points to the first device 101, it is beneficial to reduce the height difference between two end points of the wire 103 connecting the bonding post 102 and the pad 111, so as to reduce the bending degree of the wire 103, and even in the case that the distance between the protective dielectric layer 112 and the pad 111 is reduced, the bending degree of the wire 103 can be relieved by the reduced height difference between two end points of the wire 103, so as to be beneficial to reduce the probability of cracking of the first bonding point a and the second bonding point b. In addition, the protective dielectric layer 112 surrounding the sidewalls of the bond post 102 and the bond pad 110 has a good supporting effect on the bond post 102 and the bond pad 110, which is beneficial to prevent the bond post 102 and the bond pad 110 from shifting relative to the substrate 100 and from falling down when being affected by an external force, and is beneficial to prevent the sidewalls of the bond post 102 and the bond pad 110 from being oxidized or corroded.
Yet another embodiment of the present invention provides a semiconductor structure, which is substantially the same as the previous embodiment, with the main difference that a second device is further provided on a side of the first device away from the substrate. A method for fabricating a semiconductor structure according to another embodiment of the present invention will be described in detail with reference to the accompanying drawings, and it should be noted that the same or corresponding portions as those in the foregoing embodiments can refer to the detailed description of the foregoing embodiments, and are not repeated herein.
Fig. 4 to 9 are schematic cross-sectional views of a semiconductor structure according to another embodiment of the invention.
Referring to fig. 4, the semiconductor includes: a substrate 200 and a bonding pad 210 disposed on the substrate 200, wherein the surface of the bonding pad 210 is exposed by the substrate 200; a bonding post 202 located on the surface of the bonding pad 210 away from the substrate 200 and contacting the bonding pad 210; a first device 201 on the substrate 200 and spaced apart from the bond post 202; a bonding pad 211 located on a surface of the first device 201 away from the substrate 200; a lead 203, the lead 203 connecting the pad 211 and the bond post 202; a protective dielectric layer 212 extending along the sidewalls of the bond post 202.
On the basis, the semiconductor structure further comprises: a second device 206 located on a side of the first device 201 away from the substrate 200; a conductive pad 230 disposed on the substrate 200, wherein the substrate 200 exposes a surface of the conductive pad 230, and the conductive pad 230 is spaced apart from the bonding pad 210; a bonding pad 216 located on a surface of the second device 206 away from the substrate 200; a conductive post 207 located on the surface of the conductive pad 230 away from the substrate 200 and contacting the conductive pad 230, wherein the top surface of the conductive post 207 is not lower than the top surface of the bonding post 202 in the direction of the substrate 200 pointing to the first device 201; a protective support layer 217 extending along the sidewalls of the conductive pillars 207; and a conductive wire 208, one end of the conductive wire 208 is in contact and electric connection with the welding pad 216, and the other end of the conductive wire 208 is in contact and electric connection with the conductive column 207.
Specifically, the conductive post 207 is in electrical contact with the conductive pad 230 such that electrical signals can be communicated between the substrate 200 and the conductive post 207.
In this embodiment, the first device 201 is a control device and the second device 206 is a memory device. It should be noted that, in other embodiments, the functions of the first device and the second device are not limited, and both the first device and the second device are semiconductor devices commonly used in a semiconductor structure.
Specifically, one end of the conductive line 208 is bonded to the pad 216 to form a third bonding point f, and the other end of the conductive line 208 is electrically connected to the conductive post 207 to form a fourth bonding point g.
In this embodiment, the third bonding point f and the fourth bonding point g are both wedge-shaped bonding points, and in other embodiments, the third bonding point and the fourth bonding point may also be both spherical bonding points, or the third bonding point is a wedge-shaped bonding point, and the fourth bonding point is a spherical bonding point, or the third bonding point is a spherical bonding point, and the fourth bonding point is a wedge-shaped bonding point.
In this embodiment, a groove may also be formed on a side of the conductive pillar 207 away from the substrate 200, and the groove is filled with a bonding agent; the orthographic projection of the fourth bonding point g on the substrate 200 covers the orthographic projection of the groove on the substrate 200.
Further, in a direction in which the substrate 200 points to the first device 201, the cross-sectional shape of the conductive pillar 207 is rectangular, and the conductive pillar 207 may have a cylindrical structure, an elliptical cylindrical structure, or a square cylindrical structure. In other embodiments, the cross-sectional shape of the conductive pillar may also be a regular trapezoid, and then the conductive pillar may be a circular truncated cone structure.
The conductive posts 207 and the conductive wires 208 may be made of at least one of gold, aluminum, copper, gold-based alloy, or aluminum-based alloy.
The conductive line 208 includes a conductive line neck h, the conductive line neck h is located at a bend of the conductive line 208 extending upward along the third bonding point f, a space is provided between the conductive pillar 207 and the pad 216, and the conductive line neck h is located in the space.
When the conductive line 208 is used to connect the conductive pillar 207 and the pad 216 on the second device 206, a third force acting in a direction away from the pad 216 is generated at the third bonding point f, and a fourth force acting in a direction away from the conductive pillar 207 is generated at the fourth bonding point g. Because the neck h of the conductive wire is located in the interval between the conductive post 207 and the pad 216, an included angle between the tangential direction of the conductive wire 208 at the third bonding point f and the top surface of the pad 216 is favorably reduced, an included angle between the tangential direction of the conductive wire 208 at the fourth bonding point g and the top surface of the conductive post 207 is reduced, the bending degree of the conductive wire 208 is relieved, and therefore the size of the third acting force generated by the conductive wire 208 at the third bonding point f is favorably reduced, the size of the fourth acting force generated by the conductive wire 208 at the fourth bonding point g is reduced, and the probability of cracking of the third bonding point f and the fourth bonding point g is further reduced.
In this embodiment, the protective supporting layer 217 extends along the sidewalls of the conductive pillars 207 and surrounds the sidewalls of the conductive pads 230 in addition to the sidewalls of the conductive pillars 207, so as to advantageously prevent the sidewalls of the conductive pillars 207 and the sidewalls of the conductive pads 230 from being oxidized or corroded, and to support the conductive pillars 207 and the conductive pads 230, so as to advantageously prevent the conductive pillars 207 and the conductive pads 230 from shifting relative to the substrate 200 and from toppling over when being affected by an external force. Wherein the material of the protective support layer 217 includes at least one of silicon oxide, silicon nitride, or silicon oxynitride.
In other embodiments, the protective supporting layer may also be located at the fourth bonding point, that is, the protective supporting layer is also located at the top surface of the conductive pillar, which is beneficial to prevent the fourth bonding point from being oxidized or corroded, so as to ensure good connection strength of the conductive line at the top surface of the conductive pillar, or the protective supporting layer may also be located only at the sidewall of the conductive pillar.
In this embodiment, an orthogonal projection of an area surrounded by the bonding post 202, the protective dielectric layer 212, the wire 203, and the first device 201 on the substrate 200 is a first projection, an orthogonal projection of the second device 206 on the substrate 200 is a second projection, the second projection covers the first projection, and a combined orthogonal projection of the conductive post 207 and the protective support layer 217 on the substrate 200 is a third projection, and the third projection is located outside the first projection.
In addition, a molding compound layer 204 is arranged between the first device 201 and the second device 206, and the molding compound layer 204 wraps the first device 201, the bonding column 202, the protective dielectric layer 212 and the lead 203. When the second projection covers the first projection, due to the presence of the molding layer 204, when the second device 206 is formed on the first device 201, the bottom surface of the second device 206 is prevented from contacting the lead 203, resulting in damage to the lead 203.
It should be noted that, in other embodiments, the orthographic projection of the first device on the substrate may also be smaller than the orthographic projection of the second device on the substrate, and only by wrapping the first device, the bonding post, the protective dielectric layer, and the lead wire with the plastic sealing layer, a good protection effect on the lead wire can be achieved, and the second device is prevented from contacting the lead wire.
The semiconductor structure further includes: a sealing layer 209, the sealing layer 209 covering the second device 206, the conductive pillars 207, the protective support layer 217, and the conductive lines 208. The sealing layer 209 covers the conductive wire neck h, so that the conductive wire 208 is protected from being interfered by other structures, and in addition, the sealing layer 209 has a good supporting and reinforcing effect on the conductive wire neck h, so that the probability of cracking of the third bonding point f and the fourth bonding point g is further reduced. The material of the sealing layer 209 includes an electrical insulating material such as a polymer resin or a low temperature thermal glass composite.
Further, the orthographic projection of the sealing layer 209 on the substrate 200 covers the substrate 200, and has a good protection effect on the substrate 200.
In some examples, the second device 206 is formed from a single chip, and the semiconductor structure will be described below with reference to fig. 4 and 5.
In one example, referring to fig. 4, the top surface of the bond post 202 is flush with the top surface of the conductive post 207, and the bond post 202 is a single layer structure.
In yet another example, referring to fig. 5, in a direction in which the substrate 200 points toward the first device 201, a height difference between the top surface of the conductive post 207 and the top surface of the pad 216 is not greater than a thickness of the pad 216.
Specifically, the top surface of the conductive post 207 is flush with the top surface of the pad 216, which is beneficial to ensuring that the third bonding point f and the fourth bonding point g are located on the same plane, so that the included angle between the tangential direction of the conductive wire 208 at the third bonding point f and the top surface of the pad 216 is a small acute angle, for example, the acute angle is smaller than 45 °, and the included angle between the tangential direction of the conductive wire 208 at the fourth bonding point g and the top surface of the conductive post 207 is also a small acute angle, thereby alleviating the bending degree of the conductive wire 208, reducing the magnitude of the acting force generated by the conductive wire 208 at the third bonding point f, reducing the magnitude of the acting force generated by the conductive wire 208 at the fourth bonding point g, and further reducing the probability of cracking of the third bonding point f and the fourth bonding point g.
In other embodiments, the top surface of the conductive pillar may be slightly lower than the top surface of the pad, or the top surface of the conductive pillar may be slightly higher than the top surface of the pad, so as to ensure that the third bonding point and the fourth bonding point have a lower height difference.
In still other examples, the second device 206 includes a plurality of stacked chips, and the chips are stacked in sequence along the direction of the substrate 200 toward the first device 201, each chip having a pad 216 exposed on a surface of the chip away from the substrate 200. The semiconductor structure will be described below with reference to fig. 6 and 9.
It should be noted that the second device 206 illustrated in fig. 6 to 9 includes three chips stacked in sequence, and adjacent chips are connected together through the adhesive layer 219. In other embodiments, the number of chips is not limited, and the connection manner between adjacent chips is not limited.
In one example, referring to fig. 6, at least one pad 216 of different chips is electrically connected to the same conductive post 207, the top surface of the conductive post 207 is flush with the top surface of the bonding post 202, and the conductive post 207 has a single-layer structure.
Specifically, the pads 216 on different chips are electrically connected to the same conductive post 207 by different conductive lines 208. Because the conductive post 207 is disposed on the conductive pad 230, the height difference between the third bonding point f and the fourth bonding point g can be reduced to different extents, so as to reduce the curvature of the conductive wire 208 to different extents, thereby reducing the probability of cracking between the third bonding point f and the fourth bonding point g.
In yet another example, referring to fig. 7, at least one pad 216 of different chips is electrically connected to the same conductive pillar 207, and the chip close to the second device 206 is the bottom chip 226, and the height difference between the top surface of the conductive pillar 207 and the top surface of the pad 216 on the bottom chip 226 in the direction in which the substrate 200 points to the first device 201 is not greater than the thickness of the pad 216.
Specifically, the top surface of the conductive post 207 is flush with the top surface of the pad 216 on the bottom chip 226, which is beneficial to ensuring that the third bonding point f and the fourth bonding point g on the pad 216 on the bottom chip 226 are located on the same plane, so that the included angle between the tangential direction of the conductive wire 208 at the third bonding point f and the top surface of the pad 216 is a smaller acute angle, and the included angle between the tangential direction of the fourth bonding point g connected with the same conductive wire 208 with the third bonding point f and the top surface of the conductive post 207 is also a smaller acute angle, thereby further alleviating the bending degree of the conductive wire 208, and further reducing the probability of cracking of the third bonding point f and the fourth bonding point g.
In addition, the top surfaces of the conductive pillars 207 are flush with the top surfaces of the pads 216 on the bottom chip 226, which, on one hand, is beneficial to reducing the length of the conductive line 208, thereby reducing the resistance of the conductive line 208, and thus is beneficial to increasing the transmission rate of electrical signals on the conductive line 208; on the other hand, it is advantageous to prevent short circuits between adjacent conductive lines 208.
In other embodiments, the top surface of the conductive pillar may be slightly lower than the top surface of the pad on the bottom chip, or the top surface of the conductive pillar may be slightly higher than the top surface of the pad on the bottom chip, so as to ensure that the third bonding point and the fourth bonding point have a lower height difference.
In another example, referring to fig. 8, in the direction in which the substrate 200 points toward the first device 201, the height difference between the top surfaces of the conductive pillars 207 electrically connected to the same conductive line 208 and the top surfaces of the pads 216 is not greater than the thickness of the pads 216.
Specifically, in the conductive post 207 and the pad 216 electrically connected to the same conductive line 208, the top surface of the conductive post 207 is flush with the top surface of the pad 216, which is beneficial to further alleviating the bending degree of each conductive line 208, thereby further reducing the probability of cracking of the third bonding point f and the fourth bonding point g. In addition, the different conductive lines 208 are located on different planes, which is advantageous to further prevent short circuits between adjacent conductive lines 208.
In other embodiments, in the conductive pillar and the pad electrically connected to the same conductive line, the top surface of the conductive pillar may be slightly lower than the top surface of the pad, or the top surface of the conductive pillar may be slightly higher than the top surface of the pad, so as to ensure that the third bonding point and the fourth bonding point have a lower height difference.
In yet another example, referring to fig. 9, second devices 206 have exposed sidewalls of pads 216, a metal layer is disposed between pads 216 of adjacent second devices 206 for electrically connecting pads 216 of adjacent second devices 206, pads 216 and metal layer together form an electrical connection structure, and one end of conductive line 208 is electrically connected to a top surface of the electrical connection structure.
In this embodiment, the bonding pad 216 and the metal layer are integrated, so that different chips can be electrically connected to the same conductive pillar 207 through the same conductive line 208, which is beneficial to reducing the number of the conductive lines 208. In addition, the top surface of the conductive pillar 207 and the top surface of the electrical connection structure may be flush, which, on one hand, is beneficial to reducing the length of the conductive line 208, thereby reducing the resistance of the conductive line 208; on the other hand, the bending degree of the conductive wire 208 is favorably relieved, so that the probability of cracking of the third bonding point f and the fourth bonding point g is reduced.
In the above example, the conductive post 207 may have a single-layer structure or a stacked-layer structure. Moreover, the protective supporting layer 217 corresponds to the conductive pillars 207 surrounded by the protective supporting layer 217 one by one, and the top surface of the protective supporting layer 217 is flush with the top surfaces of the conductive pillars 207 corresponding to the protective supporting layer 217, so as to protect and support the sidewalls of the conductive pillars 217 comprehensively.
In summary, the bonding pad 210 has the bonding pillar 202, which is beneficial to reduce the height difference between two end points of the wire 203 connecting the bonding pillar 202 and the pad 211, so as to reduce the bending degree of the wire 203, thereby ensuring good connection strength between the wire 203 and the bonding pillar 202 and the pad 211. In addition, the conductive pad 230 has the conductive pillar 207 thereon, which is beneficial to reduce the height difference between the third bonding point f and the fourth bonding point g, so as to reduce the bending degree of the conductive wire 208, and thus is beneficial to reduce the probability of cracking of the third bonding point f and the fourth bonding point g. Moreover, since the degree of bending of the conductive lines 208 can be reduced, the overall thickness of the semiconductor structure can be reduced, leading to a trend toward smaller dimensions.
In addition, the protective support layer 217 surrounding the sidewalls of the conductive pillars 207 and the conductive pads 230 has a good supporting effect on the conductive pillars 207 and the conductive pads 230, and is beneficial for preventing the sidewalls of the conductive pillars 207 and the conductive pads 230 from being oxidized or corroded.
Accordingly, another embodiment of the present invention further provides a method for manufacturing a semiconductor structure, which is used to form the semiconductor structure described in the above embodiment.
Fig. 10 to fig. 18 are schematic structural diagrams corresponding to steps in the method for forming a semiconductor structure according to the present embodiment.
Referring to fig. 10 to 17, a method of fabricating a semiconductor structure includes: providing a substrate 100, wherein the substrate 100 has a bonding pad 110 thereon; forming bonding posts 102 on the surface of the bonding pads 110 away from the substrate 100; a protective dielectric layer 112 is formed on the sidewalls of the bond post 102.
Specifically, forming the bond post 102 and the protective dielectric layer 112 includes the steps of:
referring to fig. 10, a sacrificial layer 129 is formed on a substrate 100 having a bonding pad 110 and a package pad 120 thereon, and the substrate 100 exposes the surfaces of the bonding pad 110 and the package pad 120. Specifically, the substrate 100 has a first side and a second side opposite to each other, the bonding pads 110 are located on the first side, and the package pads 120 are located on the second side. The material of the sacrificial layer 129 may be at least one of silicon oxide, silicon nitride, or silicon oxynitride.
Referring to fig. 11, a mask layer 139 with openings is formed on the substrate 100, and a space for accommodating the first device 101 is reserved between adjacent openings. The material of the mask layer 139 may be photoresist.
Referring to fig. 12, the sacrificial layer 129 is patterned by using the mask layer 139 as a mask to form a via hole 10 exposing the bonding pad 110 on the substrate 100; the mask layer 139 is removed.
Referring to fig. 13, a bonding post 102 is formed to fill the via 10, and the material of the bonding post 102 is at least one of conductive materials such as gold, aluminum, copper, gold-based alloy, or aluminum-based alloy.
In some examples, referring to fig. 14, a portion of the sacrificial layer 129 (see fig. 13) is removed, the sacrificial layer 129 surrounding the sidewalls of the bond post 102 remains as the protective dielectric layer 112, the adhesive layer 105 is applied to the bottom surface of the first device 101 adjacent to the substrate 100, and the first device 101 coated with the adhesive layer 105 is then placed on the surface of the substrate 100. In addition, the first device 101 is located in the space between adjacent bond posts 102 with a space between the first device 101 and each bond post 102 to provide sufficient clearance for subsequent use of wire bonds to electrically connect the bond pads 111 on the first device 101 and the bond posts 102. In other examples, an adhesive layer may be applied to the substrate and the first device may then be secured to the adhesive layer.
Referring to fig. 15, a bond post 102 and a pad 111 are connected using a wire 103, one end of the wire 103 being electrically connected to the first device 101 to form a first bond point a, and the other end of the wire 103 being electrically connected to the bond post 102 to form a second bond point b.
Further, the step of connecting the bonding post 102 and the pad 111 by the wire 103 may further include: referring to fig. 16, fig. 16 is a schematic cross-sectional view of the region II in fig. 15, wherein a groove is formed on the bond post 102; the groove is filled with a bonding agent 149; one end of the wire 103 is bonded to the top surface of the bond post 102 and the top surface of the bonding agent 149 and the other end of the wire 103 is bonded to the pad 111.
In other embodiments, after the wire forms the second bond site on the bond post, a dielectric layer is also formed on the top surface of the bond post and around the second bond site, and the dielectric layer and the sacrificial layer remaining around the sidewall of the bond post in the previous step together form a protective dielectric layer.
Referring to fig. 15 and fig. 1 in combination, a molding compound 104 is formed on a side of the first device 101 away from the substrate 100, and the molding compound 104 encapsulates the first device 101, the bonding posts 102, and the leads 103. Specifically, the top surface of the molding layer 104 away from the substrate 100 is higher than the lead neck portion c of the lead 103, so as to prevent the lead 103 from being damaged when other process steps are performed subsequently. In addition, the molding layer 104 may also be used to protect the first device 101 and the bond post 102 from damage.
In still other examples, referring to fig. 17, the sacrificial layer 129 is patterned again, forming a locating groove between adjacent bond posts 102 for receiving the first device 101; the adhesive layer 105 is coated on the bottom surface of the first device 101 near the substrate 100, and then the first device 101 coated with the adhesive layer 105 is placed on the bottom of the positioning groove. Since the positioning groove for accommodating the first device 101 is formed in advance on the sacrifice layer 129 before the first device 101 is mounted on the substrate 100, accurate positioning of the mounting position of the first device 101 is facilitated.
Referring to fig. 18, the bond post 102 and the pad 111 are connected using a wire 103, one end of the wire 103 is electrically connected to the first device 101 to form a first bond point a, and the other end of the wire 103 is electrically connected to the bond post 102 to form a second bond point b, which is not lower than the first bond point a in a direction in which the substrate 100 is directed to the first device 101.
When the lead 103 is bonded with the pad 111 on the first device 101, a large pressing force is generated on the pad 111 at the first bonding point a, and when the lead 103 is bonded with the top surface of the bonding post 102, a large pressing force is generated on the bonding post 102 at the second bonding point b, at this time, the sacrificial layers 129 are wrapped on the side walls of the bonding post 102 and the first device 101, so that the bonding post 102 and the first device 101 are well supported, and the bonding post 102 and the first device 101 are prevented from being deviated or inclined at positions on the substrate 100 after being subjected to the pressing force, thereby being beneficial to improving the yield of the formed semiconductor structure.
In this example, the step of connecting the bonding post 102 and the pad 111 by the wire 103 may further include: forming a groove on the bond post 102; filling the groove with a bonding agent; one end of the wire 103 is bonded to the top surface of the bond post 102 and the top surface of the bonding agent and the other end of the wire 103 is bonded to the pad 111.
Referring collectively to fig. 18 and fig. 1, a portion of the sacrificial layer 129 is removed, leaving the sacrificial layer 129 surrounding the sidewalls of the bond post 102 as the protective dielectric layer 112.
Further, a molding compound layer 104 is formed on a side of the first device 101 away from the substrate 100, and the molding compound layer 104 wraps the first device 101, the protective dielectric layer 112, the bonding posts 102 and the leads 103. Specifically, the top surface of the molding layer 104 away from the substrate 100 is higher than the lead neck portion c of the lead 103, so as to prevent the lead 103 from being damaged when other process steps are performed subsequently. In addition, the molding layer 104 may also be used to protect the first device 101, the protective dielectric layer 112, and the bond post 102 from damage.
In summary, in the semiconductor structure formed by the above method, the bonding pillar 102 is formed on the bonding pad 110, which is beneficial to reducing the bending degree of the wire 103, and thus is beneficial to reducing the probability of cracking of the first bonding point a and the second bonding point b. In addition, the formation of the protective dielectric layer 112 on the sidewalls of the bond post 102 is advantageous for preventing the bond post 102 from shifting or tilting relative to the substrate 100 when being affected by an external force.
In another embodiment of the present invention, a method for fabricating a semiconductor structure is provided, which is used to form the semiconductor structure described in the above another embodiment.
Fig. 19 to 23 are schematic structural diagrams corresponding to steps in the method for forming a semiconductor structure according to the present embodiment.
Referring to fig. 19 to 22, the method of fabricating a semiconductor structure includes: the substrate 200 has a conductive pad 230 spaced apart from the bonding pad 210, and the substrate 200 exposes a surface of the conductive pad 230; in forming the bond posts 202 and the protective dielectric layer 212, conductive posts 207 and a protective support layer 217 are also formed spaced from the bond posts 202.
In this embodiment, the formation of the bonding posts 202, the protective dielectric layer 212, the conductive posts 207, and the protective support layer 217 includes the following steps:
referring to fig. 19, the bonding pad 210 and the conductive pad 230 are located on the same surface of the substrate 200, and a sacrificial layer 229 is formed on the substrate 200, wherein the sacrificial layer 229 covers the bonding pad 210 and the conductive pad 230.
A mask layer 239 having an opening is formed on the substrate 200, and an orthogonal projection of the opening on the substrate 200 coincides with an orthogonal projection of the bonding pad 210 or the conductive pad 230 on the substrate 200. The material of the mask layer 239 may be a photoresist.
Referring to fig. 20, the sacrificial layer 229 is patterned by using the mask layer 239 (see fig. 19) as a mask to form a via hole 20 exposing the bonding pad 210 and the conductive pad 230 on the substrate 200; the mask layer 239 is removed.
Referring to fig. 21, a bonding pillar 202 and a conductive pillar 207 are formed to fill the via 20, wherein the bonding pillar 202 contacts the bonding pad 210, the conductive pillar 207 contacts the conductive pad 230, the bonding pillar 202 and the conductive pillar 207 are made of the same material, and the bonding pillar 202 and the conductive pillar 207 are made of at least one conductive material such as gold, aluminum, copper, or a composite material of silicon and aluminum.
In other embodiments, a sacrificial layer is formed on a substrate; patterning the sacrificial layer, and forming a first through hole exposing the bonding pad and the conductive pad on the substrate, and then forming a bonding column and a bottom conductive column which are filled with the first through hole; forming an isolation layer on one side of the sacrificial layer far away from the substrate, wherein the isolation layer covers the bonding column and the bottom conductive column; patterning the isolation layer to form a second through hole exposing the bottom conductive column; and forming a top conductive column filled with the second through hole, wherein the bottom conductive column and the top conductive column jointly form a conductive column.
Referring to fig. 22, a portion of the sacrificial layer 229 (see fig. 21) is removed, leaving the sacrificial layer 229 around the sidewalls of the bond posts 202 as the protective dielectric layer 212 and leaving the sacrificial layer 229 around the sidewalls of the conductive posts 207 as the protective support layer 217.
Further, a first device 201 is formed on the substrate 200; the steps of the method for connecting the bonding post 202 and the bonding pad 211 by the wire 203 are the same as those of the above embodiments, and are not described herein.
In other embodiments, when the conductive pillars are formed by the bottom conductive pillars and the top conductive pillars, a portion of the sacrificial layer and a portion of the isolation layer are removed first, the remaining sacrificial layer surrounding the sidewalls of the bonding pillars is a protective dielectric layer, and the remaining sacrificial layer surrounding the sidewalls of the conductive pillars and the isolation layer form a protective supporting layer; a first device is then formed on the substrate and bond posts and pads are connected using wire bonds.
After the first device 201 is formed, the following steps are also included:
with continued reference to fig. 22, a molding compound 204 is formed on a side of the first device 201 away from the substrate 200, the molding compound 204 encapsulating the first device 201, the protective dielectric layer 212, the bond post 202, and the wire 203. Specifically, the molding layer 204 and the conductive pillars 207 have a space therebetween.
Referring to fig. 23, an adhesive layer (not shown) is coated on the side of the molding layer 204 away from the substrate 200, and then the second device 206 is fixed on the adhesive layer, and the orthographic projection of the second device 206 on the substrate 200 covers the orthographic projection of the molding layer 204 on the substrate 200.
Further, the conductive post 207 and the pad 216 on the second device 206 are connected by using the conductive line 208, one end of the conductive line 208 is electrically connected to the pad 216 on the second device 206 to form a third bonding point f, and the other end of the conductive line 208 is electrically connected to the conductive post 207 to form a fourth bonding point g.
In this embodiment, the step of electrically connecting the conductive wire 208 and the conductive pillar 207 to form the fourth bonding point g may also include: forming a groove on the conductive post 207; filling the groove with a bonding agent; one end of a conductive wire 208 is bonded to the top surface of the conductive post 207 and the top surface of the bonding agent.
In other embodiments, after the conductive line forms the fourth bonding point on the conductive pillar, a dielectric layer is further formed on the top surface of the conductive pillar and around the fourth bonding point, and the dielectric layer and the sacrificial layer remaining in the previous step around the sidewall of the conductive pillar jointly form a protective supporting layer.
With combined reference to fig. 23 and 4, a sealant 209 is formed on a side of the second device 206 remote from the substrate 200, the sealant 209 encapsulating the second device 206, the conductive pillars 207, the protective support layer 217, and the conductive lines 208. Specifically, the sealing layer 209 is higher than the conductive line neck h of the conductive line 208 away from the top surface of the substrate 200 for preventing the conductive line 208 from being damaged when other process steps are performed subsequently. In addition, the sealing layer 209 may also be used to prevent the second device 206, the conductive pillars 207, and the protective support layer 217 from being damaged.
In the present embodiment, the second device 206 is constituted by a single chip. In other embodiments, the second device may be a package including a plurality of chips stacked, and the chips are sequentially stacked along a direction in which the substrate points to the first device. In the direction perpendicular to the substrate surface, the height of the conductive column can be adjusted according to different connection modes between different chips and the conductive column, so that the height difference between the third bonding point and the fourth bonding point is reduced, and the connection strength between the conductive line and the second device and the conductive column is improved.
In summary, in the semiconductor structure formed by the above method, the bonding post 202 is formed on the bonding pad 210, and the conductive post 207 is formed on the conductive pad 230, which is beneficial to reduce the bending degree of the wire 203 and the conductive line 208, thereby being beneficial to ensure good connection strength between the wire 203 and the bonding post 202 and the pad 211, and between the conductive line 208 and the conductive post 207 and the pad 216. In addition, the formation of the protective dielectric layer 212 on the sidewalls of the bonding pillars 202 and the formation of the protective supporting layer 217 on the sidewalls of the conductive pillars 207 are advantageous for preventing the bonding pillars 202 and the conductive pillars 207 from shifting relative to the substrate 200 when being affected by external forces and preventing the bonding pillars 202 and the conductive pillars 207 from toppling over.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims (15)

1. A semiconductor structure, comprising:
a substrate and a bonding pad on the substrate;
the bonding column is positioned on the surface of the bonding pad far away from the substrate and is in contact with the bonding pad;
a first device on the substrate and spaced apart from the bond post;
the welding pad is positioned on the surface of the first device far away from the substrate;
a lead connecting the pad and the bond post;
a protective dielectric layer extending along sidewalls of the bond post.
2. The semiconductor structure of claim 1, wherein a height difference between the top surface of the bond post and the top surface of the bond pad in a direction from the substrate toward the first device is no greater than a thickness of the bond pad.
3. The semiconductor structure of claim 2, wherein one end of the wire is electrically connected to the pad to form a first bond site, and the other end of the wire is electrically connected to the bond post to form a second bond site, the first bond site not being lower than the second bond site.
4. The semiconductor structure of claim 3, wherein the protective dielectric layer is disposed at the second bonding point.
5. The semiconductor structure of claim 3, wherein the lead includes a lead neck located at a bend of the lead extending upward along the first bond site, wherein a space is provided between the protective dielectric layer and the first device, and wherein the lead neck is located in the space.
6. The semiconductor structure of claim 5, further comprising: and the plastic packaging layer fills the interval and covers the neck of the lead.
7. The semiconductor structure of claim 1, wherein the protective dielectric layer further surrounds sidewalls of the bond pads in a direction from the substrate toward the first device.
8. The semiconductor structure of claim 1, further comprising:
the second device is positioned on one side, far away from the substrate, of the second control device;
a conductive pad on the substrate and exposing a surface of the conductive pad, the conductive pad being spaced apart from the bonding pad;
the bonding pad is positioned on the surface of the second device far away from the substrate;
a conductive pillar located on a surface of the conductive pad away from the substrate and in contact with the conductive pad, and a top surface of the conductive pillar is not lower than a top surface of the bonding pillar in a direction in which the substrate points to the first device;
a protective support layer extending along sidewalls of the conductive pillars;
a conductive line having one end electrically connected to the pad and the other end electrically connected to the conductive post.
9. The semiconductor structure of claim 8, wherein an orthographic projection of an area surrounded by the bond post, the protective dielectric layer, the wire, and the first device on the substrate is a first projection, an orthographic projection of the second device on the substrate is a second projection, the second projection covers the first projection, and a combined orthographic projection of the conductive post and the protective support layer on the substrate is a third projection, the third projection being outside the first projection;
the semiconductor structure further includes: a sealing layer covering the second device, the conductive pillars, the protective support layer, and the conductive lines.
10. The semiconductor structure of claim 8, wherein the second device comprises a plurality of stacked chips, and the plurality of chips are sequentially stacked along a direction of the substrate toward the first device.
11. The semiconductor structure of claim 10, wherein a height difference between the top surface of the conductive pillar and the top surface of the pad electrically connected to the same conductive line is no greater than a thickness of the pad in a direction in which the substrate points toward the first device.
12. The semiconductor structure of claim 1, wherein a side of the bond post remote from the substrate has a recess filled with a bonding agent; the lead is electrically connected with the bonding column to form a second bonding point, and the orthographic projection of the second bonding point on the substrate covers the orthographic projection of the groove on the substrate.
13. A method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein the substrate is provided with a bonding pad;
forming a bonding column on the surface of the bonding pad far away from the substrate;
forming a protective dielectric layer on the side wall of the bonding column;
forming a first device on the substrate, wherein the surface of the first device, which is far away from the substrate, is provided with a welding pad, and the first device and the bonding column are mutually spaced;
and connecting the bonding column and the welding pad by adopting a lead.
14. The method as claimed in claim 13, wherein the substrate has a conductive pad spaced apart from the bonding pad, and the substrate exposes a surface of the conductive pad; when the bonding posts and the protective dielectric layer are formed, conductive posts and a protective support layer which are mutually spaced with the bonding posts are also formed, and the specific forming steps comprise:
forming a sacrificial layer on the substrate, the sacrificial layer covering the bond pad and the conductive pad;
patterning the sacrificial layer to form a through hole exposing the bonding pad and the conductive pad;
forming the bonding pillar and the conductive pillar filling the via hole, the conductive pillar and the conductive pad being in contact;
removing part of the sacrificial layer, wherein the sacrificial layer surrounding the side wall of the joint column is the protective dielectric layer, and the sacrificial layer surrounding the side wall of the conductive column is the protective supporting layer;
after forming the first device, further comprising:
forming a molding compound layer on the side of the first device far away from the substrate, wherein the molding compound layer wraps the first device, the bonding column and the lead;
forming a second device on one side of the plastic packaging layer far away from the substrate;
connecting the conductive post and the second device with a conductive line.
15. The method of claim 13, wherein the step of connecting the bond post and the bond pad with the wire comprises:
forming a groove on one side of the bonding column away from the substrate;
filling a bonding agent in the groove;
one end of the lead is bonded to the pad and the other end of the lead is bonded to the top surface of the bond post and the top surface of the bonding agent.
CN202110444203.XA 2021-04-23 2021-04-23 Semiconductor structure and manufacturing method thereof Active CN113517255B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110444203.XA CN113517255B (en) 2021-04-23 2021-04-23 Semiconductor structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110444203.XA CN113517255B (en) 2021-04-23 2021-04-23 Semiconductor structure and manufacturing method thereof

Publications (2)

Publication Number Publication Date
CN113517255A true CN113517255A (en) 2021-10-19
CN113517255B CN113517255B (en) 2023-09-22

Family

ID=78061984

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110444203.XA Active CN113517255B (en) 2021-04-23 2021-04-23 Semiconductor structure and manufacturing method thereof

Country Status (1)

Country Link
CN (1) CN113517255B (en)

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142523A (en) * 1993-11-22 1995-06-02 Hitachi Ltd Equipment and method for manufacturing semiconductor
JPH0917929A (en) * 1995-06-29 1997-01-17 Nec Corp Bonding post and its selector
TW396472B (en) * 1997-07-07 2000-07-01 Motorola Inc Semiconductor package bond post configuration and method of manufacturing thereof
US20030042621A1 (en) * 2001-09-05 2003-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Wire stitch bond on an integrated circuit bond pad and method of making the same
US20030214035A1 (en) * 2002-05-17 2003-11-20 Samsung Electronics Co., Ltd. Bump formed on semiconductor device chip and method for manufacturing the bump
US20070026659A1 (en) * 2005-07-27 2007-02-01 International Business Machines Corporation Post last wiring level inductor using patterned plate process
JP2007035863A (en) * 2005-07-26 2007-02-08 Toshiba Corp Semiconductor device
CN104733434A (en) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 Bonding structure and forming method thereof
US20160307788A1 (en) * 2015-04-17 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Interconnect Structure and Methods Forming the Same
US20190371711A1 (en) * 2018-05-31 2019-12-05 Infineon Technologies Austria Ag Bond Pad and Clip Configuration for Packaged Semiconductor Device

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07142523A (en) * 1993-11-22 1995-06-02 Hitachi Ltd Equipment and method for manufacturing semiconductor
JPH0917929A (en) * 1995-06-29 1997-01-17 Nec Corp Bonding post and its selector
TW396472B (en) * 1997-07-07 2000-07-01 Motorola Inc Semiconductor package bond post configuration and method of manufacturing thereof
US20030042621A1 (en) * 2001-09-05 2003-03-06 Taiwan Semiconductor Manufacturing Co., Ltd. Wire stitch bond on an integrated circuit bond pad and method of making the same
US20030214035A1 (en) * 2002-05-17 2003-11-20 Samsung Electronics Co., Ltd. Bump formed on semiconductor device chip and method for manufacturing the bump
JP2007035863A (en) * 2005-07-26 2007-02-08 Toshiba Corp Semiconductor device
US20070026659A1 (en) * 2005-07-27 2007-02-01 International Business Machines Corporation Post last wiring level inductor using patterned plate process
CN104733434A (en) * 2013-12-18 2015-06-24 中芯国际集成电路制造(上海)有限公司 Bonding structure and forming method thereof
US20160307788A1 (en) * 2015-04-17 2016-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-Out Interconnect Structure and Methods Forming the Same
US20190371711A1 (en) * 2018-05-31 2019-12-05 Infineon Technologies Austria Ag Bond Pad and Clip Configuration for Packaged Semiconductor Device

Also Published As

Publication number Publication date
CN113517255B (en) 2023-09-22

Similar Documents

Publication Publication Date Title
JP5118942B2 (en) Through-silicon via stack package and manufacturing method thereof
TWI429050B (en) Stack die packages
TWI438883B (en) Semiconductor package having buried post in encapsulant and method of manufacturing the same
CN116705737A (en) Semiconductor package
JP4775007B2 (en) Semiconductor device and manufacturing method thereof
US20120074584A1 (en) Multi-layer tsv insulation and methods of fabricating the same
US20070023886A1 (en) Method for producing a chip arrangement, a chip arrangement and a multichip device
KR101801137B1 (en) Semiconductor Devices and Methods of Fabricating the Same
CN102280418A (en) Semiconductor package with heat dissipation devices
CN106601692B (en) Semiconductor package, method of manufacturing the same, and semiconductor module
CN112736031A (en) Interposer and method of manufacturing the same, semiconductor device and method of manufacturing the same
CN115206897A (en) Semiconductor package including molding layer
CN116072637A (en) Semiconductor package
KR101494417B1 (en) Semiconductor package and method of manufacturing the same
CN113161323B (en) Semiconductor structure and manufacturing method thereof
KR101727160B1 (en) Semiconductor devices
CN113161319B (en) Semiconductor structure and manufacturing method thereof
CN113517255B (en) Semiconductor structure and manufacturing method thereof
KR20230116281A (en) Capacitor wire and electronic devices including the same
CN210489610U (en) Fan-shaped multi-chip packaging structure
CN111312665B (en) Package structure and method for manufacturing the same
US10636760B2 (en) Semiconductor packages
CN101621046A (en) Semiconductor package using through-electrodes having voids
US8018075B2 (en) Semiconductor package, method for enhancing the bond of a bonding wire, and method for manufacturing a semiconductor package
CN214753746U (en) Stacked semiconductor device packaging structure

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant