CN113516952B - Pixel driving circuit, driving method thereof and display panel - Google Patents
Pixel driving circuit, driving method thereof and display panel Download PDFInfo
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- CN113516952B CN113516952B CN202110577324.1A CN202110577324A CN113516952B CN 113516952 B CN113516952 B CN 113516952B CN 202110577324 A CN202110577324 A CN 202110577324A CN 113516952 B CN113516952 B CN 113516952B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3258—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the voltage across the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
Abstract
The disclosure relates to the technical field of display, and provides a pixel driving circuit, a driving method thereof and a display panel. The pixel driving circuit includes: the driving circuit is connected with the first node and the second node and is used for outputting driving current to the second node according to the voltage of the first node; the first switch unit is connected between the first node and the third node and used for responding to a control signal to connect the first node and the third node; the second switch unit is connected between the third node and the initial signal end and used for responding to a control signal to connect the third node and the initial signal end; the third switching unit is connected between the third node and the reference voltage terminal, and is used for responding to a control signal to transmit a signal of the reference voltage to the third node. The pixel driving circuit can reduce the leakage current of the first node in the light-emitting stage.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display panel.
Background
The pixel driving circuit generally includes a driving transistor for supplying a driving current to the light emitting unit according to a gate voltage thereof, however, the gate of the driving transistor easily leaks electricity to other nodes in a light emitting stage of the pixel driving circuit, thereby causing display abnormality.
Particularly in a low gray scale display state, the display panel can reduce power consumption by reducing a refresh frequency, and the display abnormality caused by the above-mentioned leakage is more serious at the low refresh frequency.
It is noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure and therefore may include information that does not constitute prior art that is already known to a person of ordinary skill in the art.
BRIEF SUMMARY OF THE PRESENT DISCLOSURE
According to an aspect of the present disclosure, there is provided a pixel driving circuit, including: the driving circuit is connected with a first node and a second node and used for outputting driving current to the second node according to the voltage of the first node; the first switch unit is connected between the first node and the third node and used for responding to a control signal to connect the first node and the third node; the second switch unit is connected between the third node and the initial signal end and used for responding to a control signal to connect the third node and the initial signal end; the third switching unit is connected between the third node and a reference voltage terminal, and is used for responding to a control signal to transmit a signal of the reference voltage terminal to the third node.
In one exemplary embodiment of the present disclosure, the driving circuit includes: and the first pole of the driving transistor is connected with the fourth node, the second pole of the driving transistor is connected with the second node, and the grid of the driving transistor is connected with the first node. The first switching unit includes: and a first electrode of the first transistor is connected with the first node, and a second electrode of the first transistor is connected with the third node. The second switching unit includes: and a first pole of the second transistor is connected with the third node, and a second pole of the second transistor is connected with the initial signal end. The third switching unit includes: and the first pole of the third transistor is connected with the third node, and the second pole of the third transistor is connected with the reference voltage end.
In one exemplary embodiment of the present disclosure, the pixel driving circuit further includes: the compensation circuit is connected with the first node, the second node and the first grid driving signal end and is used for responding to a signal of the first grid driving signal end so as to be connected with the first node and the second node; the data writing circuit is connected with the fourth node, the first grid driving signal end and the data signal end and is used for responding to the signal of the first grid driving signal end and transmitting the signal of the data signal end to the fourth node; the control circuit is connected with the fourth node, the first power supply end, the enabling signal end, the second node and the fifth node, is used for responding to the signal of the enabling signal end to connect the first power supply end and the fourth node and is used for responding to the signal of the enabling signal end to connect the second node and the fifth node; the reset circuit is connected with the initial signal end, the reset signal end and the fifth node and is used for responding to the signal of the reset signal end and transmitting the signal of the initial signal end to the fifth node; the memory circuit is connected between the first node and the first power supply terminal.
In an exemplary embodiment of the present disclosure, the compensation circuit includes: and a first pole of the fourth transistor is connected with the first node, a second pole of the fourth transistor is connected with the second node, and a grid of the fourth transistor is connected with the first grid driving signal end. The data write circuit includes: a fifth transistor, a first pole of which is connected to the fourth node, a second pole of which is connected to the data signal terminal, and a gate of which is connected to the first gate driving signal terminal; the control circuit includes: a first electrode of the sixth transistor is connected with the first power supply end, a second electrode of the sixth transistor is connected with the fourth node, and a grid electrode of the sixth transistor is connected with the enable signal end; a first pole of the seventh transistor is connected with the second node, a second pole of the seventh transistor is connected with the fifth node, and a grid of the seventh transistor is connected with the enable signal end; the reset circuit includes: a first electrode of the eighth transistor is connected with the initial signal end, a second electrode of the eighth transistor is connected with the fifth node, and a grid electrode of the eighth transistor is connected with the reset signal end; the storage circuit includes a capacitor connected between the first node and the first power supply terminal. The driving transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type transistors.
In an exemplary embodiment of the present disclosure, the reference voltage terminal shares the first power terminal.
In an exemplary embodiment of the present disclosure, a gate of the third transistor is connected to the enable signal terminal; the first transistor and the second transistor are P-type transistors, the grid electrode of the first transistor is connected with the reset signal end, and the grid electrode of the second transistor is connected with the reset signal end. In one exemplary embodiment of the present disclosure, among the first transistor and the second transistor, there is at least one N-type transistor.
In an exemplary embodiment of the present disclosure, a gate of the third transistor is connected to the enable signal terminal; the first transistor is a P-type transistor, the second transistor is an N-type transistor, the grid electrode of the first transistor is connected with the reset signal end, and the grid electrode of the second transistor is connected with the enable signal end; or, the first transistor is an N-type transistor, the second transistor is a P-type transistor, a gate of the first transistor is connected to a second gate drive signal terminal, a gate of the second transistor is connected to the reset signal terminal, and a polarity of a signal at the second gate drive signal terminal is opposite to a polarity of a signal at the reset signal terminal; or, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the gate of the first transistor is connected to the reset signal terminal, the gate of the second transistor is connected to the second gate drive signal terminal, and the polarity of the signal on the second gate drive signal terminal is opposite to the polarity of the signal on the reset signal terminal; or, the first transistor and the second transistor are N-type transistors, a gate of the first transistor is connected to a second gate driving signal end, a gate of the second transistor is connected to the second gate driving signal end, and a polarity of a signal on the second gate driving signal end is opposite to a polarity of a signal on the reset signal end; or the first transistor and the second transistor are N-type transistors, the gate of the first transistor is connected to a second gate drive signal end, the gate of the second transistor is connected to the enable signal end, and the polarity of the signal on the second gate drive signal end is opposite to the polarity of the signal on the reset signal end.
According to an aspect of the present disclosure, there is provided a pixel driving circuit driving method for driving the pixel driving circuit, wherein the driving method includes:
inputting a constant voltage to the reference voltage terminal, wherein in a low gray scale state, a voltage difference between a first node and the reference voltage is smaller than a voltage difference between the first node and an initial signal terminal in an initial stage of a light emitting stage of the pixel driving circuit;
and in a light emitting stage, turning on the third switching unit to transmit a signal of the reference voltage terminal to the third node.
According to an aspect of the present disclosure, a display panel is provided, wherein the pixel driving circuit is included.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
FIG. 1 is a schematic circuit diagram of a pixel driving circuit in the related art;
FIG. 2 is a timing diagram of nodes in a driving method of the pixel driving circuit of FIG. 1;
FIG. 3 is a schematic diagram of an exemplary embodiment of a pixel driving circuit according to the present disclosure;
FIG. 4 is a timing diagram of nodes of the pixel driving circuit shown in FIG. 3;
FIG. 5 is a table comparing a voltage variation of a first node in the related art with a voltage variation of the first node in the present disclosure;
FIG. 6 is a graph illustrating a variation of a voltage at a first node according to the related art and a variation of a voltage at a first node according to the present disclosure;
fig. 7 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;
FIG. 8 is a schematic diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;
FIG. 9 is a timing diagram of the nodes of the pixel driving circuit shown in FIG. 8;
FIG. 10 is a schematic diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;
FIG. 11 is a schematic diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure;
fig. 12 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
The terms "a", "an", "the" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
Fig. 1 is a schematic circuit diagram of a pixel driving circuit in the related art. The pixel driving circuit may include: the circuit comprises a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a capacitor C. A first pole of the first transistor T1 is connected to the first node N1, a second pole is connected to the initialization signal terminal Vinit, and a gate is connected to the reset signal terminal Re; a first pole of the second transistor T2 is connected with a first pole of the driving transistor T3, and a second pole of the second transistor T2 is connected with the first node N1; the grid is connected with a grid driving signal end Gate; the gate of the driving transistor T3 is connected to the first node N1; a first pole of the fourth transistor T4 is connected to the Data signal terminal Data, a second pole is connected to a second pole of the driving transistor T3, and a Gate is connected to the Gate driving signal terminal Gate; a first electrode of the fifth transistor T5 is connected to the first power terminal VDD, a second electrode thereof is connected to the second electrode of the driving transistor T3, and a gate thereof is connected to the enable signal terminal EM; a first pole of the sixth transistor T6 is connected with the first pole of the driving transistor T3, and a gate electrode thereof is connected with the enable signal terminal EM; a first pole of the seventh transistor T7 is connected to the initialization signal terminal Vinit, and a second pole is connected to a second pole of the sixth transistor T6. The pixel driving circuit may be connected to a light emitting unit OLED for driving the light emitting unit OLED to emit light, and the light emitting unit OLED may be connected between the second electrode of the sixth transistor T6 and the second power source terminal VSS. The transistors T1 to T7 may be all P-type transistors.
Fig. 2 is a timing diagram of nodes in a driving method of the pixel driving circuit of fig. 1. Wherein, gate represents the time sequence of Gate driving signal terminal Gate, re represents the time sequence of reset signal terminal Re, EM represents the time sequence of enabling signal terminal EM, and Data represents the time sequence of Data signal terminal Data. The driving method of the pixel driving circuit can comprise a reset phase t1, a compensation phase t2 and a light-emitting phase t3. In the reset phase t1: the reset signal terminal Re outputs a low level signal, the first transistor T1 and the seventh transistor T7 are turned on, and the initialization signal terminal Vinit inputs an initialization signal to the first node N1 and the second pole of the sixth transistor T6. In the compensation phase t2: the Gate driving signal terminal Gate outputs a low level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the Data signal terminal Data outputs a driving signal to write a voltage Vdata + Vth to the first node N1, where Vdata is a voltage of the driving signal and Vth is a threshold voltage of the driving transistor T3. Light-emitting stage t3: the enable signal end EM outputs a low level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 emits light under the action of the voltage Vdata + Vth stored in the capacitor C. According to the output power of the driving transistorFlow equation I = (μ WCox/2L) (Vgs-Vth) 2 Wherein μ is the carrier mobility; cox is the gate capacitance per unit area, W is the width of the drive transistor channel, L is the length of the drive transistor channel, vgs is the difference in gate-source voltages of the drive transistors, and Vth is the threshold voltage of the drive transistors. However, in the light emitting stage, the first node N1 is liable to leak to the initial signal terminal Vinit through the first transistor T1, thereby causing a display abnormality. Especially in the low gray scale display state, the display panel can reduce power consumption by reducing the refresh frequency, and the display abnormality caused by the above-mentioned leakage is more serious in the low refresh frequency.
Based on this, the present exemplary embodiment provides a pixel driving circuit, as shown in fig. 3, which is a schematic structural diagram of an exemplary embodiment of the pixel driving circuit of the present disclosure. Wherein the pixel driving circuit may include: the driving circuit 4 may be connected to the first node N1 and the second node N2, and is configured to output a driving current to the second node N2 according to a voltage of the first node N1; the first switching unit 1 may be connected between the first node N1 and a third node N3, for responding to a control signal to connect the first node N1 and the third node N3; the second switching unit 2 may be connected between the third node N3 and an initial signal terminal Vinit, for responding to a control signal to connect the third node N3 and the initial signal terminal Vinit; the third switching unit 3 may be connected between the third node N3 and the reference voltage terminal Vref, and configured to respond to a control signal to transmit a signal of the reference voltage terminal Vref to the third node N3.
In the present exemplary embodiment, the reference voltage terminal Vref may provide a constant voltage to the third node N3 during the light emitting period. In a low gray scale display state, in an initial stage of a light emitting stage of the pixel driving circuit, a voltage difference between a voltage of the first node N1 and the constant voltage may be smaller than a voltage difference between the first node N1 and an initial signal terminal Vinit, so that a leakage current from the first node N1 to the initial signal terminal in the light emitting stage may be reduced, where the constant voltage may be smaller than the voltage of the first node N1 or larger than the voltage of the first node N1. The pixel driving circuit can be used for solving the problem of electric leakage of the first node in a low gray scale state. For example, the voltage of the initial signal terminal Vinit may be-2V, and in the low gray level display state, the voltage range of the first node N1 in the initial stage of the light emitting period may be 1.5V-4.5V, and the constant voltage may be 0V, 1.5V, 4.5V, 5V, and so on. In the present exemplary embodiment, the above-described constant voltage may be preferably within the above-described voltage range of the first node N1.
It should be noted that the "low gray level" in the exemplary embodiment may refer to a gray level range from 0 to 16 in the gray level division manner with the maximum gray level of 255, for example, 0 gray level, 5 gray level, 10 gray level, and 16 gray level. In the exemplary embodiment, the constant voltage provided by the reference voltage terminal does not vary with the gray scale variation.
It should be understood that, in other exemplary embodiments, the leakage current of the first node may also be adjusted by adjusting the voltage value of the reference voltage terminal Vref for different gray scale ranges. For example, the gray scale is in the range of 17-32, the voltage range of the first node N1 in the initial stage of the light emitting stage may be 0.5V-1.5V, and the voltage of the reference voltage terminal may be 0.5V, 1V, 1.5V, etc. In addition, the reference voltage terminal may provide different voltages according to different gray scales, and the voltage of the reference voltage terminal may be equal to or approximately equal to the voltage of the first node at the initial stage of the light emitting stage under the corresponding gray scale, for example, under 0 gray scale, the voltage of the first node at the initial stage of the light emitting stage is 4.5V, and the reference voltage terminal may provide 4.5V; under 16 gray scale, the voltage of the first node at the initial stage of the light emitting stage is 1.5V, and the reference voltage terminal can provide 1.5V.
In the present exemplary embodiment, as shown in fig. 3, the driving circuit 4 may include: and a driving transistor DT having a first electrode connected to the fourth node N4, a second electrode connected to the second node N2, and a gate electrode connected to the first node N1. The first switching unit 1 may include: and a first transistor T1, wherein a first pole of the first transistor T1 is connected to the first node N1, a second pole of the first transistor T1 is connected to the third node N3, and a gate of the first transistor T1 may be connected to a reset signal terminal Re. The second switching unit 2 may include: and a second transistor T2, a first pole of the second transistor T2 being connected to the third node N3, a second pole being connected to the initial signal terminal Vinit, and a gate being connectable to a reset signal terminal Re. The third switching unit 3 may include: and a third transistor T3, wherein a first pole of the third transistor T3 is connected to the third node N3, a second pole of the third transistor T3 is connected to the reference voltage terminal Vref, and a gate of the third transistor T3 may be connected to the enable signal terminal EM. The first transistor T1, the second transistor T2, and the third transistor T3 may be P-type transistors.
In the present exemplary embodiment, as shown in fig. 3, the pixel driving circuit may further include: the compensation circuit 5 is connected with the first node N1, the second node N2 and the first Gate driving signal terminal Gate1, and is used for responding to a signal of the first Gate driving signal terminal Gate1 so as to connect the first node N1 and the second node N2; the data writing circuit 6 is connected to the fourth node N4, the first Gate driving signal terminal Gate1 and the data signal terminal Da, and configured to transmit a signal of the data signal terminal Da to the fourth node N4 in response to a signal of the first Gate driving signal terminal Gate1; the control circuit 7 is connected to the fourth node N4, the first power terminal VDD, the enable signal terminal EM, the second node N2, the fifth node N5, and is configured to respond to the signal of the enable signal terminal EM to connect the first power terminal VDD and the fourth node N4, and to respond to the signal of the enable signal terminal EM to connect the second node N2 and the fifth node N5; the reset circuit 8 is connected to the initial signal terminal Vinit, the reset signal terminal Re, and the fifth node N5, and configured to respond to a signal of the reset signal terminal Re and transmit a signal of the initial signal terminal Vinit to the fifth node N5; the memory circuit 9 is connected between the first node N1 and the first power source terminal VDD, and stores the charge of the first node N1.
In the present exemplary embodiment, as shown in fig. 3, the compensation circuit 5 may include: and a fourth transistor T4, a first pole of the fourth transistor T4 is connected to the first node N1, a second pole of the fourth transistor T4 is connected to the second node N2, and a Gate of the fourth transistor T4 is connected to the first Gate driving signal terminal Gate1. The data writing circuit 6 may include: a fifth transistor T5, wherein a first pole of the fifth transistor T5 is connected to the fourth node N4, a second pole of the fifth transistor T5 is connected to the data signal terminal Da, and a Gate of the fifth transistor T5 is connected to the first Gate driving signal terminal Gate1; the control circuit 7 may include: a sixth transistor T6 and a seventh transistor T7, wherein a first electrode of the sixth transistor T6 is connected to the first power terminal VDD, a second electrode thereof is connected to the fourth node N4, and a gate thereof is connected to the enable signal terminal EM; a first pole of the seventh transistor T7 is connected to the second node N2, a second pole thereof is connected to the fifth node N5, and a gate thereof is connected to the enable signal terminal EM; the reset circuit 8 may include: an eighth transistor T8, a first pole of the eighth transistor T8 is connected to the initial signal terminal Vinit, a second pole of the eighth transistor T8 is connected to the fifth node N5, and a gate of the eighth transistor T8 is connected to the reset signal terminal Re; the memory circuit 9 comprises a capacitor C connected between said first node N1 and said first supply terminal VDD. The driving transistor DT, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, such as P-type polysilicon transistors. The fifth node N5 may be configured to be connected to an anode of a light emitting unit OLED, and a cathode of the light emitting unit OLED may be connected to a second power source terminal VSS, wherein the voltage of the first power source terminal VDD may be a high-level voltage, and the voltage of the second power source terminal VSS may be a low-level voltage.
As shown in fig. 4, a timing diagram of each node of the pixel driving circuit in fig. 3 is shown, wherein Gate1 represents a timing of the first Gate driving signal terminal Gate1, re represents a timing of the reset signal terminal Re, and EM represents a timing of the enable signal terminal EM. The pixel driving circuit driving method also comprises three stages: a reset phase t1, a compensation phase t2 and a light-emitting phase t3. In the reset phase t1: the reset signal terminal Re outputs a low level signal, the first transistor T1, the second transistor T2, and the eighth transistor T8 are turned on, and the initial signal terminal Vinit inputs an initialization signal to the first node N1 and the fifth node N5. In the compensation phase t2: the first Gate driving signal terminal Gate1 outputs a low level signal, the fourth transistor T4 and the fifth transistor T5 are turned on, and the Data signal terminal Data outputs a driving signal to write a voltage Vdata + Vth to the first node N1, where Vdata is a voltage of the driving signal and Vth is a threshold voltage of the driving transistor DT. In the light emission phase t3: the enable signal terminal EM outputs a low level signal, the sixth transistor T6, the seventh transistor T7, and the third transistor T3 are turned on, the reference voltage terminal Vref inputs a constant voltage to the third node N3 to reduce a leakage current of the first node N1 to the initial signal terminal Vinit, and the driving transistor DT inputs a driving current to the fifth node N5 according to the voltage of the first node N1.
As shown in fig. 5, which is a table chart comparing the voltage variation of the first node N1 in the related art with the voltage variation of the first node N1 in the present disclosure, the data described in fig. 5 are obtained when the refresh frequency of the display panel is 1 Hz. Fig. 5 shows: in fig. 1, when the 7T1C pixel driving circuit is under different gray scales (different gray scales correspond to different data signals Vdata), the voltage variation of the first node N1 at the initial stage and the final stage of the light emitting stage; and the voltage variation of the first node N1 at the initial stage and the end stage of the light-emitting stage in the 9T1C pixel driving circuit in fig. 3 at different gray scales. As shown in fig. 6, which is a graph of the voltage variation of the first node N1 in the related art and the voltage variation of the first node N1 in the present disclosure, the curve data in fig. 6 is taken from the table data in fig. 5. Where the curve 11 is an absolute value of the voltage change rate of the first node at different gray levels in the related art, and the curve 12 is an absolute value of the voltage change rate of the first node at different gray levels in the present disclosure. Obviously, the first node N1 in the present disclosure has a smaller voltage change rate, that is, the first node N1 in the present disclosure has a smaller leakage current in the light emitting phase.
It should be understood that, in other exemplary embodiments, the reference voltage terminal Vref may share the first power terminal VDD to reduce the number of signal terminals. The gate of the first transistor T1 may be further connected to another signal terminal, and the gate of the second transistor T2 may be further connected to another signal terminal. At least one N-type transistor, for example, an N-type oxide transistor, may also be present in the first transistor T1 and the second transistor T2, and the N-type oxide transistor may have a smaller leakage current, so that the leakage current of the first node N1 to the initial signal terminal Vinit may be further reduced.
Fig. 7 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure. The second transistor T2 may be an N-type transistor, and a gate of the second transistor may be connected to the enable signal terminal EM. The first transistor T1 may be a P-type transistor, and a gate of the first transistor T1 may be connected to a reset signal terminal. The second pole of the third transistor T3 may be connected to the first power terminal VDD. The pixel driving circuit driving method may also include three stages: a reset phase t1, a compensation phase t2 and a light-emitting phase t3. And the timing of each node in the pixel driving circuit may be the same as the timing diagram shown in fig. 4.
Fig. 8 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure. The first transistor T1 may be an N-type transistor, and the Gate of the first transistor T1 may be connected to a second Gate driving signal terminal Gate2, wherein a polarity of a signal on the second Gate driving signal terminal Gate2 may be opposite to a polarity of a signal on the reset signal terminal Re. The second transistor T2 may be a P-type transistor, and a gate of the second transistor T2 may be connected to the reset signal terminal Re. Fig. 9 is a timing diagram of each node of the pixel driving circuit shown in fig. 8. Wherein, gate1 represents a timing of the first Gate driving signal terminal Gate1, gate2 represents a timing of the second Gate driving signal terminal, re represents a timing of the reset signal terminal Re, and EM represents a timing of the enable signal terminal EM. The pixel driving circuit driving method may also include three stages: a reset phase t1, a compensation phase t2 and a light-emitting phase t3.
Fig. 10 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure. The second transistor T2 may be an N-type transistor, and a Gate of the second transistor T2 may be connected to a second Gate driving signal terminal Gate2, wherein a polarity of a signal on the second Gate driving signal terminal Gate2 may be opposite to a polarity of a signal on the reset signal terminal Re. The first transistor T1 may be a P-type transistor, and the gate of the first transistor T1 may be connected to the reset signal terminal Re. The pixel driving circuit driving method may also include three stages: a reset phase t1, a compensation phase t2 and a light-emitting phase t3. And the timing of each node in the pixel driving circuit may be the same as the timing diagram shown in fig. 9.
Fig. 11 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit according to the present disclosure. The first transistor T1 and the second transistor T2 may be N-type transistors, and the Gate of the first transistor and the Gate of the second transistor may be connected to a second Gate driving signal terminal Gate2, wherein a polarity of a signal on the second Gate driving signal terminal Gate2 may be opposite to a polarity of a signal on the reset signal terminal Re. The pixel driving circuit driving method may also include three stages: a reset phase t1, a compensation phase t2 and a light-emitting phase t3. And the timing of each node in the pixel driving circuit may be the same as the timing diagram shown in fig. 9.
Fig. 12 is a schematic structural diagram of another exemplary embodiment of the pixel driving circuit according to the present disclosure. The first transistor T1 and the second transistor T2 may be N-type transistors, and the Gate of the first transistor may be connected to the second Gate driving signal terminal Gate2, wherein a polarity of a signal on the second Gate driving signal terminal Gate2 may be opposite to a polarity of a signal on the reset signal terminal Re. The gate of the second transistor may be connected to the enable signal terminal EM. The pixel driving circuit driving method may also include three stages: a reset phase t1, a compensation phase t2 and a light-emitting phase t3. And the timing of each node in the pixel driving circuit may be the same as the timing diagram shown in fig. 9.
The present exemplary embodiment further provides a pixel driving circuit driving method for driving the above-mentioned pixel driving circuit, wherein the driving method includes:
inputting a constant voltage to the reference voltage terminal, wherein in a low gray scale state, a voltage difference between a first node and the reference voltage is smaller than a voltage difference between the first node and an initial signal terminal in an initial stage of a light emitting stage of the pixel driving circuit;
and in a light emitting stage, turning on the third switching unit to transmit a signal of the reference voltage terminal to the third node.
The driving method of the pixel driving circuit has been described in detail in the above, and is not described herein again.
The present exemplary embodiment also provides a display panel, which includes the pixel driving circuit described above. The display panel can be applied to display devices such as mobile phones, tablet computers and televisions.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the following claims.
Claims (10)
1. A pixel driving circuit, comprising:
the driving circuit is connected with the first node and the second node and used for outputting driving current to the second node according to the voltage of the first node;
a first switching unit connected between the first node and a third node, for connecting the first node and the third node in response to a control signal;
a second switching unit connected between the third node and an initial signal terminal, for connecting the third node and the initial signal terminal in response to a control signal;
and a third switching unit connected between the third node and a reference voltage terminal for transmitting a signal of the reference voltage terminal to the third node in response to a control signal.
2. The pixel driving circuit according to claim 1, wherein the driving circuit comprises:
the first pole of the driving transistor is connected with a fourth node, the second pole of the driving transistor is connected with the second node, and the grid of the driving transistor is connected with the first node;
the first switching unit includes:
a first transistor having a first electrode connected to the first node and a second electrode connected to the third node;
the second switching unit includes:
a second transistor, a first pole of which is connected with the third node and a second pole of which is connected with the initial signal end;
the third switching unit includes:
and a third transistor, wherein a first pole of the third transistor is connected with the third node, and a second pole of the third transistor is connected with the reference voltage end.
3. The pixel driving circuit according to claim 2, wherein the pixel driving circuit further comprises:
the compensation circuit is connected with the first node, the second node and the first grid driving signal end and used for responding to the signal of the first grid driving signal end so as to connect the first node and the second node;
the data writing circuit is connected with the fourth node, the first grid driving signal end and the data signal end and is used for responding to the signal of the first grid driving signal end and transmitting the signal of the data signal end to the fourth node;
a control circuit, connected to the fourth node, the first power terminal, the enable signal terminal, the second node, and the fifth node, for connecting the first power terminal and the fourth node in response to the signal of the enable signal terminal, and for connecting the second node and the fifth node in response to the signal of the enable signal terminal;
the reset circuit is connected with the initial signal end, the reset signal end and the fifth node and is used for responding to the signal of the reset signal end and transmitting the signal of the initial signal end to the fifth node;
and a memory circuit connected between the first node and the first power supply terminal.
4. A pixel driving circuit according to claim 3, wherein the compensation circuit comprises:
a fourth transistor, a first electrode of which is connected with the first node, a second electrode of which is connected with the second node, and a grid of which is connected with the first grid driving signal end;
the data write circuit includes:
a fifth transistor, having a first electrode connected to the fourth node, a second electrode connected to the data signal terminal, and a gate connected to the first gate driving signal terminal;
the control circuit includes:
a sixth transistor, having a first electrode connected to the first power terminal, a second electrode connected to the fourth node, and a gate connected to the enable signal terminal;
a seventh transistor, having a first electrode connected to the second node, a second electrode connected to the fifth node, and a gate connected to the enable signal terminal;
the reset circuit includes:
a first electrode of the eighth transistor is connected with the initial signal end, a second electrode of the eighth transistor is connected with the fifth node, and a grid electrode of the eighth transistor is connected with the reset signal end;
a storage capacitor, comprising:
a capacitor connected between the first node and the first power supply terminal;
the driving transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are P-type transistors.
5. A pixel driving circuit according to claim 3, wherein the reference voltage terminal shares the first power supply terminal.
6. The pixel driving circuit according to claim 3, wherein a gate of the third transistor is connected to the enable signal terminal;
the first transistor and the second transistor are P-type transistors, the grid electrode of the first transistor is connected with the reset signal end, and the grid electrode of the second transistor is connected with the reset signal end.
7. A pixel driving circuit according to claim 3, wherein at least one N-type transistor is present among the first transistor and the second transistor.
8. The pixel driving circuit according to claim 7, wherein a gate of the third transistor is connected to the enable signal terminal;
the first transistor is a P-type transistor, the second transistor is an N-type transistor, the grid electrode of the first transistor is connected with the reset signal end, and the grid electrode of the second transistor is connected with the enable signal end;
or, the first transistor is an N-type transistor, the second transistor is a P-type transistor, a gate of the first transistor is connected to a second gate drive signal terminal, a gate of the second transistor is connected to the reset signal terminal, and a polarity of a signal at the second gate drive signal terminal is opposite to a polarity of a signal at the reset signal terminal;
or, the first transistor is a P-type transistor, the second transistor is an N-type transistor, the gate of the first transistor is connected to the reset signal terminal, the gate of the second transistor is connected to the second gate drive signal terminal, and the polarity of the signal on the second gate drive signal terminal is opposite to the polarity of the signal on the reset signal terminal;
or, the first transistor and the second transistor are N-type transistors, a gate of the first transistor is connected to a second gate driving signal end, a gate of the second transistor is connected to the second gate driving signal end, and a polarity of a signal on the second gate driving signal end is opposite to a polarity of a signal on the reset signal end;
or, the first transistor and the second transistor are N-type transistors, the gate of the first transistor is connected to the second gate driving signal end, the gate of the second transistor is connected to the enable signal end, and the polarity of the signal on the second gate driving signal end is opposite to the polarity of the signal on the reset signal end.
9. A pixel drive circuit driving method for driving the pixel drive circuit according to any one of claims 1 to 8, wherein the driving method comprises:
inputting a constant voltage to the reference voltage terminal, wherein in a low gray scale state, a voltage difference between a first node and the reference voltage is smaller than a voltage difference between the first node and an initial signal terminal in an initial stage of a light emitting stage of the pixel driving circuit;
and in a light-emitting period, turning on the third switching unit to transmit a signal of the reference voltage terminal to the third node.
10. A display panel comprising the pixel driving circuit according to any one of claims 1 to 8.
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