CN109859686B - Pixel driving circuit, driving method thereof and display panel - Google Patents

Pixel driving circuit, driving method thereof and display panel Download PDF

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Publication number
CN109859686B
CN109859686B CN201910247440.XA CN201910247440A CN109859686B CN 109859686 B CN109859686 B CN 109859686B CN 201910247440 A CN201910247440 A CN 201910247440A CN 109859686 B CN109859686 B CN 109859686B
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transistor
electrically connected
node
level
electrode
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CN109859686A (en
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刘利宾
杨倩
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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Priority to PCT/CN2020/075797 priority patent/WO2020199774A1/en
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]

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  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Electroluminescent Light Sources (AREA)

Abstract

The disclosure provides a pixel driving circuit, a driving method thereof and a display panel. The pixel driving circuit includes: a light emitting element; a driving sub-circuit electrically connected to the first node, the second node, and the third node; a first light emission control sub-circuit electrically connected to a light emission control signal line, a first voltage signal line, and the first node, and a second light emission control sub-circuit electrically connected to the light emission control signal line, the third node, and a first end of a light emitting element; a driving control sub-circuit electrically connected to a gate driving signal line, a data signal line, and the first node; a reset sub-circuit electrically connected to a reset signal line, the second node, and a first end of the light emitting element.

Description

Pixel driving circuit, driving method thereof and display panel
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a pixel driving circuit, a driving method thereof, and a display panel.
Background
In the display field, a Low Temperature Polysilicon (LTPS) process and an Oxide (Oxide) process (e.g., IGZO process) are two processes commonly used to manufacture a Thin Film Transistor (TFT) array substrate. The Low Temperature Polycrystalline Oxide (LTPO) process combines LTPS and Oxide processes in order to achieve more excellent display performance.
Disclosure of Invention
The disclosure provides a pixel driving circuit, a driving method thereof and a display panel.
According to one aspect of the present disclosure, a pixel driving circuit is provided. The pixel driving circuit includes: a light emitting element; a driving sub-circuit electrically connected to the first node, the second node, and the third node, configured to turn on a path between the first node and the third node under control of a voltage of the second node, and to generate a current for causing the light emitting element to emit light in the path; a first light emission control sub-circuit electrically connected to a light emission control signal line, a first voltage signal line, and the first node, and a second light emission control sub-circuit electrically connected to the light emission control signal line, the third node, and a first end of a light emitting element, the first and second light emission control sub-circuits being configured to transmit the current for causing the light emitting element to emit light to the first end of the light emitting element under control of a light emission control signal from the light emission control signal line; a driving control sub-circuit electrically connected to a gate driving signal line, a data signal line, and the first node, configured to supply a data signal from the data signal line to the first node under control of a gate driving signal from the gate driving signal line; a reset sub-circuit electrically connected to a reset signal line, the second node, and the first terminal of the light emitting element, configured to reset the second node and the first terminal of the light emitting element using the reset signal under control of a reset signal from the reset signal line.
In some embodiments, the drive sub-circuit comprises a drive transistor, a first transistor and a storage capacitor. A control electrode of the drive transistor is electrically connected to the second node, a first electrode is electrically connected to the first node, and a second electrode is electrically connected to the third node; a control electrode of the first transistor is electrically connected to the gate driving signal line, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to the second node; and a first end of the storage capacitor is electrically connected to the first voltage signal line, and a second end is electrically connected to the second node. The first transistor and the driving transistor are different types of transistors.
In some embodiments, the first light emission control sub-circuit includes a second transistor, and the second light emission control sub-circuit includes a third transistor. A control electrode of the second transistor is electrically connected to the light emission control signal line, a first electrode is electrically connected to the first voltage signal line, and a second electrode is electrically connected to the first node; a control electrode of the third transistor is electrically connected to the light emission control signal line, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to a first end of the light emitting element. The second transistor and the third transistor are the same type of transistor as the driving transistor.
In some embodiments, the drive control sub-circuit comprises a fourth transistor. A control electrode of the fourth transistor is electrically connected to the gate driving signal line, a first electrode is electrically connected to the data signal line, and a second electrode is electrically connected to the second node. The fourth transistor is a different type of transistor from the driving transistor.
In some embodiments, the reset sub-circuit includes a fifth transistor and a sixth transistor. A control electrode and a first electrode of the fifth transistor are electrically connected to the reset signal line in common, and a second electrode is electrically connected to the second node. A control electrode and a first electrode of the sixth transistor are electrically connected in common to the reset signal line, and a second electrode is electrically connected to a first terminal of the light emitting element. The fifth transistor and the sixth transistor are the same type of transistor as the driving transistor.
According to another aspect of the present disclosure, a display panel is provided. The display panel includes: a plurality of scan lines; a plurality of data lines crossing the plurality of scan lines; and a plurality of pixel units arranged in a matrix at intersections of each data line and each scan line and electrically connected to the corresponding data line and scan line, each pixel unit including the pixel driving circuit according to any of the embodiments described above. The data signal lines electrically connected with the pixel driving circuit are served by corresponding data lines of the pixel units, and the gate driving signal lines electrically connected with the pixel driving circuit are served by corresponding scanning lines of the pixel units.
In some embodiments, the display panel further includes a plurality of light emission control lines. The plurality of light emission control lines are arranged in parallel with the plurality of scanning lines or the plurality of data lines and are electrically connected to the same pixel cells as the plurality of scanning lines or the plurality of data lines, respectively. The light emission control signal lines to which the pixel driving circuits are electrically connected are served by the corresponding light emission control lines of the pixel units.
In some embodiments, the display panel further includes a plurality of inverters electrically connected to the plurality of scan lines in a one-to-one correspondence, respectively. The input end of the phase inverter is electrically connected with the corresponding scanning line, the output end of the phase inverter is electrically connected with the reset line of the pixel unit driven by the corresponding scanning line, and the reset signal line electrically connected with the pixel driving circuit in the pixel unit is served by the reset line. The inverter is also electrically connected to a reset level terminal and a reference level terminal, and is configured to supply a reset level from the reset level terminal or a reference level from the reference level terminal to the reset line under control of a gate driving signal from the scan line.
In some embodiments, the inverter includes a first inverting transistor and a second inverting transistor. A control electrode of the first inverter transistor is electrically connected to the scan line, a first electrode is electrically connected to the reset level terminal, a second electrode is electrically connected to the reset line, a control electrode of the second inverter transistor is electrically connected to the scan line, a second electrode is electrically connected to the reference level terminal, and a second electrode is electrically connected to the reset line. The first inverting transistor and the second inverting transistor are different types of transistors.
In some embodiments, the reset level is a level corresponding to an active level of a drive transistor, and the reference level is equal to a sum of an inactive level of the drive transistor and a threshold voltage of the drive transistor.
According to a further aspect of the present disclosure, there is provided a method of driving a pixel driving circuit according to any of the above embodiments. The method comprises the following steps: providing a light emission control signal having a first level, providing a gate driving signal and a reset signal having a second level, and providing a data signal having the second level during a first period; providing a light emission control signal and a gate driving signal having a first level, providing a reset signal having a reference level, and providing a data signal having the first level in a second period; in the third period, a reset signal having a reference level is supplied, a light emission control signal having a second level, a gate driving signal, and a data signal having the second level are supplied. The first level is a level corresponding to an inactive level of the driving transistor, and the second level is a level corresponding to an active level of the driving transistor.
In some embodiments, the reference level is equal to a sum of the first level and a threshold voltage of the drive transistor.
Drawings
In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings used in the description of the embodiments will be briefly introduced below. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived by those skilled in the art without the benefit of inventive faculty, wherein:
fig. 1 shows a schematic block diagram of a pixel driving circuit according to an embodiment of the present disclosure.
Fig. 2 illustrates a more detailed structure of the pixel driving circuit of fig. 1 according to one embodiment of the present disclosure.
Fig. 3A shows a signal timing diagram of the pixel driving circuit of fig. 2.
Fig. 3B-3D show schematic diagrams of the stages of the pixel driving circuit of fig. 2.
Fig. 4 shows a schematic block diagram of a display panel according to an embodiment of the present disclosure.
Fig. 5 illustrates a schematic structural diagram of an inverter of a display panel according to an embodiment of the present disclosure.
Fig. 6 shows a more detailed circuit diagram of the inverter of fig. 5.
Fig. 7 shows a flow chart of a driving method of a pixel driving circuit according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure. It should be noted that throughout the drawings, like elements are represented by like or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as limiting the disclosure in any way, but merely as exemplifications of embodiments of the disclosure. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure. It should be noted that the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in the embodiments of the present disclosure should be given their ordinary meanings as understood by those skilled in the art. The use of "first," "second," and similar terms in the embodiments of the disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another.
Furthermore, in the description of the embodiments of the present disclosure, the term "electrically connected" may mean that two components are directly electrically connected, and may also mean that two components are electrically connected via one or more other components. Further, the two components may be electrically connected or coupled by wire or wirelessly.
The transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors or other devices with the same characteristics. The transistors used in the embodiments of the present disclosure are mainly switching transistors according to the role in the circuit. Since the source and drain of the thin film transistor used herein are symmetrical, the source and drain can be interchanged. In the embodiments of the present disclosure, a gate of the transistor is referred to as a control electrode, one of a source and a drain is referred to as a first electrode, and the other of the source and the drain is referred to as a second electrode.
In the following examples, a pixel driving circuit implemented using LTPO technology is described, wherein part of the transistors are implemented by LTPS process, which is implemented by oxide (e.g. IGZO) process with the transistors. Hereinafter, transistors such as a driving transistor are illustrated as P-type thin film transistors implemented by the LTPS process, and some other transistors are illustrated as N-type transistors implemented by the IGZO process. It should be understood that this is by way of example only, and in other embodiments, the transistors of the present disclosure may be implemented by other processes and may be of different transistor types.
Further, in the description of the embodiments of the present disclosure, the terms "first level" and "second level" are used only to distinguish that the amplitudes of the two levels are different. In some embodiments, the "first level" may be an inactive level that turns off the associated transistor, and the "second level" may be an active level that turns on the associated transistor. Hereinafter, since the driving transistor is exemplified as a P-type thin film transistor, the "first level" is exemplified as the high level VH and the "second level" is exemplified as the low level VL.
The present disclosure is described in detail below with reference to the attached drawings.
Fig. 1 shows a schematic block diagram of a pixel driving circuit 100 according to an embodiment of the present disclosure.
As shown in fig. 1, the pixel driving circuit 100 may include a light emitting element 110, a driving sub-circuit 120, a first light emission control sub-circuit 130, a second light emission control sub-circuit 140, a driving control sub-circuit 150, and a reset sub-circuit 160.
The light emitting element 110 may be any light emitting element driven by current, such as an OLED light emitting unit. The light emitting element 110 has a first terminal connected to the second light emission control sub-circuit 140 and a second terminal connected to the fixed voltage terminal ELVSS. In some embodiments, the first terminal is an anode of the light emitting element 110 and the second terminal is a cathode of the light emitting element 110.
The driving sub-circuit 120 is electrically connected to the first node N1, the second node N2, and the third node N3, and is configured to turn on a path between the first node N1 and the third node N3 under the control of the voltage of the second node N2 and generate a current for lighting the light emitting element 110 in the path.
The first light emission control sub-circuit 130 is electrically connected to the light emission control signal line EM, the first voltage signal line V1, and the first node N1. The second light emission control sub-circuit 140 is electrically connected to the light emission control signal line EM, the third node N3, and the first terminal of the light emitting element 110. The first and second emission control sub-circuits 130 and 140 are configured to transmit a current for causing the light emitting element 110 to emit light to the first end of the light emitting element 110 under the control of an emission control signal from the emission control signal line EM.
Specifically, the first light emission control sub-circuit 130 receives the first voltage from the first voltage signal line V1 under the control of the light emission control signal and transfers the first voltage to the driving sub-circuit 120. In some embodiments, the first voltage may be the power supply voltage ELVDD. In some embodiments, ELVDD is higher than the first level (i.e., high level VH). The second light emission control sub-circuit 140 supplies the current generated by the driving sub-circuit 120 for causing the light emitting element 110 to emit light to the first terminal of the light emitting element 110 under the control of the light emission control signal.
The driving control sub-circuit 150 is electrically connected to the GATE driving signal line GATE, the DATA signal line DATA, and the first node N1. The drive control sub-circuit 150 is configured to supply the DATA signal from the DATA signal line DATA to the first node N1 under the control of the GATE drive signal from the GATE drive signal line GATE.
The RESET sub-circuit 160 is electrically connected to a RESET signal line RESET, the second node N2, and a first terminal of the light emitting element 110. The RESET sub-circuit 160 is configured to RESET the second node N2 and the first terminal of the light emitting element 110 with a RESET signal under the control of a RESET signal from a RESET signal line RESET.
Fig. 2 illustrates a more detailed structure of the pixel driving circuit 100 of fig. 1 according to an embodiment of the present disclosure.
As shown in fig. 2, the driving sub-circuit 120 includes a driving transistor Md, a first transistor M1, and a storage capacitor Cst.
The control electrode of the driving transistor Md is electrically connected to the second node N2, the first electrode and the first light-emitting control sub-circuit 130 are electrically connected to the first node N1, and the second electrode and the second light-emitting control sub-circuit 140 are electrically connected to the third node N3.
The control electrode of the first transistor M1 receives the GATE driving signal GATE, the first electrode is electrically connected to the third node N3, and the second electrode is electrically connected to the second node N2.
The storage capacitor Cst has a first terminal electrically connected to the first voltage signal line V1 for receiving the first voltage signal, and a second terminal electrically connected to the second node N2.
The first transistor M1 and the drive transistor Md are different types of transistors. Specifically, in the present exemplary embodiment, description is made with the drive transistor Md being a P-type transistor, and therefore, the first transistor M1 is illustratively an N-type transistor.
The first light emission control sub-circuit 130 includes a second transistor M2, and the second light emission control sub-circuit 140 includes a third transistor M3.
Specifically, the control electrode of the second transistor M2 is electrically connected to the emission control signal line EM, the first electrode is electrically connected to the first voltage signal line V1 to receive the first voltage signal, and the second electrode is electrically connected to the first node N1.
A control electrode of the third transistor M3 is electrically connected to the light emission control signal line EM, a first electrode is electrically connected to the third node N3, a second electrode is electrically connected to the first terminal of the light emitting element 110,
the second transistor M2 and the third transistor M3 are the same type of transistors as the driving transistor Md. In the present exemplary embodiment, the second transistor M2 and the third transistor M3 are both P-type transistors.
The drive control sub-circuit 150 includes a fourth transistor M4.
The control electrode of the fourth transistor M4 is electrically connected to the GATE driving signal line GATE, the first electrode is electrically connected to the DATA signal line DATA to receive the DATA signal, and the second electrode is electrically connected to the second node N2.
The fourth transistor M4 is a different type of transistor from the drive transistor Md. In the present exemplary embodiment, the fourth transistor M4 is an N-type transistor.
The reset sub-circuit 160 includes a fifth transistor M5 and a sixth transistor M6.
A control electrode and a first electrode of the fifth transistor M5 are electrically connected in common to a RESET signal line RESET, and a second electrode is electrically connected to the second node N2.
A control electrode and a first electrode of the sixth transistor M6 are electrically connected in common to a RESET signal line RESET, and a second electrode is electrically connected to a first terminal of the light emitting element 110.
The fifth transistor M5 and the sixth transistor M6 are the same type of transistors as the drive transistor Md. In the present exemplary embodiment, the fifth transistor M5 and the sixth transistor M6 are P-type transistors.
Fig. 3A shows a signal timing diagram of the pixel driving circuit 100 of fig. 2.
Specifically, referring to fig. 3A, during the first phase T1, a light emission control signal (see EM) having a first level (i.e., a high level VH) is provided, and a RESET signal (see RESET) and a GATE driving signal (see GATE) having a second level (i.e., a low level VL) are provided.
Thus, during the first period T1, the second transistor M2 and the third transistor M3 are turned off under the control of the light emission control signal; the first transistor M1 and the fourth transistor M4 are turned off under the control of the gate driving signal; the fifth transistor M5 and the sixth transistor M6 are turned on under the control of the reset signal. The schematic diagram of the pixel drive circuit 100 at this time is shown in fig. 3B, and it should be noted that the transistors turned off at this stage in fig. 3B are marked by cross crosses.
In the case where the fifth transistor M5 is turned on, the reset signal of the low level is transmitted to the second node N2, and in the case where the sixth transistor M6 is turned on, the reset signal of the low level is transmitted to the first terminal of the light emitting element 110. Accordingly, the low-level reset signal causes the control electrode of the drive transistor Md to become low level, which turns on the drive transistor Md. Also, the anode of the light emitting element 110 becomes low level. Thus, the anode of the light emitting element 110 and the driving transistor Md are both reset at a low level. Therefore, the first phase T1 is also referred to as a "reset phase".
During the second period T2, the light emission control signal and the gate driving signal having the first level (i.e., the high level VH) are supplied, the reset signal having the reference level is supplied, and the DATA signal (see DATA) having the first level is supplied. The reference level is also high REF in embodiments where the drive transistor is a P-type transistor. In some embodiments, the high level REF is equal to the sum of the high level VH and the threshold voltage of the driving transistor (here, the threshold voltage Vth of the N-type transistor is considered to be a positive value, and the threshold voltage of the P-type transistor is considered to be a negative value).
Thus, during the second stage T2, the second transistor M2 and the third transistor M3 are turned off under the control of the light emission control signal; the first transistor M1 and the fourth transistor M4 are turned on under the control of the gate driving signal; under the control of the reset signal, the fifth transistor M5 and the sixth transistor M6 are turned off. The schematic diagram of the pixel drive circuit 100 at this time is shown in fig. 3C, and it should be noted that the transistors turned off at this stage in fig. 3C are marked by cross crosses.
With the fourth transistor M4 turned on, the data signal of the high level is transmitted to the first node N1. Since the driving transistor Md is in the on state in the previous stage, the driving transistor Md is still in the on state at this time, so that the data signal of the high level continues to be transmitted to the third node N3. With the first transistor M1 turned on, the data signal (voltage Vdata) of the high level continues to be transmitted to the second node N2 to charge the second node N2 at the low level. As the voltage of the second node N2 continuously rises, the gate-source voltage Vgs of the driving transistor Md gradually increases from VL-Vdata until Vgs becomes Vth, which is the threshold voltage of the driving transistor Md. At this time, the drive transistor Md is no longer turned on, while stopping charging the second node N2. At this time, the voltage at the second node N2 (i.e., the gate of Md) is Vg ═ Vgs + Vs ═ Vdata + Vth. The data voltage Vdata has been written to the second node N2. Therefore, the second phase T2 can also be referred to as a "data voltage writing phase". In some embodiments, Vdata may have a first level (i.e., a high level VH).
During the third stage T3, the reset signal having the reference level (i.e., high level REF) is supplied, and the light emission control signal and the gate driving signal having the second level (i.e., low level VL) are supplied.
Thus, during the third stage T3, the second transistor M2 and the third transistor M3 are turned on under the control of the light emission control signal; the first transistor M1 and the fourth transistor M4 are turned off under the control of the gate driving signal; under the control of the reset signal, the fifth transistor M5 and the sixth transistor M6 are turned off. The schematic diagram of the pixel drive circuit 100 at this time is shown in fig. 3D, and it should be noted that the transistors which are turned off at this stage in fig. 3D are marked by cross crosses.
With the second transistor M2 turned on, the first voltage V1 (i.e., ELVDD) is transmitted to the first node N1, i.e., the source voltage Vs of the driving transistor Md is ELVDD. At this time, since both the first transistor M1 and the fifth transistor M5 are turned off, the second node N2 is in a floating state, and its voltage is maintained at Vdata + Vth, that is, the controller voltage Vg of the driving transistor Md is Vdata + Vth, and thus Vgs is Vdata + Vth-ELVDD, which is less than Vth, so that the driving transistor Md is turned on. With the third transistor M3 turned on, the driving current Id generated by the driving transistor Md is applied to the anode of the light emitting cell 110, and drives the light emitting cell to emit light. Therefore, the third stage T3 is also referred to as a "lighting stage".
Specifically, the expression of the drive current Id is:
Id＝K·(Vgs-Vth)2
＝K·(Vdata+Vth-ELVDD-Vth)2
＝K·(ELVDD-Vdata)2
where K is a current constant associated with the drive transistor Md and is related to the process parameters and the geometry of the drive transistor Md. As can be seen from the above equation, the driving current Id for driving the light emitting element 110 to emit light is independent of the threshold voltage Vth of the driving transistor Md.
In the above-described embodiments of the present disclosure, the pixel drive circuit realizes driving of the light emitting element on the basis of compensating the threshold voltage of the drive transistor Md. It should be noted that the pixel drive circuit of the present disclosure is connected only to the GATE drive signal line GATE, the emission control signal line EM, the RESET signal line RESET, and the DATA signal line DATA, and it is not necessary to electrically connect each pixel drive circuit to the initial signal line Vint as in the pixel drive circuit of the related art. Therefore, the pixel driving circuit according to the embodiment of the disclosure can save the wiring space, realize a more compact circuit layout, and is more favorable for realizing high PPI.
Further, as can be seen from the above, during the data voltage writing period T2 and the light emitting period T3, the first pole of the fifth transistor M5 receives the reference level having the high level REF. In some embodiments, the high level REF is equal to the sum of the high level VH and the threshold voltage Vth of the drive transistor Md, i.e., REF ═ VH + Vth. In some embodiments, during the data voltage writing period T2 and the light emitting period T3, the voltage of the second pole (i.e., the second node N2) of the fifth transistor M5 is Vdata + Vth — VH + Vth. Thus, in this embodiment, when the fifth transistor M5 leaks, the second node N2 is not discharged, so that the gate leakage of the driving transistor Md can be suppressed. The pixel driving circuit according to the embodiment of the present disclosure has significant advantages compared to the related art.
Fig. 4 shows a schematic block diagram of a display panel 400 according to an embodiment of the present disclosure. As shown in fig. 4, the display panel 400 may include a plurality of scan lines SL; a plurality of data lines DL crossing the plurality of scanning signal lines SL in a longitudinal and lateral direction; and a plurality of pixel units 410 disposed in a matrix at intersections of each scanning signal line and each data signal line and electrically connected to the corresponding data lines DL and SL. Each of the plurality of pixel cells 410 has disposed therein a pixel drive circuit according to an embodiment of the present disclosure, such as the pixel drive circuit 100 shown in fig. 1 or 2.
Specifically, the data signal lines to which the pixel driving circuit 100 is electrically connected are operated by the corresponding data lines DL of the pixel unit 410, and the gate driving signal lines to which the pixel driving circuit 100 is electrically connected are operated by the corresponding scan lines SL of the pixel unit 410.
In some embodiments, the display panel 400 may further include a plurality of light emission control lines EL arranged in parallel with the plurality of scan lines SL or the plurality of data lines DL and electrically connected to the same pixel unit 410 as the plurality of scan lines SL or the plurality of data lines DL, respectively,
specifically, the light emission control signal line to which the pixel drive circuit 100 is electrically connected is served by the corresponding light emission control line EL of the pixel unit 410.
In some embodiments, the reset signal received by the pixel driving circuit 100 is provided by a previous scan line SL of the corresponding scan line SL of the pixel unit 410 in the scan order.
In some embodiments, the display panel 400 further includes a plurality of inverters. The plurality of inverters are electrically connected to the plurality of scan lines SL in a one-to-one correspondence, respectively.
Fig. 5 shows a schematic configuration diagram of the inverter 500.
As shown in fig. 5, an input terminal of the inverter 500 is electrically connected to a (corresponding) scan line SL, and an output terminal of the inverter 500 is electrically connected to a reset line RST of the pixel unit 410 driven by the scan line SL. The RESET signal line RESET, to which the pixel drive circuit 100 in the pixel unit 410 is electrically connected, is served by the RESET line RST.
Inverter 500 is also electrically connected to reset level terminal VINIT and reference level terminal VREF. The inverter 500 is configured to supply a reset level from a reset level terminal VINIT or a reference level from a reference level terminal VREF to a reset line RST under the control of a gate driving signal from the scan line SL.
In some embodiments, the reset level is a level corresponding to an active level of the drive transistor Md (e.g., the low level VL in the above-described embodiments), and the reference level REF is equal to the sum of an inactive level of the drive transistor Md and the threshold voltage Vth of the drive transistor Md (e.g., REF + Vth in the above-described embodiments).
Fig. 6 shows a more detailed circuit diagram of the inverter 500.
The inverter 500 includes a first inverting transistor Mi1 and a second inverting transistor Mi 2. The control electrode of the first inverter transistor Mi1 is electrically connected to the scan line SL, the first electrode is electrically connected to the reset level terminal VINIT, and the second electrode is electrically connected to the reset line RST. The control electrode of the second inverting transistor Mi2 is electrically connected to the scan line SL, the second electrode is electrically connected to the reference level terminal VREF, and the second electrode is electrically connected to the reset line RST. The first inverting transistor Mi1 and the second inverting transistor Mi2 are different types of transistors. For example, as shown in fig. 6, the first inverting transistor Mi1 is an N-type transistor, and the second inverting transistor Mi2 is a P-type transistor.
With the exemplary circuit of the inverter shown in fig. 6, the reset signal required in the pixel driving circuit can be obtained on the basis of the gate driving signal from the scanning line, and the phases of the gate driving signal and the reset signal can be referred to the timing chart shown in fig. 3A.
Fig. 7 shows a flow chart of a driving method 700 of a pixel driving circuit according to an embodiment of the disclosure. The driving method 700 may be used to drive the pixel driving circuit 100 according to fig. 1 or fig. 2.
As shown in fig. 7, in step S710, in a first period, a light emission control signal having a first level is supplied, a gate driving signal and a reset signal having a second level are supplied, and a data signal having a second level is supplied.
In step S720, in a second period, the light emission control signal and the gate driving signal having the first level are supplied, the reset signal having the reference level is supplied, and the data signal having the first level is supplied.
In step S730, in the third period, the reset signal having the reference level is supplied, the light emission control signal having the second level, the gate driving signal, and the data signal having the second level are supplied.
Wherein the first level is a level corresponding to an inactive level of the driving transistor, and the second level is a level corresponding to an active level of the driving transistor.
In some embodiments, the reference level is equal to a sum of the first level and a threshold voltage of the drive transistor.
The driving process of the method 700 in different embodiments is described above with reference to fig. 2, and is not described herein again.
The foregoing detailed description has set forth numerous embodiments via the use of schematics, flowcharts, and/or examples. Where such diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those within the art that each function and/or operation within such diagrams, flowcharts, or examples can be implemented, individually and/or collectively, by a wide range of structures, hardware, software, firmware, or virtually any combination thereof.
While the present disclosure has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present disclosure may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.

Claims (9)

1. A display panel, comprising:
a plurality of scan lines;
a plurality of data lines crossing the plurality of scan lines;
a plurality of pixel units disposed at intersections of each data line and each scan line in a matrix and electrically connected to the corresponding data line and scan line, each pixel unit including a pixel driving circuit including:
a light emitting element;
a driving sub-circuit electrically connected to the first node, the second node, and the third node, configured to turn on a path between the first node and the third node under control of a voltage of the second node, and to generate a current for causing the light emitting element to emit light in the path;
a first light emission control sub-circuit electrically connected to a light emission control signal line, a first voltage signal line, and the first node, and a second light emission control sub-circuit electrically connected to the light emission control signal line, the third node, and a first end of a light emitting element, the first and second light emission control sub-circuits being configured to transmit the current for causing the light emitting element to emit light to the first end of the light emitting element under control of a light emission control signal from the light emission control signal line;
a driving control sub-circuit electrically connected to a gate driving signal line, a data signal line, and the first node, configured to supply a data signal from the data signal line to the first node under control of a gate driving signal from the gate driving signal line;
a reset sub-circuit electrically connected to a reset signal line, the second node, and the first terminal of the light emitting element, and configured to reset the second node and the first terminal of the light emitting element using a reset signal under control of the reset signal from the reset signal line; and
the plurality of phase inverters are electrically connected with the plurality of scanning lines in a one-to-one correspondence mode, the input ends of the phase inverters are electrically connected with the corresponding scanning lines, and the output ends of the phase inverters are electrically connected with the reset lines of the pixel units driven by the corresponding scanning lines; the inverter is further electrically connected to a reset level terminal and a reference level terminal, the inverter being configured to supply a reset level from the reset level terminal or a reference level from the reference level terminal to the reset line under control of a gate driving signal from the scan line;
the data signal lines electrically connected with the pixel driving circuit are served by corresponding data lines of the pixel units, the gate driving signal lines electrically connected with the pixel driving circuit are served by corresponding scanning lines of the pixel units, and the reset signal lines electrically connected with the pixel driving circuit are served by the reset lines.
2. The display panel according to claim 1, further comprising a plurality of light emission control lines arranged in parallel with the plurality of scanning lines or the plurality of data lines and electrically connected to the same pixel cells as the plurality of scanning lines or the plurality of data lines, respectively,
wherein the light emission control signal line to which the pixel driving circuit is electrically connected is served by a corresponding light emission control line of the pixel unit.
3. The display panel of claim 1, wherein the driving sub-circuit comprises a driving transistor, a first transistor, and a storage capacitor, wherein,
a control electrode of the drive transistor is electrically connected to the second node, a first electrode is electrically connected to the first node, and a second electrode is electrically connected to the third node;
a control electrode of the first transistor is electrically connected to the gate driving signal line, a first electrode is electrically connected to the third node, and a second electrode is electrically connected to the second node; and
a first terminal of the storage capacitor is electrically connected to the first voltage signal line, a second terminal is electrically connected to the second node,
wherein the first transistor and the driving transistor are different types of transistors.
4. The display panel of claim 3, wherein the first emission control sub-circuit comprises a second transistor and the second emission control sub-circuit comprises a third transistor, wherein
A control electrode of the second transistor is electrically connected to the light emission control signal line, a first electrode is electrically connected to the first voltage signal line, and a second electrode is electrically connected to the first node;
a control electrode of the third transistor is electrically connected to the light emission control signal line, a first electrode is electrically connected to the third node, a second electrode is electrically connected to a first end of the light emitting element,
wherein the second transistor and the third transistor are the same type of transistor as the driving transistor.
5. The display panel of claim 4, wherein the drive control sub-circuit comprises a fourth transistor, wherein
A control electrode of the fourth transistor is electrically connected to the gate driving signal line, a first electrode is electrically connected to the data signal line, a second electrode is electrically connected to the second node,
wherein the fourth transistor is a different type of transistor from the driving transistor.
6. The display panel of claim 5, wherein the reset sub-circuit comprises a fifth transistor and a sixth transistor, wherein
A control electrode and a first electrode of the fifth transistor are electrically connected in common to the reset signal line, a second electrode is electrically connected to the second node,
a control electrode and a first electrode of the sixth transistor are electrically connected in common to the reset signal line, a second electrode is electrically connected to a first terminal of the light emitting element,
wherein the fifth transistor and the sixth transistor are the same type of transistor as the driving transistor.
7. The display panel of claim 1, wherein the inverter comprises a first inverting transistor and a second inverting transistor, wherein,
a control electrode of the first inverting transistor is electrically connected to the scan line, a first electrode is electrically connected to the reset level terminal, a second electrode is electrically connected to the reset line,
a control electrode of the second inverting transistor is electrically connected to the scan line, a second electrode is electrically connected to the reference level terminal, a second electrode is electrically connected to the reset line,
wherein the first inverting transistor and the second inverting transistor are different types of transistors.
8. The display panel according to claim 1, wherein the reset level is a level corresponding to an active level of a driving transistor, and the reference level is equal to a sum of an inactive level of the driving transistor and a threshold voltage of the driving transistor.
9. A method of driving a display panel according to any one of claims 1-8, comprising:
providing a light emission control signal having a first level, providing a gate driving signal and a reset signal having a second level, and providing a data signal having the second level during a first period;
providing a light emission control signal and a gate driving signal having a first level, providing a reset signal having a reference level, and providing a data signal having the first level in a second period;
in a third period, a reset signal having a reference level is supplied, a light emission control signal having a second level, a gate driving signal, and a data signal having the second level are supplied,
wherein the first level is a level corresponding to an inactive level of the driving transistor, and the second level is a level corresponding to an active level of the driving transistor;
wherein the reference level is equal to a sum of the first level and a threshold voltage of the drive transistor.
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Publication number Priority date Publication date Assignee Title
CN109859686B (en) * 2019-03-29 2021-03-23 京东方科技集团股份有限公司 Pixel driving circuit, driving method thereof and display panel

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154239A (en) * 2017-06-30 2017-09-12 武汉天马微电子有限公司 Pixel circuit, driving method, organic light-emitting display panel and display device
CN107993612A (en) * 2017-12-21 2018-05-04 信利（惠州）智能显示有限公司 A kind of AMOLED pixel-driving circuits and image element driving method
CN108389549A (en) * 2018-01-30 2018-08-10 上海天马微电子有限公司 Pixel circuit and driving method thereof, display panel and driving method thereof
CN109003586A (en) * 2018-08-03 2018-12-14 武汉华星光电半导体显示技术有限公司 A kind of pixel-driving circuit and liquid crystal display panel
CN109119027A (en) * 2018-09-10 2019-01-01 京东方科技集团股份有限公司 Pixel circuit and its driving method and display panel

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2438363A1 (en) * 2003-08-28 2005-02-28 Ignis Innovation Inc. A pixel circuit for amoled displays
US7646367B2 (en) * 2005-01-21 2010-01-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, display device and electronic apparatus
JP4655800B2 (en) * 2005-07-21 2011-03-23 セイコーエプソン株式会社 Electro-optical device and electronic apparatus
KR102164711B1 (en) * 2014-04-10 2020-10-13 삼성디스플레이 주식회사 Organic light emitting display device, and method of driving the same
CN105427806B (en) * 2016-01-06 2018-10-23 京东方科技集团股份有限公司 Pixel circuit, display base plate and display device, the method for driving display base plate
CN109859686B (en) * 2019-03-29 2021-03-23 京东方科技集团股份有限公司 Pixel driving circuit, driving method thereof and display panel

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107154239A (en) * 2017-06-30 2017-09-12 武汉天马微电子有限公司 Pixel circuit, driving method, organic light-emitting display panel and display device
CN107993612A (en) * 2017-12-21 2018-05-04 信利（惠州）智能显示有限公司 A kind of AMOLED pixel-driving circuits and image element driving method
CN108389549A (en) * 2018-01-30 2018-08-10 上海天马微电子有限公司 Pixel circuit and driving method thereof, display panel and driving method thereof
CN109003586A (en) * 2018-08-03 2018-12-14 武汉华星光电半导体显示技术有限公司 A kind of pixel-driving circuit and liquid crystal display panel
CN109119027A (en) * 2018-09-10 2019-01-01 京东方科技集团股份有限公司 Pixel circuit and its driving method and display panel

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