CN113496887B - Uniform etching method of silicon wafer for integrated circuit - Google Patents
Uniform etching method of silicon wafer for integrated circuit Download PDFInfo
- Publication number
- CN113496887B CN113496887B CN202010258298.1A CN202010258298A CN113496887B CN 113496887 B CN113496887 B CN 113496887B CN 202010258298 A CN202010258298 A CN 202010258298A CN 113496887 B CN113496887 B CN 113496887B
- Authority
- CN
- China
- Prior art keywords
- etching
- corrosion
- silicon wafer
- time
- uniform
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 93
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 93
- 239000010703 silicon Substances 0.000 title claims abstract description 93
- 238000000034 method Methods 0.000 title claims abstract description 92
- 238000005530 etching Methods 0.000 title claims abstract description 59
- 238000005260 corrosion Methods 0.000 claims abstract description 112
- 230000007797 corrosion Effects 0.000 claims abstract description 111
- 239000002253 acid Substances 0.000 claims abstract description 43
- 230000005587 bubbling Effects 0.000 claims abstract description 28
- 239000004094 surface-active agent Substances 0.000 claims abstract description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract 3
- 239000007788 liquid Substances 0.000 claims description 29
- 239000013078 crystal Substances 0.000 claims description 16
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims 1
- 229910017604 nitric acid Inorganic materials 0.000 claims 1
- BULVZWIRKLYCBC-UHFFFAOYSA-N phorate Chemical compound CCOP(=S)(OCC)SCSCC BULVZWIRKLYCBC-UHFFFAOYSA-N 0.000 abstract description 6
- 238000005498 polishing Methods 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 4
- 238000011109 contamination Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 229910021645 metal ion Inorganic materials 0.000 description 1
- 230000036632 reaction speed Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- General Chemical & Material Sciences (AREA)
- Physics & Mathematics (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Chemical & Material Sciences (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Weting (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A method for uniformly etching monocrystalline silicon wafer for integrated circuit. By HNO 3 Etching the silicon wafer by using acid etching solution prepared from HF and a surfactant C; determining a maximum thickness deviation variation according to TTV requirements of a user; determining the etching time according to the etching thickness D required by the process and the etching speed S of the acid etching solution on the silicon wafert e Then through the maximum thickness deviation change and the rotation of the silicon wafervFrequency of mechanical hand shakingfBubbling time of gastIs to obtain the bubbling timetThe method comprises the steps of carrying out a first treatment on the surface of the And according to the bubbling timetAnd etching timet e Determining whether the relationship is uniform corrosion; when the conditions are met, uniform corrosion can be realized; if the condition is not satisfied, the rotation of the silicon wafer can be heightenedvAnd mechanical hand shaking frequencyfThereby meeting the conditions and realizing uniform corrosion.
Description
Technical Field
The invention relates to a processing and manufacturing technology of a silicon chip for an integrated circuit, in particular to a method for uniformly corroding the silicon for the integrated circuit by adopting mixed acid.
Background
At present, silicon polishing sheets for integrated circuits generally adopt the technological processes of straight pulling, slicing, grinding, corrosion, rough polishing, fine polishing and cleaning. The polished wafer surface has a mechanical stress damage layer with a certain depth formed by stress generated by mechanical processing, and the surface of the silicon wafer is polluted by impurities such as metal ions. The depth of the post-polishing processed skew layer was about 7 μm. The process deformation layer is left with contamination and impurities such as abrasives and wafer fragments. The presence of such a skew layer deteriorates the surface properties of the wafer, and also causes adverse effects such as contamination diffusion in the production process. Therefore, it is necessary to remove the damage caused by polishing by other methods. Such damage is typically removed by chemically etching the surface of the wafer. Chemical etching is a chemical reaction of an acid or base with a silicon wafer at a certain concentration and a certain temperature, thereby achieving uniform chemical thinning of the surface of the silicon wafer.
In the prior art, acid etching is a commonly used silicon wafer etching method.
The acid etching is isotropic etching, and the etching liquid is HNO 3 And HF. Acid corrosion is an exothermic reaction that is carried out,no heating is required during etching, and no self-limiting process exists in a certain plane. The acid corrosion reaction is very strong, the reaction speed is high, the local corrosion rate can change due to the competitive consumption of acid liquor around the silicon wafer, so that the corrosion reaction rate is uneven, the surface of the silicon wafer is unevenly dissolved, and the surface flatness of the silicon wafer is poor. In the conventional process, a method for rotating a silicon wafer and a mode of bubbling gas are adopted to improve the uniformity of corrosion. However, in each process, an experimental verification method is adopted, and fuzzy control is adopted, so that an accurate result cannot be obtained, and the problems of exceeding total thickness deviation and low product yield are often formed.
Therefore, the invention provides a technology for uniformly etching the silicon wafer aiming at the mixed acid etching method, and a correlation equation for controlling the rotation speed of the silicon wafer, the bubbling time of the introduced gas and the manual shaking frequency of the machine is obtained through a large number of experiments, so that the mode of the silicon wafer for the integrated circuit after etching can be prejudged, the influence on the flatness of the silicon wafer is researched, and related technological parameters are reasonably controlled so as to improve the uniformity of the etching process of the silicon wafer and realize the accurate and stable control of the flatness of the acid etched silicon wafer.
Disclosure of Invention
The invention provides a uniform corrosion method of a silicon wafer for an integrated circuit, which aims to judge and accurately control the flatness change before and after the acid corrosion of the silicon wafer in advance, improve the uniformity of the acid corrosion process of the silicon wafer and achieve the purpose of uniform corrosion.
The invention adopts the following technical scheme:
by HNO 3 Preparing acid corrosive liquid from HF and surfactant to corrode silicon wafer, and adopting HNO 3 Etching the silicon wafer by using acid etching solution prepared from HF and a surfactant C; determining a maximum thickness deviation variation according to TTV requirements of a user; determining the etching time according to the etching thickness D required by the process and the etching speed S of the acid etching solution on the silicon wafert e Then through the maximum thickness deviation change and the rotation of the silicon wafervFrequency of mechanical hand shakingfBubbling time of gastIs to obtain the bubbling timetThe method comprises the steps of carrying out a first treatment on the surface of the And according to the bubbling timetAnd etching timet e If the relation of the (2) is the uniform corrosion, if the condition is met, the requirement can be met, and the uniform corrosion is realized; if the condition is not satisfied, the rotation of the silicon wafer can be heightenedvAnd mechanical hand shaking frequencyfThereby meeting the conditions and realizing uniform corrosion.
The specific method comprises the following steps:
firstly, preparing an acid corrosive liquid, wherein the component proportioning range of the acid corrosive liquid is as follows:
HNO 3 : HF : C = 270 : 15 : 1 ～ 275 : 15 : 1 (1)
wherein HNO is of the formula 3 The concentration range of (2) is: 65-75%, the concentration range of HF is: 55-65%.
Second, confirm the corrosion timet e . In the etching process, etching timet e The relation with the corrosion thickness D required by the process is as follows:
wherein D is the corrosion thickness required by the process, the unit is mu m,Sthe corrosion speed of the acid corrosive liquid to the silicon wafer is expressed as mu m/s.
Third, the maximum thickness deviation change that can be generated by corrosion is confirmed. Post etch silicon waferTTVVariation from thickness deltaTTV max The relation of (2) is:
in the method, in the process of the invention,TTV 0 thickness deviation before silicon wafer corrosion is given in μm.
Fourth, determining bubbling time of the gast . By maximum thickness deviation variation and rotation of silicon wafervFrequency of mechanical hand shakingfBubbling time of gastThe bubbling time was determined.
Variation of thickness deviation deltaTTV max Rotated with the silicon wafervFrequency of mechanical hand shakingfBubbling time of gastThe relation of (2) is:
wherein A and B are constants,mis the rotation index of the silicon wafer,nis a mechanical hand shaking frequency index;
is HNO in corrosive liquid 3 Is a concentration of (2); t is the temperature of the corrosive liquid, the unit is,tthe unit is s, which is the bubbling time of the gas.
The temperature range of the corrosive liquid in the equation is 15-35 ℃. Bubbling timetRanging from 20 to 120s.
Fifth step, by etching timet e And bubbling timetTo confirm whether the corrosion is uniform. In the process of uniform corrosion, the bubbling time of gastAnd process etching timet e The uniform corrosion relationship of (2) is:
wherein D is the corrosion thickness required by the process, the unit is mu m,Sthe corrosion speed of the acid corrosive liquid to the silicon wafer is expressed as mu m/s.
Satisfying the relation (7), the etching can be started for uniform etching.
Sixth step, if not satisfiedRelation (7), turning up the silicon wafervFrequency of mechanical hand shakingfCorrosion begins when relation (7) is satisfied. Silicon wafer rotationvThe adjustment range of (2) is: 20. 50 to r/min; mechanical hand shaking frequencyfThe adjustment range of (2) is: 1. 10-Hz.
Drawings
FIG. 1 is a flow chart of a method of uniform etching according to the present invention.
DETAILED DESCRIPTION OF EMBODIMENT (S) OF INVENTION
The process of the present invention will be described in detail by means of specific examples.
Example 1
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 270 : 15 : 1，HNO 3 The concentration of (2) is: 65% of HF: 55%.
Second step, the userTTVThe requirement is 7.0 μm, the previous procedureTTV 0 It was required to be 3.2 μm, so that it was determined that the maximum thickness deviation variation which can be generated by corrosion was 3.8 μm.
And thirdly, the corrosion thickness D of the process is 8.0 mu m, the corrosion temperature is 20 ℃, and the required corrosion time is 88 seconds.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 20 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, confirming the bubbling time as 117.35s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.3 mu m, the thickness deviation generated in the process is 1.1 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 2
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 275 : 15 : 1，HNO 3 The concentration of (2) is: 75% of HF: 65%.
Second step, the userTTVThe requirement is 8.0 μm, the previous procedureTTV 0 It was required to be 3.5 μm, so that it was determined that the maximum thickness deviation variation which can be generated by corrosion was 4.5 μm.
And thirdly, the corrosion thickness D of the process is 8.2 mu m, the corrosion temperature is 25 ℃, and the required corrosion time is 69s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 25 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, confirm the bubbling time to be 99.71s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.7 mu m, the thickness deviation generated in the process is 1.2 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 3
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 275 : 15 : 1，HNO 3 The concentration of (2) is: 65% of HF: 65%.
Second step, the userTTVThe requirement is 8.0 μm, the previous procedureTTV 0 It was required to be 3.7 μm to determine that the maximum thickness deviation that can be generated by corrosion was 4.3 μm.
And thirdly, the corrosion thickness D of the process is 8.0 mu m, the corrosion temperature is 35 ℃, and the required corrosion time is 72s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 25 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, confirming the bubbling time as 107.31s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.3 mu m, the thickness deviation generated in the process is 0.6 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 4
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 275 : 15 : 1，HNO 3 The concentration of (2) is: 75% of HF: 65%.
Second step, the userTTVThe requirement is 7.5 μm, the previous procedureTTV 0 It was required to be 3.5 μm, so that it was determined that the maximum thickness deviation variation which can be generated by corrosion was 4.0 μm.
And thirdly, the corrosion thickness D of the process is 8 mu m, the corrosion temperature is 20 ℃, and the required corrosion time is 88 seconds.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 20 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, confirming the bubbling time as 110.25s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.2 mu m, the thickness deviation generated in the process is 0.7 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 5
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 275 : 15 : 1，HNO 3 The concentration of (2) is: 65% of HF: 55%.
Second step, the userTTVThe requirement is 7.0 μm, the previous procedureTTV 0 It was required to be 3.4 μm to determine that the maximum thickness deviation that can be generated by corrosion was 3.6 μm.
And thirdly, the corrosion thickness D of the process is 8.3 mu m, the corrosion temperature is 25 ℃, and the required corrosion time is 74s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 21 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 9 Hz, the bubbling time was confirmed to be 92.34s according to equation 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.4 mu m, the thickness deviation generated in the process is 1.0 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 6
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 270 : 15 : 1，HNO 3 The concentration of (2) is: 75% of HF: 65%.
Second step, the userTTVThe requirement is 7.5 μm, the previous procedureTTV 0 It was required to be 3.0 μm to determine that the maximum thickness deviation that can be generated by corrosion was 4.5 μm.
And thirdly, the corrosion thickness D of the process is 8 mu m, the corrosion temperature is 25 ℃, and the required corrosion time is 76s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 50r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 3 Hz, the bubbling time was confirmed to be 87.60s according to equations 4-6; because oft ＜1.16 t e So that the repeated test condition is reset and the rotation of the silicon wafer is regulatedvThe method comprises the following steps: 22 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, the bubbling time was confirmed to be 99.41s according to the equation 4-6, and this condition satisfied the uniform corrosion relation, and corrosion was started.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.5 mu m, the thickness deviation generated in the process is 1.5 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 7
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 270 : 15 : 1，HNO 3 The concentration of (2) is: 65% of HF: 65%.
Second step, the userTTVThe requirement is 7.0 μm, the previous procedureTTV 0 It was required to be 3.6 μm, so that it was determined that the maximum thickness deviation variation which can be generated by corrosion was 3.4 μm.
And thirdly, the corrosion thickness D of the process is 8.5 mu m, the corrosion temperature is 35 ℃, and the required corrosion time is 77s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 25 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, confirming the bubbling time to be 97.49s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.4 mu m, the thickness deviation generated in the process is 0.8 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 8
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 270 : 15 : 1，HNO 3 The concentration of (2) is: 75% of HF: 55%.
Second step, the userTTVThe requirement is 8.0 μm, the previous procedureTTV 0 It was required to be 3.5 μm, so that it was determined that the maximum thickness deviation variation which can be generated by corrosion was 4.5 μm.
And thirdly, the corrosion thickness D of the process is 8 mu m, the corrosion temperature is 30 ℃, and the required corrosion time is 76s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 25 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 10Hz, confirming the bubbling time as 90.27s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 4.4 mu m, the thickness deviation generated in the process is 0.9 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Example 9
P-type silicon wafer with corrosion crystal orientation of <110
Firstly, preparing an acid corrosive liquid, wherein the acid corrosive liquid comprises the following components in parts by weight: HNO (HNO) 3 : HF : C = 275 : 15 : 1，HNO 3 The concentration of (2) is: 75% of HF: 65%.
Second step, the userTTVThe requirement is 8.0 μm, the previous procedureTTV 0 It was required to be 3.5 μm, so that it was determined that the maximum thickness deviation variation which can be generated by corrosion was 4.5 μm.
And thirdly, the corrosion thickness D of the process is 8.2 mu m, the corrosion temperature is 25 ℃, and the required corrosion time is 69s.
Fourth step, the silicon wafer rotatesvThe method comprises the following steps: 25 r/min; mechanical hand shaking frequencyfThe method comprises the following steps: 1 Hz, the bubbling time was confirmed to be 118.61s according to equations 4-6; satisfies the relation of uniform corrosion and starts to corrode.
The total thickness deviation of the silicon wafer for the integrated circuit after corrosion is 5.1 mu m, the thickness deviation generated in the process is 1.6 mu m, which is far higher than the requirement of a user, and uniform corrosion is realized. The flatness of the silicon wafer is high.
Claims (7)
1. A method for uniformly etching monocrystalline silicon wafer for integrated circuit; etching the silicon wafer by adopting acid etching solution prepared from HNO3, HF and surfactant C; determination of maximum thickness deviation variation ΔTTV by user TTV requirement max The method comprises the steps of carrying out a first treatment on the surface of the Determining etching time te according to etching thickness D required by process and etching speed S of acid etching solution on silicon wafer, and changing delta TTV according to maximum thickness deviation max And the relation between the rotation v of the silicon wafer and the mechanical hand shaking frequency f, and the bubbling time t of the gas is obtained, wherein:
n＝1.06+1.22/T (3)
wherein A and B are constants, m is a silicon wafer rotation index, and n is a mechanical hand shaking frequency index;
is HNO in corrosive liquid 3 Is a concentration of (2); t is the temperature of the corrosive liquid, the unit is the temperature, T is the bubbling time of the gas into the gas, and the unit is s; and according to bubbling time t and corrosion time t of the gas e Is to determine whether or not the relationship of (a) is uniformEtching; when the conditions are met, uniform corrosion is realized; if the conditions are not met, the rotation v of the silicon wafer and the shaking frequency f of the manipulator are increased, so that the conditions are met, and uniform corrosion is realized.
2. The method for uniformly etching a monocrystalline silicon piece according to claim 1, wherein the acid etching solution comprises the following components in proportion:
HNO 3 :HF:C＝270:15:1～275:15:1 (4)
wherein HNO is of the formula 3 The concentration range of (2) is: 65-75%, the concentration range of HF is: 55-65%.
3. The method for uniformly etching a silicon single crystal wafer according to claim 1, wherein the etching time te is determined by the relation between the etching thickness D required by the process and the etching speed S of the silicon single crystal wafer by the acid etching solution,
wherein D is the etching thickness required by the process, the unit is mu m, S is the etching speed of the acid etching solution to the silicon wafer, and the unit is mu m/S.
4. The method for uniform etching of a silicon single crystal wafer according to claim 1, wherein the TTV-to-thickness variation ΔTTV of the silicon single crystal wafer after etching max The relation of (2) is:
TTV＝TTV 0 +ΔTTT max (6)
in TTV 0 Thickness deviation before silicon wafer corrosion is given in μm.
5. The method for uniformly etching a silicon single crystal wafer according to claim 1, wherein the temperature of the etching solution is in the range of 15 to 35 ℃; the bubbling time t of the gas is 20 to 120 seconds.
6. Root of Chinese characterA method for the uniform etching of a silicon single crystal wafer according to claim 1, wherein the etching time t is set e And bubbling time t of the gas is introduced to confirm whether the corrosion is uniform; in the uniform corrosion process, the bubbling time t of the gas is introduced and the process corrosion time t is calculated e The uniform corrosion relationship of (2) is:
t＞1.16·t e (7)
satisfies the relation (7), and satisfies the condition of starting corrosion for uniform corrosion.
7. The method for uniform etching of a silicon single crystal wafer according to claim 6, wherein if the relation (7) is not satisfied, the silicon wafer rotation v and the mechanical hand frequency f are adjusted up, and the corrosion starts when the relation (7) is satisfied; the adjustment range of the rotation v of the silicon wafer is as follows: 20-50 r/min; the adjustment range of the mechanical hand shaking frequency f is as follows: 1-10 Hz.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010258298.1A CN113496887B (en) | 2020-04-03 | 2020-04-03 | Uniform etching method of silicon wafer for integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010258298.1A CN113496887B (en) | 2020-04-03 | 2020-04-03 | Uniform etching method of silicon wafer for integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113496887A CN113496887A (en) | 2021-10-12 |
| CN113496887B true CN113496887B (en) | 2023-06-02 |
Family
ID=77995111
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010258298.1A Active CN113496887B (en) | 2020-04-03 | 2020-04-03 | Uniform etching method of silicon wafer for integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113496887B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114420554B (en) * | 2021-12-31 | 2022-10-11 | 郑州合晶硅材料有限公司 | Acid etching method for controlling morphology of silicon wafer |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1074727A (en) * | 1996-08-29 | 1998-03-17 | Mitsubishi Materials Shilicon Corp | Etching device and etching |
| WO2003036706A1 (en) * | 2001-10-24 | 2003-05-01 | Sumitomo Mitsubishi Silicon Corporation | Method and apparatus for etching silicon wafer and method for analysis of impurities |
| JP2003313091A (en) * | 2002-04-22 | 2003-11-06 | Seiko Epson Corp | Method and apparatus for producing rock crystal piece |
| JP2008182201A (en) * | 2006-12-27 | 2008-08-07 | Siltronic Ag | Silicon etching method |
| CN102433563A (en) * | 2011-12-16 | 2012-05-02 | 天津中环领先材料技术有限公司 | Acid corrosion process of 8-inch monocrystalline silicon wafer for IGBT |
| JP2013098256A (en) * | 2011-10-28 | 2013-05-20 | Mitsubishi Electric Corp | Etchant pretreatment method, silicon substrate etching method, and silicon substrate etching device |
| CN109307705A (en) * | 2017-12-20 | 2019-02-05 | 重庆超硅半导体有限公司 | A kind of integrated circuit silicon single crystal rod expects tenor accurate measurement method end to end |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4493745A (en) * | 1984-01-31 | 1985-01-15 | International Business Machines Corporation | Optical emission spectroscopy end point detection in plasma etching |
| US5804090A (en) * | 1995-03-20 | 1998-09-08 | Nissan Motor Co., Ltd. | Process for etching semiconductors using a hydrazine and metal hydroxide-containing etching solution |
| JPH09129619A (en) * | 1995-08-31 | 1997-05-16 | Toshiba Corp | Etching depth measuring device |
| US5958258A (en) * | 1997-08-04 | 1999-09-28 | Tokyo Electron Yamanashi Limited | Plasma processing method in semiconductor processing system |
| US7332437B2 (en) * | 2000-06-29 | 2008-02-19 | Shin-Etsu Handotai Co., Ltd. | Method for processing semiconductor wafer and semiconductor wafer |
| JP2003133294A (en) * | 2001-10-30 | 2003-05-09 | Mitsubishi Electric Corp | Etching apparatus and etching method |
| JP2005172920A (en) * | 2003-12-08 | 2005-06-30 | Toshiba Corp | Method and program for extracting hazardous pattern |
| CN100539040C (en) * | 2006-12-05 | 2009-09-09 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of grid curb wall |
| US20090065478A1 (en) * | 2007-09-11 | 2009-03-12 | Dockery Kevin P | Measuring etching rates using low coherence interferometry |
| CN101275287A (en) * | 2008-01-02 | 2008-10-01 | 株洲南车时代电气股份有限公司 | Whirl etching system and method for large area silicon chips |
| JP5026363B2 (en) * | 2008-01-17 | 2012-09-12 | 東京エレクトロン株式会社 | Etching amount calculation method, storage medium, and etching amount calculation device |
| CN101901779B (en) * | 2009-05-27 | 2012-07-25 | 中芯国际集成电路制造(北京)有限公司 | Method for controlling processing process of STI (Shallow Trench Isolation) channel of wafer |
| US8396583B2 (en) * | 2010-03-25 | 2013-03-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and system for implementing virtual metrology in semiconductor fabrication |
| CN103693612A (en) * | 2012-09-28 | 2014-04-02 | 无锡华润上华半导体有限公司 | Silicon film preparation method |
| US10026660B2 (en) * | 2014-10-31 | 2018-07-17 | Veeco Precision Surface Processing Llc | Method of etching the back of a wafer to expose TSVs |
| US9870928B2 (en) * | 2014-10-31 | 2018-01-16 | Veeco Precision Surface Processing Llc | System and method for updating an arm scan profile through a graphical user interface |
| CN108097533B (en) * | 2017-12-21 | 2021-01-26 | 重庆超硅半导体有限公司 | Automatic gluing and bonding method for single crystal silicon rod for integrated circuit |
| US11499236B2 (en) * | 2018-03-16 | 2022-11-15 | Versum Materials Us, Llc | Etching solution for tungsten word line recess |
-
2020
- 2020-04-03 CN CN202010258298.1A patent/CN113496887B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1074727A (en) * | 1996-08-29 | 1998-03-17 | Mitsubishi Materials Shilicon Corp | Etching device and etching |
| WO2003036706A1 (en) * | 2001-10-24 | 2003-05-01 | Sumitomo Mitsubishi Silicon Corporation | Method and apparatus for etching silicon wafer and method for analysis of impurities |
| JP2003313091A (en) * | 2002-04-22 | 2003-11-06 | Seiko Epson Corp | Method and apparatus for producing rock crystal piece |
| JP2008182201A (en) * | 2006-12-27 | 2008-08-07 | Siltronic Ag | Silicon etching method |
| JP2013098256A (en) * | 2011-10-28 | 2013-05-20 | Mitsubishi Electric Corp | Etchant pretreatment method, silicon substrate etching method, and silicon substrate etching device |
| CN102433563A (en) * | 2011-12-16 | 2012-05-02 | 天津中环领先材料技术有限公司 | Acid corrosion process of 8-inch monocrystalline silicon wafer for IGBT |
| CN109307705A (en) * | 2017-12-20 | 2019-02-05 | 重庆超硅半导体有限公司 | A kind of integrated circuit silicon single crystal rod expects tenor accurate measurement method end to end |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113496887A (en) | 2021-10-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI384544B (en) | Etching method and etching device for semiconductor wafer | |
| US20120289056A1 (en) | Selective silicon nitride etch | |
| CN101415866B (en) | Method for manufacturing epitaxial wafer | |
| CN109321253A (en) | A kind of etching solution of Silicon Wafer | |
| CN101091237A (en) | Epitaxial wafer manufacturing method and epitaxial wafer | |
| CN113496887B (en) | Uniform etching method of silicon wafer for integrated circuit | |
| CN107154351B (en) | Silicon wafer polishing method and device | |
| US20130137277A1 (en) | Critical Concentration in Etching Doped Poly Silicon With HF/HNO3 | |
| JP2003197602A (en) | Method for manufacturing wafer | |
| CN110383427B (en) | Method for manufacturing wafer | |
| EP0750967A2 (en) | Method for preshaping a semiconductor substrate for polishing and structure | |
| JP2013065614A (en) | Wet etching method of silicon wafer and wet etching device | |
| JP3188902B2 (en) | Silicon wafer etching method and etching solution using the same | |
| CN106087066A (en) | A kind of method improving quartz crystal slice surface roughness | |
| EP4328958A1 (en) | Method for producing silicon wafer | |
| WO2020213246A1 (en) | Silicon wafer etching method and etching apparatus | |
| CN104347390B (en) | A kind of method of plasma etching substrate | |
| CN113496886B (en) | Method for controlling alkali corrosion removal amount of monocrystalline silicon wafer for integrated circuit | |
| JP2886411B2 (en) | Silicon wafer etchant and method thereof | |
| JP2003007672A (en) | Method of etching silicon semiconductor wafer | |
| JP2001044154A (en) | Manufacture of semiconductor wafer | |
| JP7036085B2 (en) | Etching method for silicon wafer | |
| JP2009302412A (en) | Method of manufacturing semiconductor wafer | |
| WO2021240935A1 (en) | Etching method for silicon wafer | |
| WO2023234005A1 (en) | Method for dry etching single crystal silicon wafer, method for producing single crystal silicon wafer, and single crystal silicon wafer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |