CN100539040C - The manufacture method of grid curb wall - Google Patents
The manufacture method of grid curb wall Download PDFInfo
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- CN100539040C CN100539040C CNB2006101191675A CN200610119167A CN100539040C CN 100539040 C CN100539040 C CN 100539040C CN B2006101191675 A CNB2006101191675 A CN B2006101191675A CN 200610119167 A CN200610119167 A CN 200610119167A CN 100539040 C CN100539040 C CN 100539040C
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Abstract
A kind of manufacture method of grid curb wall comprises: the semiconductor-based end with grid is provided, and described gate surface is formed with dielectric layer in upper edge, the described semiconductor-based end; Measure the thickness of the dielectric layer of described gate lateral wall, and calculate the difference of described thickness and side wall target thickness; Calculate etch period T according to described difference with to the etch rate of described dielectric layer; Described dielectric layer is carried out T time etching.This method can remedy the variation of thickness of the dielectric layer of deposition, overcomes because the etching back side wall consistency of thickness problem of poor that the thickness of dielectric layers difference causes.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, the manufacture method of grid curb wall (Spacer) in particularly a kind of semiconductor device.
Background technology
Metal oxide semiconductor transistor comprises grid and is arranged in source electrode, the drain electrode of described grid both sides substrate, the conducting channel of grid below, the gate oxide between described conducting channel and grid.Be formed with the side wall of all around gate at gate lateral wall, described side wall can be protected grid on the one hand, to such an extent as to prevent on the other hand heavy dose of source electrode and drain electrode inject too may the generation source leak near conducting channel between conducting.Particularly along with the development of semiconductor fabrication to higher technology node, the size of grid is more and more littler, conducting channel in the substrate below the grid is shorter and shorter, and the side wall that can reduce source leakage leakage current seems particularly important, and this also has higher requirement to the manufacturing process of side wall.The manufacturing process of side wall generally was divided into for two steps; at first be formed with deposition one dielectric layer on the entire substrate of grid; as silica, silicon nitride, carve the dielectric layer that (etch back) removal is positioned at source-drain electrode and grid top by returning then, and only form one around protective layer at gate lateral wall.In the manufacturing process of side wall, it is the problem that the technologist has to face that technological parameter how to control etching forms the side wall protection layer that profile and live width all meet the demands.The patent No. be US 6977184 B1 U.S. Patent Publication a kind of etching technics of grid curb wall.Fig. 1 is the flow chart of the grid curb wall etching technics of described patent disclosure.
Step 1 as shown in Figure 1, at first, provides the semiconductor-based end with grid, is coated with silicon nitride layer (S100) on the described semiconductor-based end.Generalized section as shown in Figure 2, on the semiconductor-based end 102, be formed with oxide layer 104, be formed with grid 106 on described oxide layer 104, be coated with silicon nitride layer 108 on the described semiconductor-based end 102 with grid 106, the thickness of described silicon nitride layer 108 is 400 to 1200A.
Step 3 as shown in Figure 1, stops to carry out first step etching (S120).
Step 4 as shown in Figure 1, is carried out the second step etching (S130) with second etching agent to the silicon nitride layer 108 ' of described reservation, the thickness d 2 decision etch periods of the silicon nitride layer 108 ' that described second step records when etching terminates according to first step etching.
Step 5 as shown in Figure 1, stops to carry out the second step etching, forms side wall 108a as shown in Figure 4.
The above-mentioned etching technics that is used to make side wall at first deposits a thicker silicon nitride layer, removes the part silicon nitride layer by first step etching then, and monitors remaining thickness with optical means, forms side wall thereby then carry out the second step etching.When semiconductor fabrication process develops into 90 or even during the 65nm technology node, above-mentioned existing etching technics can't be used for the manufacturing of little live width grid curb wall, because it only is 100 to cause 200A that being used to of depositing on grid made the thickness of the material of side wall, the speed of etching is also very fast in etching, etching terminal mainly relies on the time but not existing optical monitoring is controlled, thereby the thickness of the spacer material layer that deposits before making the thickness of the side wall that forms after the etching and profile to etching is comparatively responsive.Monitor the thickness of the spacer material layer that deposits before the etching in the existing lithographic method by control sheet (control wafer), determine etch period, this method between two secondary control sheets monitorings with a certain regular time the offside walling bed of material carry out etching, cause the varied in thickness of the existing etching technics offside walling bed of material to take appropriate measures, make after the etching that the consistency of side wall live width and profile is bad between the different chips, even cause the leakage current generating of the device of formation, influence the stability of device, cause yield to reduce.
Summary of the invention
Therefore, the object of the present invention is to provide a kind of manufacture method of grid curb wall, can't take appropriate measures with the varied in thickness that solves the offside walling bed of material in the existing method of manufacturing side wall, make the bad problem of consistency of side wall live width and profile between the different chips.
For achieving the above object, the manufacture method of a kind of grid curb wall provided by the invention comprises: the semiconductor-based end with grid is provided, and described gate surface is formed with dielectric layer in upper edge, the described semiconductor-based end; Measure the thickness of the dielectric layer of described gate lateral wall, and calculate the difference of described thickness and side wall target thickness; Calculate etch period T according to described difference with to the etch rate of described dielectric layer; Described dielectric layer is carried out T time etching.
Described dielectric layer is a kind of in silica, silicon nitride, the carborundum.
Measure the thickness of the dielectric layer of described gate lateral wall with optics critical size method of measurement.
This method further comprises: described dielectric layer is carried out over etching.
This method further comprises: stop to measure the residual thickness of described dielectric layer at gate lateral wall to after the described dielectric layer etching; Calculate the difference of described residual thickness and side wall target thickness; Adjust etch rate according to described difference, and with adjusted etch rate feed back to on next wafer during the dielectric layer etching to the calculation procedure of etch period.
The etching gas that described dielectric layer is carried out etching is CF
4, CH
2F
4, C
2F
6, SiF
4, NF
3, CHF
3In a kind of or the combination.
In described etching gas, mix and use O
2And N
2As assist gas.
The etching gas of described over etching is C
2H
6, CH
2F
2And O
2Mist.
Measure described gate lateral wall dielectric layer thickness step and the step that described dielectric layer carries out T time etching carried out in identical or different semiconductor equipment.
Accordingly, the present invention also provides a kind of method of measuring etch rate, comprising: form dielectric layer at the bottom of having the semiconductor of grid, and measure the thickness of the dielectric layer of described gate lateral wall; Described dielectric layer is carried out the etching of different time and measures the thickness of the dielectric layer remain in gate lateral wall respectively; The relation curve of described thickness of match and etch period; According to the rate of change of described relation curve calculated thickness to the time.
The present invention also provides a kind of manufacture method of grid curb wall, comprising: the semiconductor-based end with grid is provided, and described gate surface is formed with dielectric layer in upper edge, the described semiconductor-based end; Measure the thickness of the dielectric layer of described gate lateral wall, and calculate the difference of described thickness and side wall target thickness; Calculate etch period T according to described difference with to the etch rate of described dielectric layer; Described dielectric layer is carried out T time etching; Stop to measure the residual thickness of described dielectric layer at gate lateral wall to after the described dielectric layer etching; Calculate the poor of described residual thickness and side wall target thickness; Adjust etch rate according to the difference of described residual thickness and side wall target thickness, and when adjusted etch rate fed back to dielectric layer etching to next wafer to the calculation procedure of etch period.
Compared with prior art, the present invention has the following advantages:
The thickness of the inventive method measuring media layer before etching, and according to described thickness and etch rate calculating etch period T, the etching through described etch period T can form the side wall that reaches target thickness at gate lateral wall.This method can remedy etching back side wall live width and the profile varying that the variation of the thickness of dielectric layer causes, overcome because the etching back side wall consistency of thickness problem of poor that the thickness of dielectric layers difference causes, can improve the consistency of the live width of the grid curb wall on the different chips, improve the process window and the maintainability of etching, stability of enhancing product performance and yield.
After the etching of finishing described dielectric layer, measure after etching described dielectric layer once more at the residual thickness of gate lateral wall, to judge through after the described T time etching, whether the side wall that forms reaches target thickness, if do not have, to readjust the etch rate of dielectric layer on the follow-up semiconductor wafer and calculate etch period, pass through in this method to measure and feedback step after the etching, overcome because drift takes place etching condition and caused that the etching back side wall can not reach the defective of target thickness, feed back by twice measurement and front and back that the present invention carries out before and after the etching dielectric layer, can form the side wall that satisfies target call at gate lateral wall, improve the stability of technology.
OCD in the inventive method (Optical Critical Dimension) method has the advantage of real-time measurement, needn't be to dielectric layer to be measured destructive processing the such as cut into slices, simplify technology, reduced the profile of the side wall of expense and monitoring etching that can be real-time, so that the etching technics parameter is adjusted, make the side wall profile that forms reach requirement.
Description of drawings
Fig. 1 is the flow chart of the etching technics of existing a kind of side wall;
Fig. 2 to Fig. 4 is the corresponding structure figure of each step of the etching technics of the described side wall of Fig. 1;
Fig. 5 is the flow chart of first embodiment of the manufacture method of side wall of the present invention;
Fig. 6 to Fig. 8 is each step corresponding structure schematic diagram of first embodiment of the manufacture method of side wall of the present invention;
Fig. 9 is the flow chart of second embodiment of the manufacture method of side wall of the present invention;
Figure 10 is the flow chart of the embodiment of the method for measuring media layer etch rate of the present invention.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent more, the specific embodiment of the present invention is described in detail below in conjunction with accompanying drawing.
The manufacture method of grid curb wall of the present invention is at first measured (OCD by the optics critical size, OpticalCritical Dimension) the method measurement is deposited on the thickness of dielectric layers of gate surface, determine etch period according to the difference of the target thickness of described thickness and side wall with to the etch rate of described dielectric layer then, described dielectric layer is carried out etching and forms side wall by described definite time.The inventive method can avoid because etching back side wall live width and the profile varying that the difference of thickness of dielectric layers causes on the wafer, can improve the grid curb wall on the different chips live width consistency and to the control ability of etching technics.
Fig. 5 is the flow chart of first embodiment of the manufacture method of side wall of the present invention.
As shown in Figure 5, step 1 at first, provides the semiconductor-based end with grid, is formed with shallow trench isolation to be formed with the source region in the described semiconductor-based end, is formed with source electrode and drain electrode in described active area; Described grid is the stack architecture of polysilicon or polysilicon and metal silicide; Described gate surface is formed with dielectric layer (S200) in upper edge, the described semiconductor-based end.Described dielectric layer is a kind of in silica, silicon nitride, the carborundum, and its thickness is 100 to 200A, and dielectric layer described in the present embodiment is a silicon nitride, and thickness is 110A.The mode of the formation of described dielectric layer is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).
Step 3 is calculated etch period T (S220) according to described difference with to the etch rate of described dielectric layer.Under the situation of given etching gas and parameter, the etch rate of described dielectric layer is generally a fixing value under the constant situation of etching condition.With described dielectric layer is that silicon nitride is an example, introduces the method for a kind of measurement to the etch rate of silicon nitride material below: at first deposit a silicon nitride layer on the grid of semi-conductive substrate, measure the thickness of described silicon nitride layer; Select for use one group of fixing etching condition that described silicon nitride layer is carried out the etching of different time, and distinguish the thickness of (using the OCD method) measurement at described gate lateral wall residual silicon nitride layer; The relation curve of described thickness of match and etch period according to the rate of change of described relation curve calculated thickness to the time, just obtains the etch rate under this etching condition then.General, its corresponding residual thickness of etch period is a linear relationship, the slope that calculates this linear relationship is etch rate.
Step 4 according to described etch period T, is carried out the etching (S230) of T time to described dielectric layer.Described etching is the plasma dry etching.The etching gas that described dielectric layer is carried out etching is CF
4, CH
2F
4, C
2F
6, SiF
4, NF
3, CHF
3In a kind of or combination, in described etching gas, mix to use O
2And N
2As assist gas.By the etching of T time, formed side wall at described gate lateral wall to described dielectric layer.Because measured the thickness of dielectric layer among the present invention before etching, and calculated etch period T according to described thickness and etch rate, the etching through described etch period T can form the side wall that reaches target thickness at gate lateral wall.This method can remedy the variation of thickness of dielectric layer to the influence of the side wall that forms, has overcome because the etching back side wall consistency of thickness problem of poor that the thickness of dielectric layers difference causes, has improved the process window and the maintainability of etching.Present embodiment also comprises the step to described dielectric layer over etching (OE), and etching gas is C
2H
6, CH
2F
2And O
2Mist.By over etching to most dielectric layers, can eliminate the sufficient shape profile of described side wall bottom, help forming better side wall profile.
Need to prove, measure in the described method described gate lateral wall dielectric layer thickness with described dielectric layer is carried out etching and not only can in same semiconductor equipment, carry out but also can in different semiconductor equipments, carry out.
First embodiment to the inventive method is described below in conjunction with profile.
As shown in Figure 6, at first, provide the semiconductor-based end 200 with grid 203, in the described semiconductor-based end 200, be formed with shallow trench isolation, in described active area, be formed with source electrode 206 and drain electrode 204 from 201 to be formed with the source region; Described grid 203 is the stack architecture of polysilicon or polysilicon and metal silicide, at described grid 203 be formed with oxide layer 202 at the semiconductor-based end 200.
As shown in Figure 7, described gate surface forms dielectric layer 208 in upper edge, the described semiconductor-based end.Described dielectric layer 208 is a kind of in silica, silicon nitride, the carborundum, and its thickness is 100 to 200A, and dielectric layer described in the present embodiment 208 is a silicon nitride, and thickness is 110A.The mode of the formation of described dielectric layer 208 is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).
Measure the thickness 210 of the dielectric layer 208 of described grid 203 sidewalls, and calculate the difference of described thickness 210 and side wall target thickness.Measure the thickness 210 of described dielectric layer 208 in the present embodiment by optics critical size (OCD) method of measurement.OCD method principle is as follows: a plurality of grids 203 at the semiconductor-based end 200 can be regarded a reflecting grating as, the OCD method is by projecting a branch of polarised light on the described grating, upper surface 208a and lower surface 208b reflection back generation phase difference through the dielectric layer 208 of the diverse location on described grid 203 surfaces, produce between the upper surface 208a of the dielectric layer 208 on a plurality of grids 208 relevant positions and the reverberation of lower surface 208b and interfere, the cycle of accepting described Light Interference Streaks and calculating interference fringe by data processing by photosensitive unit, distance between the cycle of described interference fringe and the described grid 203, the thickness of the height of grid 203 and described dielectric layer 208, refraction coefficient, reflection coefficient, absorption coefficient all has relation, cycle by the interference fringe that obtained with and with the relation of the thickness 210 of described dielectric layer 208, by calculating the thickness 210 that can obtain dielectric layer to be monitored 208.
Calculate etch period T according to described difference with to the etch rate of described dielectric layer 203.Under the situation of given etching gas and parameter, the etch rate of described dielectric layer 203 is generally a fixing value under the constant situation of etching condition.With described dielectric layer 208 is that silicon nitride is an example, introduces the method for a kind of measurement to the etch rate of silicon nitride material below: at first deposit a silicon nitride layer on the grid of semi-conductive substrate, measure the thickness of described silicon nitride layer; Select for use one group of fixing etching condition that described silicon nitride layer is carried out the etching of different time, and measure thickness respectively at described gate lateral wall residual silicon nitride layer; The relation curve of described thickness of match and etch period according to the rate of change of described relation curve calculated thickness to the time, just obtains the etch rate under this etching condition then.General, its corresponding residual thickness of etch period is a linear relationship, the slope that calculates this linear relationship is etch rate.
According to described etch period T, described dielectric layer 208 is carried out the etching of T time.Described etching is the plasma dry etching.The etching gas that described dielectric layer 208 is carried out etching is CF
4, CH
2F
4, C
2F
6, SiF
4, NF
3, CHF
3In a kind of or combination, in described etching gas, mix to use O
2And N
2As assist gas.By the etching of T time, at described grid 203 sidewalls formation side wall 211 as shown in Figure 8 to described dielectric layer 208.
Measure in the described method described grid 203 sidewalls dielectric layer 208 thickness 210 with described dielectric layer 208 is carried out etching not only can in same semiconductor equipment, carry out but also can in different semiconductor equipments, carry out.
Fig. 9 is the flow chart of second embodiment of the manufacture method of side wall of the present invention.
As shown in Figure 9, step 1 at first, provides the semiconductor-based end with grid, is formed with shallow trench isolation to be formed with the source region in the described semiconductor-based end, is formed with source electrode and drain electrode in described active area; Described grid is the stack architecture of polysilicon or polysilicon and metal silicide; Described gate surface is formed with dielectric layer (S200) in upper edge, the described semiconductor-based end.Described dielectric layer is a kind of in silica silicon nitride, the carborundum, and its thickness is 100 to 200A, and dielectric layer described in the present embodiment is a silicon nitride, and thickness is 110A.The mode of the formation of described dielectric layer is a kind of in physical vapour deposition (PVD), the chemical vapour deposition (CVD).
Step 3 is calculated etch period T (S220) according to described difference with to the etch rate of described dielectric layer.Under the situation of given etching gas and parameter, the etch rate of described dielectric layer is generally a fixing value under the constant situation of etching condition.With described dielectric layer is that silicon nitride is an example, introduces the method for a kind of measurement to the etch rate of silicon nitride material below: at first deposit a silicon nitride layer on the grid of semi-conductive substrate, measure the thickness of described silicon nitride layer; Select for use one group of fixing etching condition that described silicon nitride layer is carried out the etching of different time, and measure thickness respectively at described gate lateral wall residual silicon nitride layer; The relation curve of described thickness of match and etch period according to the rate of change of described relation curve calculated thickness to the time, just obtains the etch rate under this etching condition then.General, its corresponding residual thickness of etch period is a linear relationship, the slope that calculates this linear relationship is etch rate.
Step 4 according to described etch period T, is carried out the etching (S230) of T time to described dielectric layer.Described etching is the plasma dry etching.The etching gas that described dielectric layer is carried out etching is CF
4, CH
2F
4, C
2F
6, SiF
4, NF
3, CHF
3In a kind of or combination, in described etching gas, mix to use O
2And N
2As assist gas.By the etching of T time, formed side wall at described gate lateral wall to described dielectric layer.
Step 5 stops after the described dielectric layer etching, measures the residual thickness (S240) of described dielectric layer at gate lateral wall.The method of described measurement is the OCD method.
Step 6 is calculated the difference (S250) of the target thickness of described residual thickness and side wall.
Step 7 judges whether described difference is zero (S260), if zero, finish;
If described difference is non-vanishing, adjust described etch rate (S270) according to described difference, and when it is fed back to dielectric layer etching to next wafer to the calculation procedure of etch period,
Among the inventive method embodiment before etching the thickness to described dielectric layer measure, and calculate etch period T according to described thickness and etch rate, the etching through described etch period T can form the side wall that reaches target thickness at gate lateral wall.This method can remedy the variation of thickness of dielectric layer of deposition to the influence of the profile of the side wall that forms, overcomes because the etching back side wall consistency of thickness problem of poor that the thickness of dielectric layers difference causes.In addition, after the etching of finishing described dielectric layer, measure after etching described dielectric layer once more at the residual thickness of gate lateral wall, to judge through after the described T time etching, whether the side wall that forms reaches target thickness, if do not have, will readjust the etch rate of dielectric layer etching on the follow-up semiconductor wafer and calculate etch period.In this method by the feedback step after the etching, overcome because drift takes place etching condition and caused that the etching back side wall can not reach the defective of target thickness, feed back by twice measurement and front and back that the present invention carries out before and after the etching dielectric layer, can form the side wall that satisfies target call at gate lateral wall, improve the stability of technology.Same, the step of the thickness of the dielectric layer of the described gate lateral wall of measurement not only can be carried out in same semiconductor equipment but also can be carried out in different semiconductor equipments with the step of described dielectric layer being carried out etching in the described method.
The present invention also provides the method for a kind of measurement to the etch rate of dielectric layer.With described dielectric layer is that silicon nitride is an example, introduces the method for a kind of measurement to the etch rate of silicon nitride material below:
As shown in figure 10, at first deposit a silicon nitride layer on the grid of semiconductor substrate, measure the thickness (S300) of described silicon nitride layer, the method for described measurement is the OCD method;
Select for use one group of fixing etching condition that described silicon nitride layer is carried out the etching of different time, and measure thickness (S310) respectively at described gate lateral wall residual silicon nitride layer;
The relation curve (S320) of described thickness of match and etch period then;
According to the rate of change of described relation curve calculated thickness, obtain the etch rate (S330) under this etching condition to the time.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (10)
1, a kind of manufacture method of grid curb wall comprises:
The one semiconductor-based end with grid was provided, and described gate surface is formed with dielectric layer in upper edge, the described semiconductor-based end;
Measure the thickness of the dielectric layer of described gate lateral wall, and calculate the difference of described thickness and side wall target thickness;
Calculate etch period T according to described difference with to the etch rate of the dielectric layer of described gate lateral wall;
Described dielectric layer is carried out T time etching, and wherein, the method for thickness of measuring the dielectric layer of described gate lateral wall is an optics critical size mensuration.
2, the manufacture method of grid curb wall as claimed in claim 1 is characterized in that: described dielectric layer is a kind of in silica, silicon nitride, the carborundum.
3, the manufacture method of grid curb wall as claimed in claim 1 is characterized in that, this method further comprises: described dielectric layer is carried out over etching.
4, the manufacture method of grid curb wall as claimed in claim 1 is characterized in that, this method further comprises:
Stop to measure the residual thickness of described dielectric layer at gate lateral wall to after the described dielectric layer etching;
Calculate the difference of described residual thickness and side wall target thickness;
Adjust etch rate according to described difference, and with adjusted etch rate feed back to on next wafer during the dielectric layer etching to the calculation procedure of etch period.
5, the manufacture method of grid curb wall as claimed in claim 1 is characterized in that: the etching gas that described dielectric layer is carried out etching is CF
4, C
2F
6, SiF
4, NF
3, CHF
3In a kind of or the combination.
6, the manufacture method of grid curb wall as claimed in claim 5 is characterized in that: mix in described etching gas and use O
2And N
2As assist gas.
7, the manufacture method of grid curb wall as claimed in claim 3 is characterized in that: the etching gas of described over etching is C
2H
6, CH
2F
2And O
2Mist.
8, the manufacture method of grid curb wall as claimed in claim 1 is characterized in that: measure described gate lateral wall dielectric layer thickness step and the step that described dielectric layer carries out T time etching carried out in same semiconductor equipment.
9, the manufacture method of grid curb wall as claimed in claim 1 is characterized in that: the step of thickness of measuring the dielectric layer of described gate lateral wall is carried out in different semiconductor equipments with the step of described dielectric layer being carried out T time etching.
10, a kind of manufacture method of grid curb wall comprises:
The one semiconductor-based end with grid was provided, and described gate surface is formed with dielectric layer in upper edge, the described semiconductor-based end;
Measure the thickness of the dielectric layer of described gate lateral wall, and calculate the difference of described thickness and side wall target thickness;
Calculate etch period T according to described difference with to the etch rate of the dielectric layer of described gate lateral wall;
Described dielectric layer is carried out T time etching;
Stop to measure the residual thickness of described dielectric layer at gate lateral wall to after the described dielectric layer etching;
Calculate the poor of described residual thickness and side wall target thickness;
Adjust etch rate according to the difference of described residual thickness and side wall target thickness, and when adjusted etch rate fed back to dielectric layer etching to next wafer to the calculation procedure of etch period; Wherein,
Thickness and the described dielectric layer of measurement of measuring the dielectric layer of described gate lateral wall are optics critical size mensuration in the method for the residual thickness of gate lateral wall.
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Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102044482B (en) * | 2009-10-20 | 2013-03-06 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove |
| CN102074467B (en) * | 2009-11-20 | 2012-10-31 | 中芯国际集成电路制造(上海)有限公司 | Method for forming side wall of grid structure |
| CN102280403A (en) * | 2010-06-13 | 2011-12-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove with target critical dimension |
| CN103173766A (en) * | 2011-12-26 | 2013-06-26 | 中芯国际集成电路制造(上海)有限公司 | Advanced process control method of wet etching process |
| CN102723312A (en) * | 2012-06-20 | 2012-10-10 | 上海华力微电子有限公司 | Method for forming silicon dioxide spacer with uniform thickness |
| CN103280408B (en) * | 2013-05-31 | 2016-08-10 | 上海华力微电子有限公司 | The manufacture method of side wall in semiconductor device |
| CN106611724A (en) * | 2015-10-26 | 2017-05-03 | 北京北方微电子基地设备工艺研究中心有限责任公司 | Etching method and etching device |
| CN105632937A (en) * | 2016-03-25 | 2016-06-01 | 上海华虹宏力半导体制造有限公司 | Formation method of semiconductor structure |
| CN106128976B (en) * | 2016-08-30 | 2019-03-19 | 上海华力微电子有限公司 | A method of monitoring side wall post-etch residue |
| CN110767565A (en) * | 2019-10-31 | 2020-02-07 | 上海华力集成电路制造有限公司 | Method for measuring anti-sputtering rate |
| CN113496887B (en) * | 2020-04-03 | 2023-06-02 | 重庆超硅半导体有限公司 | Uniform etching method of silicon wafer for integrated circuit |
| CN112331615B (en) * | 2021-01-06 | 2021-04-02 | 晶芯成(北京)科技有限公司 | Method for forming semiconductor device |
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