CN102280403A - Method for forming groove with target critical dimension - Google Patents
Method for forming groove with target critical dimension Download PDFInfo
- Publication number
- CN102280403A CN102280403A CN2010102038043A CN201010203804A CN102280403A CN 102280403 A CN102280403 A CN 102280403A CN 2010102038043 A CN2010102038043 A CN 2010102038043A CN 201010203804 A CN201010203804 A CN 201010203804A CN 102280403 A CN102280403 A CN 102280403A
- Authority
- CN
- China
- Prior art keywords
- groove
- hard mask
- layer
- mask layer
- critical size
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Abstract
The invention discloses a method for forming a groove with target critical dimension. The method comprises the following steps: providing a front end device structure, wherein the front end device structure is provided with an intermetallic dielectric layer with the groove, and the material of the intermetallic dielectric layer is an oxide with a low dielectric constant; and introducing a reactant gas comprising a reducible gas, and regulating the actual critical dimension of the groove to the target critical dimension. According to the method provided by the invention, the uniformity of the critical dimension of grooves with different chips or different batches can be improved effectively, and the yield can be improved.
Description
Technical field
The present invention relates to process for fabrication of semiconductor device, particularly a kind of manufacture method of groove.
Background technology
In semiconductor fabrication process, on Semiconductor substrate, form needed through hole or groove, be used for the application such as (embedding techniques) of backend interconnect technology Damascus technics.Because copper has excellent conducting performance, thereby is used as the material of backend interconnect line in the semiconductor integrated circuit manufacturing process.Copper interconnecting line generally forms by mosaic technology or dual-damascene technics.Single inlay structure only is that the production method of single-layer metal lead was changed into mosaic mode (dielectric layer etching+metal filled) at that time by traditional (metal etch+dielectric layers fills).Dual-damascene structure then is that through hole and plain conductor are combined, and so only needs metal filled step together, can simplify technology.
Be example with the dual-damascene structure below, illustrate that prior art forms the technological process of groove.Figure 1A-1E is the cutaway view that conventional method forms device that each step obtains in the technological process of dual-damascene structure groove.Shown in Figure 1A, substrate 100 is provided, have metal interconnecting wires 101 on the substrate 100.On described substrate 100, be formed with etching stop layer 102 and metal intermetallic dielectric layer 103 successively, wherein, be formed with through hole in the metal intermetallic dielectric layer 103.Also leave employed hard mask layer 104 when forming through hole on the surface of metal intermetallic dielectric layer 103.Shown in Figure 1B, in through hole, be filled with bottom anti-reflection layer (BARC) 105, and cover on the surface of hard mask layer 104.On hard mask layer 104, be formed with bottom anti-reflection layer 105, low temperature oxide layer (LTO) 106, anti-reflecting layer 107 successively and have the photoresist layer 108 of pattern.Shown in Fig. 1 C, be that mask antagonistic reflex layer 107 and low temperature oxide layer 106 are carried out etching with photoresist layer 108, and photoresist layer 108 is consumed in etching process with pattern.Shown in Fig. 1 D, be that mask carries out etching to bottom anti-reflection layer 105 with anti-reflecting layer 107 and low temperature oxide layer 106, be that mask carries out etching to metal intermetallic dielectric layer 103 with bottom anti-reflection layer 105 then.Anti-reflecting layer 107 and low temperature oxide layer 106 are consumed substantially in above-mentioned etching process.For convenience, the etching process shown in Fig. 1 C and the 1D is called main etching.Shown in Fig. 1 E, feed carbon dioxide (CO
2) gas hard mask layer 104 surface is gone up and through hole in bottom anti-reflection layer 105 peel off.Shown in Fig. 1 F, carry out the removal of etching stop layer 102 in the through hole, so that the interconnecting metal that subsequent technique is filled is electrically connected with metal interconnecting wires 101.Feed CO at last
2Gas stripping remains in the polymer in the through hole, finishes the making of groove in the dual-damascene structure.
Yet, continuous reduction along with semiconductor technology node, the critical size of groove constantly dwindles, because the influence of microeffects such as thermal effect, also can there be some differences in the critical size of the groove that forms on the wafer of different chips or different batches under the same process condition.Therefore; prior art usually can be before main etching; critical size to groove is adjusted; for example adjust the critical size (ADI CD) behind the photoresist developing; adjust the size of bottom anti-reflection layer split shed or adjust the size of hard mask split shed, to improve the uniformity of groove critical size.But said method only can be before main etching be adjusted the critical size of the groove that will form subsequently.Therefore, the method for prior art only can be estimated the deviation that may occur in advance, before etching it is compensated, measures its critical size then after groove forms.The shortcoming of this mode is even deviation appears in the groove critical size that discovery obtains at last, also to have no idea to remedy.Can cause the critical dimension uniformity of different chips or different batches groove relatively poor like this, and yields is lower.
So, be badly in need of a kind of manufacture method of improved groove at present, to improve the critical dimension uniformity of different chips or different batches groove, improve yields.
Summary of the invention
Introduced the notion of a series of reduced forms in the summary of the invention part, this will further describe in the embodiment part.Summary of the invention part of the present invention does not also mean that key feature and the essential features that will attempt to limit technical scheme required for protection, does not more mean that the protection range of attempting to determine technical scheme required for protection.
The present invention proposes the method that a kind of formation has the groove of target critical dimension, comprise: the front end device architecture is provided, be formed with the metal intermetallic dielectric layer with groove on the described front end device architecture, the material of described metal intermetallic dielectric layer is the oxide of low-k; And feed the reacting gas comprise reducibility gas, the actual critical size of described groove is adjusted to described target critical dimension.
According to a further aspect in the invention, described method also comprises: detect step, wherein, described groove is detected through the described actual critical size after the described adjustment, to determine whether described groove has reached described target critical dimension.
According to a further aspect in the invention, described method also comprises: at least one is set-up procedure again, wherein, according to the result of described detection step the critical size of described groove is implemented described set-up procedure and described detection step once more.
According to a further aspect in the invention, described metal intermetallic dielectric layer with groove forms by following steps: substrate is provided; On described substrate, form metal intermetallic dielectric layer, groove hard mask layer, anti-reflecting layer that the oxide by described low-k constitutes and photoresist layer successively with pattern; Carry out main etch step, and peel off described groove hard mask layer, to form described metal intermetallic dielectric layer with groove.
According to a further aspect in the invention, before forming the described metal intermetallic dielectric layer that constitutes by the oxide of low-k, on described substrate, form etching stop layer.
According to a further aspect in the invention, described peel off groove hard mask layer step after, remove remaining etching stop layer.
According to a further aspect in the invention, described groove hard mask layer comprises one deck hard mask layer at least.
According to a further aspect in the invention, described groove hard mask layer comprises first hard mask layer and second hard mask layer that is formed on described first hard mask layer, and wherein, first hard mask layer is a bottom anti-reflection layer, and second hard mask layer is a low temperature oxide layer.
According to a further aspect in the invention, be formed with through hole in the described metal intermetallic dielectric layer.
According to a further aspect in the invention, be formed with the through hole hard mask layer on the described metal intermetallic dielectric layer, described groove hard mask layer is formed on the described through hole hard mask layer and fills described through hole.
According to a further aspect in the invention, the material of described metal intermetallic dielectric layer is a black diamond.
According to a further aspect in the invention, described reducibility gas is one or more in hydrogen and the carbon monoxide.
According to a further aspect in the invention, described reacting gas also comprises one or more in argon gas, helium and the nitrogen.
According to a further aspect in the invention, described set-up procedure comprises: according to the difference between described actual critical size and the described target critical dimension, determine the feeding time of described reacting gas.
According to a further aspect in the invention, the difference between described actual critical size and the described target critical dimension is during smaller or equal to 2nm, and the feeding time of reacting gas is 10s; Difference between described actual critical size and the described target critical dimension is during greater than 2nm and smaller or equal to 4nm, and the feeding time of reacting gas is 30s.
According to a further aspect in the invention, described set-up procedure comprises: pre-determine the relation curve between feeding time of the critical size of described groove and described reacting gas; According to the actual critical size of described groove and the difference between the target critical dimension, determine the feeding time of described reacting gas according to described relation curve.
According to a further aspect in the invention, the step that pre-determines of described relation curve comprises: measure the relation curve between feeding time of the critical size of different situations lower groove and reacting gas by experiment respectively; Select and the corresponding relation curve of groove that will adjust.
The method according to this invention can be improved the critical dimension uniformity of different chips or different batches groove effectively, improves yields.
Description of drawings
Following accompanying drawing of the present invention is used to understand the present invention at this as a part of the present invention.Embodiments of the invention and description thereof have been shown in the accompanying drawing, have been used for explaining principle of the present invention.In the accompanying drawings,
Figure 1A-1F is the cutaway view that conventional method forms device that each step obtains in the technological process of groove;
Fig. 2 is the process chart that forms the dual-damascene structure groove according to one embodiment of the present invention;
Fig. 3 A-3F is the cutaway view of device that each step obtains in the technological process of making the dual-damascene structure groove according to one embodiment of the present invention;
Fig. 4 is the relation curve between feeding time of the critical size of groove and reacting gas.
Embodiment
In the following description, a large amount of concrete details have been provided so that more thorough understanding of the invention is provided.Yet, it will be apparent to one skilled in the art that the present invention can need not one or more these details and implemented.In other example,, be not described for technical characterictics more well known in the art for fear of obscuring with the present invention.
In order thoroughly to understand the present invention, will in following description, detailed steps be proposed, so that the manufacture craft of groove of the present invention is described.Obviously, execution of the present invention is not limited to the specific details that the technical staff had the knack of of semiconductor applications.Preferred embodiment of the present invention is described in detail as follows, yet except these were described in detail, the present invention can also have other execution modes.
The inventive method comprises: the front end device architecture is provided, is formed with the metal intermetallic dielectric layer with groove on the described front end device architecture, the material of described metal intermetallic dielectric layer is the oxide of low-k; And feed the reacting gas comprise reducibility gas, the actual critical size of described groove is adjusted to described target critical dimension.The formation method of described front end device architecture is shown in step 201-205 among Fig. 2 and Fig. 3 A-3E, and described set-up procedure is shown in step 206 among Fig. 2 and Fig. 3 F.Need to prove, the device schematic diagram shown in step 201-205 and Fig. 3 A-3E only is used for explaining the method that is preferably formed of described front end device architecture among Fig. 2, described front end device architecture also can adopt additive method to form, as long as be formed with metal intermetallic dielectric layer on the described front end device architecture with groove, the material of described metal intermetallic dielectric layer is the oxide of low-k, promptly applicable to said method of the present invention.
Fig. 2 is the process chart that forms the dual-damascene structure groove according to one embodiment of the present invention.Fig. 3 A-3F is the cutaway view of device that each step obtains in the technological process of making the dual-damascene structure groove according to one embodiment of the present invention.Below in conjunction with Fig. 2 and Fig. 3 A-3F manufacture craft of the present invention is described in detail.
In step 201, substrate is provided, on substrate, form successively and form the needed layer of groove structure in through hole and the subsequent technique.
As shown in Figure 3A, provide substrate 300, include the structure (not shown) of various MOS devices on the substrate 300.In the present embodiment, this groove is used to realize the interconnection of interlayer metal, so also need have metal interconnecting wires 301 on the substrate 300, so that it is connected with the conductive structure of lower floor.Alternatively, form etching stop layer 302 on substrate 300, the thickness of etching stop layer 302 is about the 300-600 dust, and its material can be the silicon nitride of carbon containing.Forming thickness on etching stop layer 302 is the metal intermetallic dielectric layer 303 of 2000-4000 dust, is used to make insulation between top layer metallic layer and the following one deck metal level (or substrate).For the leakage current that reduces integrated circuit, reduce capacity effect between the lead, reduce integrated circuit heating etc., the material of metal intermetallic dielectric layer 303 is selected the oxide material of low-k usually for use, for example black diamond and unadulterated silica (USG) etc., wherein, black diamond is the silica (SiO with space of Applied Materials's research and development
2), described low-k can for dielectric constant smaller or equal to 3.In addition, because the dual-damascene structure groove that present embodiment is made with Damascus technics is an example, so be formed with through hole in the metal intermetallic dielectric layer 303.Alternatively, can also also leave employed through hole hard mask layer 304 when forming described through hole on the surface of metal intermetallic dielectric layer 303, its material can be silicon oxynitride (SiON), tetraethoxysilane (TEOS) etc.The effect that leaves through hole hard mask layer 304 is, can be used as the mask layer that forms groove in the subsequent technique on the one hand; On the other hand, can also be used as the layer that stops of removing metal intermetallic dielectric layer 303 each layers of top after etching groove be finished.Form the groove hard mask layer in through hole and on the through hole hard mask layer 304, this groove hard mask layer comprises one deck hard mask layer at least.According to preferred implementation of the present invention, described groove hard mask layer comprises two-layer hard mask layer.Particularly, fill first hard mask layer 305 in through hole, and make first hard mask layer 305 cover the above 1000-3000 dust in surface to through hole hard mask layer 304, first hard mask layer 305 can be a bottom anti-reflection layer.Formation thickness is that second hard mask layer, 306, the second hard mask layers 306 of 500-1500 dust can be low temperature oxide layer (LTO) on first hard mask layer 305.Forming thickness on second hard mask layer 306 is the anti-reflecting layer 307 of 500-1500 dust.On anti-reflecting layer 307, form photoresist layer 308 with pattern.
In step 202, be that the mask antagonistic reflex layer and second hard mask layer carry out etching with photoresist layer with pattern.Shown in Fig. 3 B, be that the mask antagonistic reflex layer 307 and second hard mask layer 306 carry out etching with photoresist layer 308 with pattern.Design transfer to the second hard mask layer 306, the second hard mask layers 306 of photoresist are had the opening that is used to form groove, and photoresist layer 308 is consumed substantially and finishes in etching process.
In step 203, etching forms groove on metal intermetallic dielectric layer.Shown in Fig. 3 C, be that mask carries out etching to first hard mask layer 305 with the anti-reflecting layer 307 and second hard mask layer 306, with design transfer to the first hard mask layer 305.The anti-reflecting layer 307 and second hard mask layer 306 are consumed substantially in this process.Then, be that mask carries out etching to through hole hard mask layer 304 and metal intermetallic dielectric layer 303 with first hard mask layer 305, form groove.For convenience, the etching process of describing in step 202 and 203 is defined as main etching.
In step 204, first hard mask layer 305 is peeled off.Shown in Fig. 3 D, feed that carbon dioxide is gone up through hole hard mask layer 304 surfaces and through hole in first hard mask layer 305 peel off.
In step 205, remove the etching stop layer (that is the etching stop layer that, exposes) of via bottoms.Shown in Fig. 3 E, carry out the removal of via bottoms residue etching stop layer 302, so that the interconnecting metal that subsequent technique is filled is electrically connected with metal interconnecting wires 301.The front end device architecture that provided in the method for the present invention can be provided after above-mentioned steps, be formed with metal intermetallic dielectric layer 303 on the described front end device architecture, and the material of described metal intermetallic dielectric layer be the oxide of low-k with groove.
In step 206, feed the reacting gas comprise reducibility gas, the actual critical size of groove is adjusted to target critical dimension, finish the making of groove.Described reducibility gas comprises hydrogen (H
2) and carbon monoxide (CO) etc. in one or more, the flow velocity of reducibility gas is 100-500sccm, wherein, sccm is under the standard state, just 1 atmospheric pressure, 1 cubic centimetre of (1cm of 25 degrees centigrade of following per minutes
3/ min) flow velocity.In addition, the pressure in diluting reaction gas and/or the maintenance reaction chamber can also comprise protective gas in the reacting gas.Described protective gas comprises the inert gas of for example argon gas (Ar), helium (He) and in the nitrogen one or more, and the flow velocity of protective gas is 0-300sccm.The flow velocity of concrete protective gas and kind can wait to determine according to the flow velocity of reacting gas, pressure in the reaction chamber.Preferably, the pressure of reaction chamber is between the 5-50 millitorr, and substrate bias power is 10-300 watt, and reaction temperature is 0-100 ℃.Shown in Fig. 3 F, be adjusted groove with predetermined critical size.
The method according to this invention can also comprise: detect step, groove is detected through the actual critical size after adjusting, to determine whether groove has reached target critical dimension; At least one is set-up procedure again, according to the result who detects step the critical size of described groove is implemented set-up procedure and is detected step, is adjusted to target critical dimension up to the actual critical size with groove.
The inventor finds, though under different semiconductor technologies, in order to form the various structure sheaf differences that groove adopted of various devices, but as long as metal intermetallic dielectric layer is the oxide material of low-k, the critical size of groove will be regular along with the feeding time of reacting gas to be changed, and promptly the critical size of groove increases with the prolongation of the feeding time of reacting gas.By ESEM to groove overlook profile and section profile detects, find under the different feeding time, resulting groove overlook profile and section profile remains unchanged, only the critical size of groove changes.Therefore the method according to this invention has guaranteed the electric property of formed groove.
Usually, owing in main etching process and the carbon dioxide stripping process, can adhere to some polymer on the sidewall of groove, these polymer can stop the lateral etching of groove, and therefore, the actual critical size that obtains of groove can be less than target critical dimension.According to the actual critical size of groove and the difference between the target critical dimension, the feeding time of control reacting gas is adjusted the critical size of groove.
Described set-up procedure comprises: according to the actual critical size of groove and the difference between the target critical dimension, determine the feeding time of reacting gas, make groove have adjusted critical size.For example, the difference between actual critical size and the target critical dimension is during smaller or equal to 2nm, and the feeding time that pre-determines reacting gas is 10s; Difference between actual critical size and the target critical dimension is during greater than 2nm and smaller or equal to 4nm, and the feeding time that pre-determines reacting gas is 30s.
In the practical operation,, determine the concrete operations step of the feeding time of reacting gas, comprising: pre-determine the relation curve between feeding time of the critical size of groove and reacting gas according to the actual critical size of groove and the difference between the target critical dimension; According to the actual critical size of groove and the difference between the target critical dimension, determine the feeding time of reacting gas according to this relation curve.
Wherein, the step that pre-determines of relation curve comprises: determine respectively by experiment under the different situations (as under the dielectric layer material between different metal, under the differential responses gas, under the flow velocity of differential responses gas, under the different pressures, different temperatures is inferior) critical size of groove and the relation curve between the feeding time of reacting gas; Select and the corresponding relation curve of groove that will adjust.
To describe in detail according to one embodiment of the present invention below and pre-determine the relation curve step.
At first, be determined by experiment relation curve between feeding time of the critical size of groove and reacting gas.This step will be carried out many group experiments, wherein, needs to keep other parameter constant, only changes the feeding time of reacting gas, measures the critical size of groove after reaction respectively.
According to one embodiment of the present invention, the material of metal intermetallic dielectric layer is a black diamond, and its thickness is the 2500-3000 dust.The reacting gas that feeds is a hydrogen, and the flow velocity of hydrogen is 100-250sccm.In addition, also fed nitrogen as protective gas, the flow velocity of nitrogen is 30-100sccm.In the present embodiment, the feeding time of reacting gas is adjusted in 10-30 scope second, as being 10 seconds, 15 seconds, 20 seconds, 25 seconds and 30 seconds etc.Adjust in the critical size process, between the pressure 15-35 millitorr of reaction chamber, substrate bias power is 50-150 watt.According to above-mentioned steps, obtain relation curve shown in Figure 4.As shown in Figure 4, abscissa is the feeding time of reacting gas among the figure, and ordinate is the critical size of groove.401 for testing each data point of the difference feeding pairing critical size of time that obtains, and 402 is the linear relationship that obtains according to each data point match.Along with feeding time of reacting gas constantly prolongs, the critical size of groove is increasing.
Then, according to the actual critical size of groove and the difference between the target critical dimension, determine the feeding time of reacting gas according to this relation curve.According to one embodiment of the present invention, after removing remaining etching stop layer, the actual critical size of the groove that obtains is 49nm.And target critical dimension is 51nm, and according to relation curve shown in Figure 4, the feeding time of determining reacting gas is 18-19s.
Another execution mode according to the present invention, the method according to this invention is used to make the groove of single inlay structure.In single inlay structure groove forming process, do not comprise through hole in the metal intermetallic dielectric layer 303, therefore do not have the required through hole hard mask layer 304 of the through hole of formation on the surface of metal intermetallic dielectric layer 303 yet, that is to say that the groove hard mask layer is formed directly on the surface of metal intermetallic dielectric layer 303.At this moment, step 205 should be for removing the etching stop layer (that is the etching stop layer that, exposes) of channel bottom.
The manufacture method of groove of the present invention by the feeding time of control reducibility gas, can be regulated the critical size of groove, and groove overlooked profile and almost not influence of section profile.The mechanism of above-mentioned phenomenon is comparatively complicated, the inventor thinks, may be because the oxide material reaction of reducibility gas and low-k metal intermetallic dielectric layer is reduced to the pairing simple substance of its oxide, so the volume of the metal intermetallic dielectric layer of trenched side-wall reduces.With the black diamond is example, and black diamond is the silica material with hole, and its density is less than the density (2.23g/cm of normal solid oxide silicon
3), and the density of elementary silicon is 2.33g/cm
3After feeding reducibility gas, the quality of elementary silicon is less than the quality of black diamond, and the density of elementary silicon is greater than the density of black diamond, so the volume of elementary silicon is less than the volume of black diamond, thereby makes the critical size of groove become big.
According to the manufacture method of the groove of embodiment of the present invention, can in a big way, adjust the critical size of groove easily and flexibly, make it consistent with target critical dimension.And under the different reacting gas feeding time, overlook profile and the section profile of the groove that obtains do not change, and have therefore guaranteed the electric property of device.In addition, the critical size of described adjustment groove is positioned at the final step of whole technical process, when the critical size of discovery groove is still less than target critical dimension after measuring, it can be reentered into and continues in the reative cell to adjust.Therefore, compared with prior art, can control the critical size of groove more accurately, improve key size evenness.In addition, the method that the present invention is distinctive to repeat to adjust critical size can improve yields, reduces production costs.
Have according to the semiconductor device of the groove of execution mode manufacturing as mentioned above and can be applicable in the multiple integrated circuit (IC).According to IC of the present invention for example is memory circuitry, as random-access memory (ram), dynamic ram (DRAM), synchronous dram (SDRAM), static RAM (SRAM) (SRAM) or read-only memory (ROM) or the like.According to IC of the present invention can also be logical device, as programmable logic array (PLA), application-specific integrated circuit (ASIC) (ASIC), combination type DRAM logical integrated circuit (buried type DRAM), radio circuit or other circuit devcies arbitrarily.IC chip according to the present invention can be used for for example consumer electronic products, in various electronic products such as personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera, digital camera, mobile phone, especially in the radio frequency products.
The present invention is illustrated by above-mentioned execution mode, but should be understood that, above-mentioned execution mode just is used for for example and illustrative purposes, but not is intended to the present invention is limited in the described execution mode scope.It will be appreciated by persons skilled in the art that in addition the present invention is not limited to above-mentioned execution mode, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (19)
1. a formation has the method for the groove of target critical dimension, comprising:
The front end device architecture is provided, is formed with the metal intermetallic dielectric layer with groove on the described front end device architecture, the material of described metal intermetallic dielectric layer is the oxide of low-k; And
Feeding comprises the reacting gas of reducibility gas, and the actual critical size of described groove is adjusted to described target critical dimension.
2. the method for claim 1, it is characterized in that described method also comprises: detect step, wherein, described groove is detected through the described actual critical size after the described adjustment, to determine whether described groove has reached described target critical dimension.
3. method as claimed in claim 2 is characterized in that described method also comprises: at least one is set-up procedure again, wherein, according to the result of described detection step the critical size of described groove is implemented described set-up procedure and described detection step once more.
4. the method for claim 1 is characterized in that, described metal intermetallic dielectric layer with groove forms by following steps:
Substrate is provided;
On described substrate, form metal intermetallic dielectric layer, groove hard mask layer, anti-reflecting layer that the oxide by described low-k constitutes and photoresist layer successively with pattern;
Carry out main etch step, and peel off described groove hard mask layer, to form described metal intermetallic dielectric layer with groove.
5. method as claimed in claim 4 is characterized in that, before forming the described metal intermetallic dielectric layer that is made of the oxide of low-k, forms etching stop layer on described substrate.
6. method as claimed in claim 5 is characterized in that, described peel off groove hard mask layer step after, remove the etching stop layer expose.
7. method as claimed in claim 4 is characterized in that, described groove hard mask layer comprises one deck hard mask layer at least.
8. method as claimed in claim 7, it is characterized in that described groove hard mask layer comprises first hard mask layer and second hard mask layer that is formed on described first hard mask layer, wherein, first hard mask layer is a bottom anti-reflection layer, and second hard mask layer is a low temperature oxide layer.
9. the method for claim 1 is characterized in that, is formed with through hole in the described metal intermetallic dielectric layer.
10. method as claimed in claim 9 is characterized in that, is formed with the through hole hard mask layer on the described metal intermetallic dielectric layer, and described groove hard mask layer is formed on the described through hole hard mask layer and fills described through hole.
11. the method for claim 1 is characterized in that, the material of described metal intermetallic dielectric layer is a black diamond.
12. the method for claim 1 is characterized in that, described reducibility gas is one or more in hydrogen and the carbon monoxide.
13. method as claimed in claim 12 is characterized in that, described reacting gas also comprises one or more in argon gas, helium and the nitrogen.
14., it is characterized in that described set-up procedure comprises as claim 1,2 or 3 described methods:
According to the difference between described actual critical size and the described target critical dimension, determine the feeding time of described reacting gas.
15. method as claimed in claim 14 is characterized in that, the difference between described actual critical size and the described target critical dimension is during smaller or equal to 2nm, and the feeding time of reacting gas is 10s; Difference between described actual critical size and the described target critical dimension is during greater than 2nm and smaller or equal to 4nm, and the feeding time of reacting gas is 30s.
16., it is characterized in that described set-up procedure comprises as claim 1,2 or 3 described methods:
Pre-determine the relation curve between feeding time of the critical size of described groove and described reacting gas;
According to the actual critical size of described groove and the difference between the target critical dimension, determine the feeding time of described reacting gas according to described relation curve.
17. method as claimed in claim 16 is characterized in that, the step that pre-determines of described relation curve comprises:
Measure the relation curve between feeding time of the critical size of different situations lower groove and reacting gas by experiment respectively;
Select and the corresponding relation curve of groove that will adjust.
18. an integrated circuit that comprises the groove of making by the method for claim 1, wherein said integrated circuit is selected from random access memory, dynamic random access memory, synchronous RAM, static RAM, read-only memory, programmable logic array, application-specific integrated circuit (ASIC), buried type DRAM and radio circuit.
19. an electronic equipment that comprises the groove of making by the method for claim 1, wherein said electronic equipment is selected from personal computer, portable computer, game machine, cellular phone, personal digital assistant, video camera and digital camera.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102038043A CN102280403A (en) | 2010-06-13 | 2010-06-13 | Method for forming groove with target critical dimension |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102038043A CN102280403A (en) | 2010-06-13 | 2010-06-13 | Method for forming groove with target critical dimension |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102280403A true CN102280403A (en) | 2011-12-14 |
Family
ID=45105764
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102038043A Pending CN102280403A (en) | 2010-06-13 | 2010-06-13 | Method for forming groove with target critical dimension |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102280403A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097493A (en) * | 2014-04-24 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN105142327A (en) * | 2014-05-26 | 2015-12-09 | 上海蓝沛新材料科技股份有限公司 | Anti-reflective embedded micro/nano metal interconnection line and preparation method thereof |
| CN105225942A (en) * | 2014-06-27 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| CN107978554A (en) * | 2016-10-21 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN113140505A (en) * | 2021-03-18 | 2021-07-20 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050059251A1 (en) * | 2003-09-12 | 2005-03-17 | Taiwan Semicondutor Manufacturing Co. | Constant and reducible hole bottom CD in variable post-CMP thickness and after-development-inspection CD |
| US7189643B2 (en) * | 2003-07-25 | 2007-03-13 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
| CN101197275A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method of grids curb wall |
| CN101266943A (en) * | 2007-03-16 | 2008-09-17 | 恩益禧电子股份有限公司 | Method of manufacturing semiconductor device and control system |
-
2010
- 2010-06-13 CN CN2010102038043A patent/CN102280403A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7189643B2 (en) * | 2003-07-25 | 2007-03-13 | Fujitsu Limited | Semiconductor device and method of fabricating the same |
| US20050059251A1 (en) * | 2003-09-12 | 2005-03-17 | Taiwan Semicondutor Manufacturing Co. | Constant and reducible hole bottom CD in variable post-CMP thickness and after-development-inspection CD |
| CN101197275A (en) * | 2006-12-05 | 2008-06-11 | 中芯国际集成电路制造(上海)有限公司 | Production method of grids curb wall |
| CN101266943A (en) * | 2007-03-16 | 2008-09-17 | 恩益禧电子股份有限公司 | Method of manufacturing semiconductor device and control system |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105097493A (en) * | 2014-04-24 | 2015-11-25 | 中芯国际集成电路制造(上海)有限公司 | Manufacture method of semiconductor device |
| CN105097493B (en) * | 2014-04-24 | 2020-09-08 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
| CN105142327A (en) * | 2014-05-26 | 2015-12-09 | 上海蓝沛新材料科技股份有限公司 | Anti-reflective embedded micro/nano metal interconnection line and preparation method thereof |
| CN105142327B (en) * | 2014-05-26 | 2018-11-27 | 上海蓝沛信泰光电科技有限公司 | A kind of embedded micro-nano metal interconnection route of antireflection and preparation method thereof |
| CN105225942A (en) * | 2014-06-27 | 2016-01-06 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| CN105225942B (en) * | 2014-06-27 | 2018-06-29 | 中芯国际集成电路制造(上海)有限公司 | Lithographic method |
| CN107978554A (en) * | 2016-10-21 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof, electronic device |
| CN113140505A (en) * | 2021-03-18 | 2021-07-20 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
| CN113140505B (en) * | 2021-03-18 | 2023-08-11 | 上海华力集成电路制造有限公司 | Method for manufacturing through hole |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8610279B2 (en) | Microfeature workpieces having conductive interconnect structures formed by chemically reactive processes, and associated systems and methods | |
| CN107946193B (en) | Three-dimensional storage structure manufacturing method, storage structure, memory and electronic equipment | |
| CN102280403A (en) | Method for forming groove with target critical dimension | |
| TW201423909A (en) | Devices, systems, and methods related to forming through-substrate vias with sacrificial plugs | |
| TW201417144A (en) | Semiconductor devices including supporting patterns in gap regions between conductive patterns and methods of fabricating the same | |
| KR20120013614A (en) | Method of Fabricating Semiconductor Device Having Various Isolation Regions | |
| US20210151457A1 (en) | Three-dimensional memory structure, three-dimensional memory device and electronic apparatus | |
| US8343853B2 (en) | Semiconductor wafer, semiconductor device using the same, and method and apparatus for producing the same | |
| US7199473B2 (en) | Integrated low-k hard mask | |
| US11018054B2 (en) | Integrated circuit interconnects | |
| US7877865B2 (en) | Method of forming a wiring having carbon nanotube | |
| US20090176369A1 (en) | Low-h plasma treatment with n2 anneal for electronic memory devices | |
| US11443983B2 (en) | Void-free high aspect ratio metal alloy interconnects and method of manufacture using a solvent-based etchant | |
| CN101740475B (en) | Semiconductor device with dual-mosaic structure and forming method thereof | |
| Yang et al. | Line resistance reduction in advanced copper interconnects | |
| Lee et al. | Impacts of Cu contamination in 3D integration process on memory retention characteristics in thinned DRAM chip | |
| US10886168B2 (en) | Surface modified dielectric refill structure | |
| Agarwal et al. | TSV integration on 20nm logic Si: 3D assembly and reliability results | |
| CN102024790A (en) | Semiconductor device for interconnection process and manufacturing method thereof | |
| US6818548B2 (en) | Fast ramp anneal for hillock suppression in copper-containing structures | |
| US9171755B2 (en) | Methods of manufacturing semiconductor devices including capped metal patterns with air gaps in-between for parasitic capacitance reduction | |
| US11251129B2 (en) | Deposition of graphene on a dielectric surface for next generation interconnects | |
| US11646266B2 (en) | Helmet structures for semiconductor interconnects | |
| CN102136450A (en) | Method for forming metal interconnection | |
| CN100495657C (en) | Method for reducing stress of conductive layer and mask layer and method for making grid |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20130107 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20130107 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
|
| C12 | Rejection of a patent application after its publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20111214 |