CN105097493B - Method for manufacturing semiconductor device - Google Patents
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- CN105097493B CN105097493B CN201410166905.6A CN201410166905A CN105097493B CN 105097493 B CN105097493 B CN 105097493B CN 201410166905 A CN201410166905 A CN 201410166905A CN 105097493 B CN105097493 B CN 105097493B
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Abstract
The invention discloses a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein an internal metal layer is formed on the semiconductor substrate; sequentially forming a first etching stop layer and a second etching stop layer on the semiconductor substrate, wherein the first etching stop layer comprises a diamond-like carbon dielectric layer; forming a top dielectric layer on the second etch stop layer; forming a trench and a via in the top dielectric layer; removing the first etching stop layer and the second etching stop layer at the bottom of the through hole to expose part of the internal metal layer; and forming a top metal layer in the groove and the through hole. The manufacturing process according to the present invention improves the breakdown voltage performance and the time-varying dielectric breakdown (TDDB) performance of the metal layer inside the semiconductor device.
Description
Technical Field
The present invention relates to semiconductor manufacturing processes, and more particularly, to a method of manufacturing a semiconductor device.
Background
As semiconductor manufacturing technology becomes more sophisticated, integrated circuits have also undergone significant changes, and the number of components integrated on the same chip has increased from the first tens, hundreds to the present millions. To meet the requirements of complexity and circuit density, the fabrication process of semiconductor integrated circuit chips utilizes batch processing techniques to form various types of complex devices on a substrate and interconnect them to have complete electronic functionality.
As semiconductor devices are increasingly scaled down in size, the top metal layer of the device structure will affect the performance of the top internal metal, particularly the breakdown voltage and electromigration of the internal metal layer. In the prior art, the PEOX oxide layer provides compressive stress when the metallic copper provides tensile stress. However, the stress provided by the copper metal is greater than the stress provided by the PEOX oxide layer, so the top metal layer will exhibit tensile stress. Currently, increasing the height of the via is commonly used to reduce the effect of copper metal stress on the top metal layer.
Therefore, there is a need for a method of fabricating a semiconductor device to solve the problems of the prior art.
Disclosure of Invention
In this summary, concepts in a simplified form are introduced that are further described in the detailed description. This summary of the invention is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In order to solve the problems in the prior art, the invention provides a method for manufacturing a semiconductor device, which comprises the following steps: providing a semiconductor substrate, wherein an internal metal layer is formed on the semiconductor substrate; sequentially forming a first etching stop layer and a second etching stop layer on the semiconductor substrate, wherein the first etching stop layer comprises a diamond-like carbon dielectric layer; forming a top dielectric layer on the second etch stop layer; forming a trench and a via in the top dielectric layer; removing the first etching stop layer and the second etching stop layer at the bottom of the through hole to expose part of the internal metal layer; and forming a top metal layer in the groove and the through hole.
Preferably, the first etch stop layer is a diamond-like carbon layer.
Preferably, the first etch stop layer has a compressive stress.
Preferably, the first etch stop layer has a compressive stress greater than 6.4G.
Preferably, the first etch stop layer has a thickness greater than 50A and less than 300A.
Preferably, the second etching stop layer is a silicon nitride layer with a thickness of 200A-500A.
Preferably, the top dielectric layer is a PEOX layer.
Preferably, the step of forming trenches and vias in the top dielectric layer comprises: etching the top dielectric layer to form a through hole; filling a sacrificial layer in the through hole; etching and removing part of the top dielectric layer above the internal metal layer to form a groove, wherein the bottom of the groove is flush with the sacrificial layer; and removing the sacrificial layer to expose the second etching stop layer.
Preferably, the method further comprises the step of removing part of the sacrificial layer by etching back after the sacrificial layer is filled in the through hole.
Preferably, a part of the second etching stop layer is etched and removed at the same time of forming the through hole, and the thickness of the remaining second etching stop layer is more than 100 angstroms.
In conclusion, the manufacturing process according to the present invention improves the breakdown voltage performance and the time-varying dielectric breakdown (TDDB) performance of the metal layer inside the semiconductor device.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, there is shown in the drawings,
FIGS. 1A-1G are cross-sectional views of a device resulting from steps of fabricating a top layer internal metal, in accordance with one embodiment of the present invention;
FIG. 2 is a process flow diagram for making the top layer internal metal according to one embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
In order to provide a thorough understanding of the present invention, detailed steps will be set forth in the following description in order to explain how the present invention is problematic in the prior art. It will be apparent that the invention is susceptible to additional embodiments, beyond those specifically described.
It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the invention. As used herein, the singular is intended to include the plural unless the context clearly dictates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Exemplary embodiments according to the present invention will now be described in more detail with reference to the accompanying drawings. These exemplary embodiments may, however, be embodied in many different forms and should not be construed as limited to only the embodiments set forth herein. It is to be understood that these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity, and the same elements are denoted by the same reference numerals, and thus the description thereof will be omitted.
Referring to fig. 1A through 1G, cross-sectional views of various steps of an embodiment according to an aspect of the present invention are shown.
As shown in fig. 1A, a semiconductor substrate (not shown) is provided, on which an interlayer dielectric layer is formed, the semiconductor substrate including a device structure layer 100 formed in the front-end process, such as a metal interconnect structure layer, a copper metal inner layer, etc. Specifically, for example, a wiring layer is formed in the substrate, and the wiring layer is a metal layer to be led out to the surface of the device. Preferably, an inner metal layer 100 is formed on the semiconductor substrate. A first etching stop layer 101 and a second etching stop layer 102 are sequentially formed on the semiconductor substrate, wherein the first etching stop layer 101 includes a diamond-like carbon dielectric layer, in an embodiment of the present invention, the first etching stop layer 101 is a diamond-like carbon layer, the first etching stop layer 101 has a compressive stress greater than 6.4G, and the thickness of the first etching stop layer 101 is 50a to 300 a. The second etch stop layer 102 may comprise a dielectric material, such as a silicon-containing material, a nitrogen-containing material, a carbon-containing material, or the like. The etch stop layer may comprise any of several etch stop materials. Non-limiting examples include semiconductor etch stop materials, and dielectric etch stop materials, and in the present invention the material of the second etch stop layer 102 is preferably silicon nitride with a thickness of 200A-500A. A top dielectric layer 103, preferably a PEOX layer, is then formed on the second etch stop layer 102, the process of forming the top dielectric layer being well known to those skilled in the art and not described in detail herein.
As shown in fig. 1B, the top dielectric layer 103 and the second etch stop layer 102 are etched to form a via 104 in the top dielectric layer 103 and the second etch stop layer 102, in an embodiment of the invention, the via 104 is located directly above an inner copper metal layer on a semiconductor substrate. The semiconductor substrate may be dry etched using conventional dry etching processes such as reactive ion etching, ion beam etching, plasma etching, laser ablation or any combination of these methods. A single etching method may be used, or more than one etching method may be used. The etching gas comprises HBr and Cl2、CH2F2、O2And some additive gases such as nitrogen and argon. The flow range of the etching gas can be 0-150 cubic centimeters per minute (sccm), the pressure in the reaction chamber can be 3-50 millitorr (mTorr), and plasma etching is carried out under the condition that the radio frequency power is 600W-1500W. Wherein, after the etching to form the via hole 104, the thickness of the remaining second etching stop layer 102 is greater than 100 angstroms.
Next, as shown in fig. 1C, the via hole 104 is filled with a bottom anti-reflective coating (BARC) as a sacrificial layer, and the top of the bottom anti-reflective coating is flush with the top of the top dielectric layer 103. The material of the bottom anti-reflection coating is organic material.
The etch back removes a portion of the BARC layer to form the BARC layer 105, the BARC layer 105 having a top that is lower than a top of the top dielectric layer 103.
The etch back step may be performed using either a dry etch or a wet etch. The dry etching method can employ an anisotropic etching method based on a carbon fluoride gas. The wet etching process can employ a hydrofluoric acid solution, such as a buffered oxide etchant or a hydrofluoric acid buffer solution.
Using a dry etching process, e.g. with Sulfur Fluoride (SF)6) Nitrogen and chlorine as an etchant and having a high selectivity to an oxide layer, an etch-back process. Conventional dry etching processes such as reactive ion etching, ion beam etching, plasma etching, laser ablation or any combination of these methods. A single etching method may be used, or more than one etching method may be used.
In a specific embodiment of the present invention, plasma etching is used, and the etching gas may be a nitrogen-based gas. Specifically, lower rf power is used and a low pressure and high density plasma gas can be generated. The adopted etching gas is a gas based on fluorine, and the flow of the etching gas is as follows: 100-200 cubic centimeters per minute (sccm); the pressure in the reaction chamber can be 30-50 mTorr, the etching time is 10-15 seconds, the power is 50-100W, and the bias power is 0W.
Next, as shown in fig. 1D, the top dielectric layer on the upper portion of the inner copper metal layer is etched and removed by using a photolithography process to form a trench, so that the top of the top dielectric layer remaining after etching is flush with the top of the bottom anti-reflective coating 105, and the bottom of the trench is flush with the bottom anti-reflective coating 105. Specifically, a patterned photoresist layer is formed on the semiconductor substrate by a photolithography process, the patterned photoresist layer exposes the top dielectric layer 103 above the internal copper metal layer, and the top dielectric layer 103 is etched according to the patterned photoresist layer. Dry etching, such as plasma etching, may be used, with etching gases including boron chloride, chlorine, and some additive gases such as nitrogen, argon. The flow rate of the boron chloride and the chlorine can be in the range of 0-150 cubic centimeters per minute (sccm) and 50-200 cubic centimeters per minute (sccm), and the pressure in the reaction chamber can be in the range of 5-20 millitorr (mTorr). And removing the patterned photoresist layer. Then, the BARC layer 105 on the second etch stop layer 102 is removed to expose the remaining second etch stop layer 102. Finally, trenches and vias are formed in the top dielectric layer 103. As shown in fig. 1E.
Next, as shown in fig. 1F, the remaining second etch stop layer 102 and the first etch stop layer 101 are continuously etched to expose a portion of the internal metal layer, forming a trench and a via 106. The remaining second etch stop layer 102 and first etch stop layer may be dry etched to form trenches and vias 106 using conventional dry etch processes such as reactive ion etching, ion beam etching, plasma etching, laser ablation, or any combination of these methods. A single etching method may be used, or more than one etching method may be used.
Then, as shown in fig. 1G, a top metal layer 107 is formed in the trench and the via 106 on the semiconductor substrate, the material of the top metal layer 107 is preferably copper, specifically, the top metal layer 107 covers the exposed inner metal layer, the etched top dielectric layer, and the top metal layer 107 is flush with the top of the un-etched top dielectric layer.
In one embodiment of the present invention, the copper seed layer may be formed by Physical Vapor Deposition (PVD). For example, a copper metal layer is formed on an already formed copper seed layer using an electrochemical plating method, and a stable plating process can be maintained by an in-line analysis of water bath composition and replenishment of organic and inorganic substances.
Fig. 2 is a process flow diagram for making the top layer internal metal according to one embodiment of the present invention, for schematically illustrating the flow of the entire manufacturing process.
In step 201, providing a semiconductor substrate with an internal metal layer, and sequentially forming a first etching stop layer, a second etching stop layer and a top dielectric layer on the semiconductor substrate;
in step 202, etching the top dielectric layer and the second etch stop layer to form a via and a trench;
in step 203, forming a sacrificial layer on the remaining second etching stop layer to fill the through hole and the trench, and etching back to remove part of the sacrificial layer;
in step 204, etching to remove part of the top dielectric layer above the inner metal layer;
in step 205, removing the remaining sacrificial layer to expose the second etch stop layer;
in step 206, the exposed second etching stop layer and the first etching stop layer thereunder are etched continuously to expose the internal metal layer;
in step 207, a top metal layer is formed on the semiconductor substrate, the top metal layer being flush with the top of the un-etched top dielectric.
In conclusion, the manufacturing process improves the breakdown voltage performance and the time-varying insulation dielectric breakdown performance of the metal layer inside the semiconductor device.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the above-described embodiments, and that various changes and modifications may be made in accordance with the present invention within the scope of the invention as hereinafter claimed. The scope of the invention is defined by the appended claims and equivalents thereof.
Claims (8)
1. A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate, wherein an internal metal layer is formed on the semiconductor substrate;
sequentially forming a first etching stop layer and a second etching stop layer on the semiconductor substrate, wherein the first etching stop layer comprises a diamond-like carbon dielectric layer and has a compressive stress of more than 6.4 GPa;
forming a top dielectric layer on the second etch stop layer;
forming a trench and a via in the top dielectric layer;
removing the first etching stop layer and the second etching stop layer at the bottom of the through hole to expose part of the internal metal layer;
and forming a top metal layer in the groove and the through hole to cover the exposed inner metal layer.
2. The method of claim 1, wherein the first etch stop layer is a diamond-like carbon layer.
3. The method of claim 1, wherein the first etch stop layer has a thickness greater than 50A and less than 300A.
4. The method of claim 1, wherein the second etch stop layer is a silicon nitride layer having a thickness of 200A-500A.
5. The method of claim 1, wherein the top dielectric layer is a PEOX layer.
6. The method of claim 1, wherein the step of forming trenches and vias in the top dielectric layer comprises: etching the top dielectric layer to form a through hole; filling a sacrificial layer in the through hole; etching and removing part of the top dielectric layer above the internal metal layer to form a groove, wherein the bottom of the groove is flush with the sacrificial layer; and removing the sacrificial layer to expose the second etching stop layer.
7. The method of claim 6, further comprising the step of etching back to remove a portion of the sacrificial layer after filling the sacrificial layer in the via.
8. The method of claim 6, wherein etching removes a portion of the second etch stop layer while forming the via, the remaining second etch stop layer having a thickness greater than 100 angstroms.
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| CN201410166905.6A CN105097493B (en) | 2014-04-24 | 2014-04-24 | Method for manufacturing semiconductor device |
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| CN105097493B true CN105097493B (en) | 2020-09-08 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070218679A1 (en) * | 2006-03-20 | 2007-09-20 | Applied Materials, Inc. | Organic BARC etch process capable of use in the formation of low k dual damascene integrated circuits |
| CN102280403A (en) * | 2010-06-13 | 2011-12-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove with target critical dimension |
| CN102403263A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Trench etching method in double Damascus structure |
| CN103681844A (en) * | 2012-09-17 | 2014-03-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102004042168B4 (en) * | 2004-08-31 | 2009-08-20 | Advanced Micro Devices, Inc., Sunnyvale | Semiconductor element having a small-ε metallization layer stack with enhanced electromigration resistance and method of forming the semiconductor element |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070218679A1 (en) * | 2006-03-20 | 2007-09-20 | Applied Materials, Inc. | Organic BARC etch process capable of use in the formation of low k dual damascene integrated circuits |
| CN102280403A (en) * | 2010-06-13 | 2011-12-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming groove with target critical dimension |
| CN102403263A (en) * | 2010-09-17 | 2012-04-04 | 中芯国际集成电路制造(上海)有限公司 | Trench etching method in double Damascus structure |
| CN103681844A (en) * | 2012-09-17 | 2014-03-26 | 中国科学院微电子研究所 | Semiconductor device and manufacturing method thereof |
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