CN113484602B - Ultra-low power consumption programmable power supply voltage detection circuit - Google Patents
Ultra-low power consumption programmable power supply voltage detection circuit Download PDFInfo
- Publication number
- CN113484602B CN113484602B CN202110836223.1A CN202110836223A CN113484602B CN 113484602 B CN113484602 B CN 113484602B CN 202110836223 A CN202110836223 A CN 202110836223A CN 113484602 B CN113484602 B CN 113484602B
- Authority
- CN
- China
- Prior art keywords
- port
- power supply
- supply voltage
- ultra
- power consumption
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 34
- 239000003990 capacitor Substances 0.000 claims description 46
- 238000010586 diagram Methods 0.000 description 9
- 230000014759 maintenance of location Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
- G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/40—Testing power supplies
Abstract
The invention belongs to the technical field of power supply voltage detection in integrated circuits, and discloses an ultra-low power consumption programmable power supply voltage detection circuit which comprises a power supply voltage dividing circuit, a threshold voltage generating circuit, a comparator and an ultra-low power consumption oscillator, wherein the power supply voltage dividing circuit receives a power supply voltage Vdd and a control clock generated by the ultra-low power consumption oscillator and outputs a divided signal Vdiv. The threshold voltage generating circuit receives a control clock and a programming selection input Sel [ n:0] generated by the ultra-low power consumption oscillator, and outputs a threshold voltage Vth. The comparator receives the divided voltage signal Vdiv and the threshold voltage Vth, and outputs an indication signal Vpvd. The ultra-low power consumption oscillator generates control clocks required by the power supply voltage dividing circuit and the threshold voltage generating circuit. The ultra-low power consumption programmable power supply voltage detection circuit has small average power consumption, and the used devices such as resistors and the like do not need to be large. The chip area is reduced, and the cost is reduced.
Description
Technical Field
The invention belongs to the technical field of power supply voltage detection in integrated circuits, and particularly relates to an ultra-low power consumption programmable power supply voltage detection circuit.
Background
A power supply voltage detection circuit is typically included in an integrated circuit to indicate the level of the power supply voltage. When the power supply voltage is lower than a threshold value preset in the power supply voltage detection circuit, the power supply voltage detection circuit changes the indication signal to inform the system so as to run the necessary program. The supply voltage detection circuit is usually provided with programmable features to adapt to different application scenarios. The power supply voltage detection circuit should also have as low power consumption as possible to extend the service life of the battery as possible in portable electronic products that are increasingly used.
The conventional power supply voltage detection circuit uses a resistor voltage division, a reference voltage generation circuit and a comparator, and generally consumes large power consumption. A known supply voltage detection circuit is shown in fig. 1 and comprises a resistor divider, a reference voltage generation circuit and a comparator. The resistor voltage divider comprises a series of resistors and related switch selection circuits, one end of each resistor series is connected with a power supply voltage Vdd, and the other end of each resistor series is connected with the ground; the programming selection input Sel [ n:0] is connected to the resistor voltage divider, and outputs one node in the resistor string through the switch selection circuit; the output Vdiv of the resistive divider is connected to a first input of the comparator. The reference voltage generating circuit outputs a reference voltage Vref, which is connected to the second input of the comparator. The comparator compares the output Vdiv of the resistor divider with the reference voltage Vref, and outputs a power supply voltage indication signal Vpvd. The resistor divider and reference voltage generation circuit of such a power supply voltage detection circuit generally consumes a large power consumption. If the power consumption of the two circuits is to be reduced, larger resistors are usually required, which occupy larger chip area and increase the cost of the product.
Disclosure of Invention
The invention aims to provide an ultra-low power consumption programmable power supply voltage detection circuit, which aims to solve the technical problems that the resistance voltage division and reference voltage generation circuit of the existing power supply voltage detection circuit have large power consumption.
In order to solve the technical problems, the specific technical scheme of the ultra-low power consumption programmable power supply voltage detection circuit is as follows:
The utility model provides an ultra-low power consumption programmable power supply voltage detection circuit, includes a power supply voltage bleeder circuit, a threshold voltage generating circuit, a comparator and an ultra-low power consumption oscillator, power supply voltage bleeder circuit receive power supply voltage Vdd and ultra-low power consumption oscillator produced control clock, output bleeder signal Vdiv. The threshold voltage generating circuit receives a control clock generated by an ultralow-power-consumption oscillator and a programming selection input Sel [ n:0] and outputs a threshold voltage Vth. The comparator receives the divided voltage signal Vdiv and the threshold voltage Vth, and outputs an indication signal Vpvd. The ultra-low power consumption oscillator generates control clocks required by a power voltage dividing circuit and a threshold voltage generating circuit.
Further, the power supply voltage dividing circuit is composed of two resistors, two capacitors and two switches; the first port of the first resistor R1 is connected with the power supply voltage Vdd, and the second port is connected with the first port of the second resistor R2; a second port of the second resistor R2 is connected with a first port of the second switch S2, a second port of the second switch S2 is connected with ground, and a third port of the second switch S2 is connected with the control clock PC; the first port of the first capacitor C1 is connected with the power supply voltage Vdd, and the second port of the first capacitor C2 is connected with the first port of the second capacitor; the second port of the second capacitor C2 is connected with the ground; the first port of the first switch S1 is connected to the second port of the first resistor R1, the second port of the first switch S1 is connected to the second port of the first capacitor C1, and the third port of the first switch S1 is connected to the control clock PF.
Further, when the control clock PC is at a high level, the second switch S2 is turned on, and the power supply voltage Vdd is divided by the first resistor R1 and the second resistor R2 to generate a divided output Vdivr.
Further, when the control clock PF is at a high level, the first switch S1 is turned on, and the resistor voltage division output Vdivr is equal to the output Vdiv of the power supply voltage division circuit; when the control clock PF is at a low level, the first switch S1 is turned off, and the charge dividing node Vdiv is still equal to Vdivr due to the charge retention on the capacitor, and the capacitor dividing node Vdiv can still maintain the division of the power supply voltage Vdd according to the proportional relationship between the resistor and the capacitor.
Further, the threshold voltage generating circuit comprises a reference voltage generating circuit, an amplifier, a resistor voltage divider, a switch and a capacitor, wherein the reference voltage generating circuit receives a control clock PC and generates a reference voltage Vref, the reference voltage Vref is connected to a first port of the amplifier, a second port of the amplifier is connected to a third port of the resistor voltage divider, the third port of the amplifier is connected to the first port of the resistor voltage divider, and a fourth port of the amplifier is connected to the control clock PC; the second port of the resistor voltage division is connected to the ground, and the fourth port is connected with the voltage division selection input Sel [ n:0]; the first port of the switch S3 is connected with the third port of the amplifier, the second port of the switch S3 is connected with the first port of the capacitor C3, and the third port of the switch S3 is connected with the control clock PF; the first port of the capacitor C3 is the output Vth of the threshold voltage generating circuit, and the second port of the capacitor C3 is connected to ground.
Further, the amplifier and the resistor voltage division form a voltage amplifying circuit for amplifying the reference voltage Vref generated by the reference voltage generating circuit; the partial pressure selects Sel [ n:0] to select the magnification factor, and the programmable function is realized.
Further, when the control clock PF is at a high level, the switch S3 is turned on, the voltage generated by the amplifier is charged to the capacitor C3 through the switch S3, and when the control clock PF is at a low level, the switch S3 is turned off, and the voltage generated by the previous amplifier is maintained as the threshold voltage Vth in the capacitor C3.
Further, a first port of the comparator is connected with the divided voltage output Vdiv of the power voltage dividing circuit, a second port of the comparator is connected with the threshold voltage Vth of the threshold voltage generating circuit, and a third port of the comparator outputs a comparison result signal as an indication signal Vpvd of power voltage detection; hysteresis is included in the comparator.
Further, the ultra-low power consumption oscillator generates control clocks PC and PF, which generate high level at fixed time, and maintain the time tc and tf, and the rest time is low level.
Further, the on time of the control clock PC is earlier than the on time of the control clock PF, when the control clock PF is turned on, the resistor voltage divider Vdivr, the reference voltage Vref, and the amplifier output voltage Vop are stable, the resistor voltage divider Vdivr refreshes the voltage division output Vdiv through the switch S1, and the amplifier output Vop refreshes the threshold voltage Vth through the switch S3; when the control clock PF is at a low level, the capacitors C1 and C2 maintain the divided voltage output Vdiv, and the capacitor C3 maintains the threshold voltage Vth, and when the switches S1 and S3 of low leakage are used, the divided voltage output Vdiv and the threshold voltage Vth can be maintained stable.
The ultra-low power consumption programmable power supply voltage detection circuit has the following advantages:
The control clocks PC and PF of the ultra-low power consumption programmable power supply voltage detection circuit are only at high level in a short time, and the other control clocks PC and PF are at low level in most of the time, so that the resistor voltage division branch circuit, the reference voltage generation circuit and the amplifier are only turned on in a short time, and the circuits are turned off in most of the time, so that the average power consumption of the circuits is small, and devices such as resistors used in the circuits are not required to be large. The chip area is reduced, and the cost is reduced.
Drawings
Fig. 1 is a conventional power supply voltage detection circuit diagram.
FIG. 2 is a schematic diagram of an ultra-low power programmable supply voltage detection circuit of the present invention.
FIG. 3 is a detailed schematic diagram of the ultra-low power programmable supply voltage detection circuit of the present invention.
Fig. 4 is a schematic diagram of an oscillator output clock of the ultra-low power programmable supply voltage detection circuit of the present invention.
FIG. 5 is a schematic diagram of one embodiment of a resistive divider circuit of an ultra low power programmable supply voltage detection circuit of the present invention.
Detailed Description
In order to better understand the purpose, structure and function of the present invention, the following describes in detail an ultra-low power consumption programmable power supply voltage detection circuit according to the present invention with reference to the accompanying drawings.
As shown in fig. 2, the ultra-low power consumption programmable power supply voltage detection circuit of the present invention includes a power supply voltage dividing circuit, a threshold voltage generating circuit, a comparator and an ultra-low power consumption oscillator. The power supply voltage dividing circuit receives the power supply voltage Vdd and a control clock generated by the ultra-low power consumption oscillator, and outputs a divided signal Vdiv. The threshold voltage generating circuit receives a control clock generated by an ultralow-power-consumption oscillator and a programming selection input Sel [ n:0] and outputs a threshold voltage Vth. The comparator receives the divided voltage signal Vdiv and the threshold voltage Vth, and outputs an indication signal Vpvd. The ultra-low power consumption oscillator generates control clocks required by a power voltage dividing circuit and a threshold voltage generating circuit.
FIG. 3 is a detailed schematic diagram of the present invention, wherein the power supply voltage dividing circuit is composed of two resistors, two capacitors and two switches; the first port of the first resistor R1 is connected with the power supply voltage Vdd, and the second port is connected with the first port of the second resistor R2; a second port of the second resistor R2 is connected with a first port of the second switch S2, a second port of the second switch S2 is connected with ground, and a third port of the second switch S2 is connected with the control clock PC; the first port of the first capacitor C1 is connected with the power supply voltage Vdd, and the second port of the first capacitor C2 is connected with the first port of the second capacitor; the second port of the second capacitor C2 is connected with the ground; the first port of the first switch S1 is connected to the second port of the first resistor R1, the second port of the first switch S1 is connected to the second port of the first capacitor C1, and the third port of the first switch S1 is connected to the control clock PF.
When the control clock PC is at a high level, the second switch S2 is turned on, and the power supply voltage Vdd is divided by the first resistor R1 and the second resistor R2 to generate a divided output Vdivr; the on-resistance of the second switch S2 is far smaller than the resistance of the first resistor R1 and the second resistor R2, and is negligible, so the divided voltage output is:
the capacitance values of the first capacitor C1 and the second capacitor C2 are set as follows:
When the control clock PF is at a high level, the first switch S1 is turned on, and the resistor voltage division output Vdivr is equal to the output Vdiv of the power supply voltage division circuit; when the control clock PF is at low level, the first switch S1 is turned off, the charge dividing node Vdiv is still equal to Vdivr due to the charge retention on the capacitor, and the capacitor dividing node Vdiv can still maintain the relationship of equation (1) according to the ratio of resistor to capacitor (2).
The threshold voltage generating circuit comprises a reference voltage generating circuit, an amplifier, a resistor divider, a switch and a capacitor. The reference voltage generating circuit receives the control clock PC and generates reference voltage Vref, the reference voltage Vref is connected to a first port of the amplifier, a second port of the amplifier is connected to a third port of resistor voltage division, the third port of the amplifier is connected to the first port of resistor voltage division, and a fourth port of the amplifier is connected to the control clock PC; the second port of the resistor voltage division is connected to the ground, and the fourth port is connected with the voltage division selection input Sel [ n:0]; the first port of the switch S3 is connected with the third port of the amplifier, the second port of the switch S3 is connected with the first port of the capacitor C3, and the third port of the switch S3 is connected with the control clock PF; the first port of the capacitor C3 is the output Vth of the threshold voltage generating circuit, and the second port of the capacitor C3 is connected to ground.
The amplifier and the resistor voltage division form a voltage amplifying circuit for amplifying the reference voltage Vref generated by the reference voltage generating circuit; the partial pressure selects Sel [ n:0] to select the magnification factor, and the programmable function is realized. When the control clock PF is at a high level, the switch S3 is turned on, the voltage generated by the amplifier is charged to the capacitor C3 through the switch S3, and when the control clock PF is at a low level, the switch S3 is turned off, and the voltage generated by the previous amplifier is held as the threshold voltage Vth in the capacitor C3.
The first port of the comparator is connected with the divided voltage output Vdiv of the power voltage dividing circuit, the second port of the comparator is connected with the threshold voltage Vth of the threshold voltage generating circuit, and the third port of the comparator outputs a comparison result signal as an indication signal Vpvd for power voltage detection; hysteresis is included in the comparator to filter the noise disturbance.
FIG. 4 is a block diagram of an ultra-low power oscillator and a timing diagram of a generated control clock, wherein the ultra-low power oscillator generates control clocks PC and PF, the control clocks PC and PF are timed to generate high levels, the sustain times tc and tf are maintained, and the rest of the time is low level. The control clock PC controls a resistor voltage dividing branch of the power supply voltage dividing circuit, a reference voltage generating circuit and an amplifier in the threshold voltage generating circuit, when the control clock PC is in a high level, the controlled circuit is in an on state, and when the control clock PC is in a low level, the controlled circuit is in an off state; the control clock PF controls the first switch S1 in the power supply voltage dividing circuit and the switch S3 of the threshold voltage generating circuit, and when the control clock PF is at a high level, the controlled switch is in an on state, and when the control clock PF is at a low level, the controlled switch is in an off state. The turn-on time of the control clock PC is earlier than the turn-on time of the control clock PF so as to turn on the resistor-dividing branch of the power supply voltage dividing circuit, the reference voltage generating circuit of the threshold voltage generating circuit, and the amplifier in advance, and when the control clock PF is turned on, the resistor-dividing circuit Vdivr, the reference voltage Vref, and the amplifier output voltage Vop are stable, the resistor-dividing circuit Vdivr refreshes the divided output Vdiv through the switch S1, and the amplifier output Vop refreshes the threshold voltage Vth through the switch S3. When the control clock PF is at a low level, the capacitors C1 and C2 maintain the divided voltage output Vdiv, and the capacitor C3 maintains the threshold voltage Vth, and when the switches S1 and S3 with low leakage are used, the divided voltage output Vdiv and the threshold voltage Vth can be maintained for a long time without a large change.
The control clocks PC and PF are high only for a short time and the other is low for most of the time, so that the resistor divider branch, the reference voltage generating circuit and the amplifier are turned on only for a short time, and the other is turned off for most of the time, so that the average power consumption of these circuits is small, so that the power consumption of these circuits is not required to be small, so that the devices such as the resistor used therein are not required to be large.
Fig. 5 is a diagram of an embodiment of the resistor divider of the present invention, including a decoding circuit, resistor string, and switching circuit. This embodiment takes two-bit program select inputs Sel [1:0] as an example. The decoding circuit comprises a group of gates for converting two-bit programming selection inputs Sel [1:0] into four-bit switch control signals SW 3-SW 0, and the conversion relationship is as follows:
| Sel[1] | Sel[0] | SW3 | SW2 | SW1 | SW0 |
| 1 | 1 | 1 | 0 | 0 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 | 0 | 1 |
in the table, 1 represents a high level, and 0 represents a low level.
The resistor string includes 5 resistors connected in series, a first port of the resistor string is connected to a third port Vop of the amplifier, second to fifth ports of the resistor string are connected to first ports of the first to fourth switches (S4 to S7), respectively, and a sixth port of the resistor string is connected to ground. The second ports of the first to fourth switches (S4 to S7) are connected together as the output Vo of the resistor divider, and the third ports of the first to fourth switches (S4 to S7) are connected with the switch control signals SW0 to SW3, respectively. When the switch control signals SW0 to SW3 are at high level, the switches are in on state, and the nodes of the corresponding resistor strings are connected to the resistor voltage division output Vo.
It will be understood that the application has been described in terms of several embodiments, and that various changes and equivalents may be made to these features and embodiments by those skilled in the art without departing from the spirit and scope of the application. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the application without departing from the essential scope thereof. Therefore, it is intended that the application not be limited to the particular embodiment disclosed, but that the application will include all embodiments falling within the scope of the appended claims.
Claims (3)
1. The ultra-low power consumption programmable power supply voltage detection circuit comprises a power supply voltage dividing circuit, a threshold voltage generating circuit, a comparator and an ultra-low power consumption oscillator, and is characterized in that the power supply voltage dividing circuit receives a power supply voltage Vdd and a control clock generated by the ultra-low power consumption oscillator, outputs a divided voltage signal Vdiv, the threshold voltage generating circuit receives the control clock generated by the ultra-low power consumption oscillator and a programming selection input Sel [ n:0], outputs a threshold voltage Vth, the comparator receives the divided voltage signal Vdiv and the threshold voltage Vth, outputs an indication signal Vpvd, and the ultra-low power consumption oscillator generates the control clocks required by the power supply voltage dividing circuit and the threshold voltage generating circuit; the power supply voltage dividing circuit consists of two resistors, two capacitors and two switches; the first port of the first resistor R1 is connected with the power supply voltage Vdd, and the second port is connected with the first port of the second resistor R2; a second port of the second resistor R2 is connected with a first port of the second switch S2, a second port of the second switch S2 is connected with ground, and a third port of the second switch S2 is connected with the control clock PC; the first port of the first capacitor C1 is connected with the power supply voltage Vdd, and the second port of the first capacitor C2 is connected with the first port of the second capacitor; the second port of the second capacitor C2 is connected with the ground; a first port of the first switch S1 is connected with a second port of the first resistor R1, a second port of the first switch S1 is connected with a second port of the first capacitor C1, and a third port of the first switch S1 is connected with the control clock PF; the threshold voltage generating circuit comprises a reference voltage generating circuit, an amplifier, a resistor voltage divider, a switch and a capacitor, wherein the reference voltage generating circuit receives a control clock PC and generates a reference voltage Vref, the reference voltage Vref is connected to a first port of the amplifier, a second port of the amplifier is connected to a third port of the resistor voltage divider, the third port of the amplifier is connected to the first port of the resistor voltage divider, and a fourth port of the amplifier is connected to the control clock PC; the second port of the resistor voltage division is connected to the ground, and the fourth port is connected with the voltage division selection input Sel [ n:0]; the first port of the switch S3 is connected with the third port of the amplifier, the second port of the switch S3 is connected with the first port of the capacitor C3, and the third port of the switch S3 is connected with the control clock PF; the first port of the capacitor C3 is the output Vth of the threshold voltage generating circuit, and the second port of the capacitor C3 is connected to the ground; the ultra-low power consumption oscillator generates control clocks PC and PF, the control clocks PC and PF generate high level at fixed time, the time tc and tf are maintained, and the rest time is low level.
2. The ultra-low power consumption programmable power supply voltage detection circuit according to claim 1, wherein the amplifier and the resistor voltage divider form a voltage amplifying circuit for amplifying the reference voltage Vref generated by the reference voltage generating circuit; the partial pressure selects Sel [ n:0] to select the magnification factor, and the programmable function is realized.
3. The ultra-low power consumption programmable power supply voltage detection circuit according to claim 1, wherein a first port of the comparator is connected to the divided voltage output Vdiv of the power supply voltage dividing circuit, a second port is connected to the threshold voltage Vth of the threshold voltage generating circuit, and a third port outputs a comparison result signal as an indication signal Vpvd of the power supply voltage detection; hysteresis is included in the comparator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110836223.1A CN113484602B (en) | 2021-08-20 | 2021-08-20 | Ultra-low power consumption programmable power supply voltage detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110836223.1A CN113484602B (en) | 2021-08-20 | 2021-08-20 | Ultra-low power consumption programmable power supply voltage detection circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113484602A CN113484602A (en) | 2021-10-08 |
| CN113484602B true CN113484602B (en) | 2024-04-30 |
Family
ID=77943341
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110836223.1A Active CN113484602B (en) | 2021-08-20 | 2021-08-20 | Ultra-low power consumption programmable power supply voltage detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113484602B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114019884A (en) * | 2021-11-16 | 2022-02-08 | Tcl家用电器（合肥）有限公司 | Household appliance power consumption control circuit and household appliance |
| CN114296503B (en) * | 2021-12-30 | 2023-04-18 | 杭州朔天科技有限公司 | Ultra-low power consumption programmable low dropout linear voltage regulator circuit |
Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001077688A (en) * | 1999-09-06 | 2001-03-23 | Toyo Commun Equip Co Ltd | Digital processing phase lock loop circuit |
| KR20060075831A (en) * | 2004-12-29 | 2006-07-04 | 주식회사 하이닉스반도체 | Regulation circuit |
| CN101478234A (en) * | 2009-01-13 | 2009-07-08 | 浙江大学 | Switching capacitor type DC-DC converter |
| CN102122943A (en) * | 2010-12-29 | 2011-07-13 | 山东华芯半导体有限公司 | Low-power consumption time delay programmable power-on resetting method and circuit |
| CN103296880A (en) * | 2013-05-21 | 2013-09-11 | 西安电子科技大学 | Low-power-consumption boost DC-DC converter started at ultralow voltage |
| CN103389771A (en) * | 2013-07-26 | 2013-11-13 | 上海宏力半导体制造有限公司 | Low power consumption voltage regulator circuit |
| JP2015056781A (en) * | 2013-09-12 | 2015-03-23 | ローム株式会社 | Output circuit, circuit for driving output transistor, and electronic apparatus |
| CN107276587A (en) * | 2017-08-16 | 2017-10-20 | 电子科技大学 | A kind of pierce circuit with external sync function |
| CN107294376A (en) * | 2016-03-30 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Charge pump regulator and memory, internet of things equipment |
| JP2017200115A (en) * | 2016-04-28 | 2017-11-02 | ローム株式会社 | Automatic adjustment oscillator and switching power supply using the same |
| US9973081B1 (en) * | 2017-08-17 | 2018-05-15 | Qualcomm Incorporated | Low-power low-duty-cycle switched-capacitor voltage divider |
| CN108399930A (en) * | 2018-02-12 | 2018-08-14 | 宁波宇喆电子科技有限公司 | A kind of low-power consumption programming high voltage generation circuit |
| JP2019110521A (en) * | 2017-12-15 | 2019-07-04 | ローム株式会社 | Switch device |
| CN209105196U (en) * | 2018-09-27 | 2019-07-12 | 深圳市傲科光电子有限公司 | A kind of low power consuming clock data recovery circuit and receiver |
| CN111277249A (en) * | 2020-01-22 | 2020-06-12 | 上海芯凌微电子有限公司 | Low-power-consumption relaxation oscillator circuit |
| CN211698123U (en) * | 2019-12-12 | 2020-10-16 | 广州大彩光电科技有限公司 | Power supply monitoring device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9647670B2 (en) * | 2015-09-15 | 2017-05-09 | Silicon Laboratories Inc. | Oscillator with dynamic gain control |
-
2021
- 2021-08-20 CN CN202110836223.1A patent/CN113484602B/en active Active
Patent Citations (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001077688A (en) * | 1999-09-06 | 2001-03-23 | Toyo Commun Equip Co Ltd | Digital processing phase lock loop circuit |
| KR20060075831A (en) * | 2004-12-29 | 2006-07-04 | 주식회사 하이닉스반도체 | Regulation circuit |
| CN101478234A (en) * | 2009-01-13 | 2009-07-08 | 浙江大学 | Switching capacitor type DC-DC converter |
| CN102122943A (en) * | 2010-12-29 | 2011-07-13 | 山东华芯半导体有限公司 | Low-power consumption time delay programmable power-on resetting method and circuit |
| CN103296880A (en) * | 2013-05-21 | 2013-09-11 | 西安电子科技大学 | Low-power-consumption boost DC-DC converter started at ultralow voltage |
| CN103389771A (en) * | 2013-07-26 | 2013-11-13 | 上海宏力半导体制造有限公司 | Low power consumption voltage regulator circuit |
| JP2015056781A (en) * | 2013-09-12 | 2015-03-23 | ローム株式会社 | Output circuit, circuit for driving output transistor, and electronic apparatus |
| CN107294376A (en) * | 2016-03-30 | 2017-10-24 | 中芯国际集成电路制造(上海)有限公司 | Charge pump regulator and memory, internet of things equipment |
| JP2017200115A (en) * | 2016-04-28 | 2017-11-02 | ローム株式会社 | Automatic adjustment oscillator and switching power supply using the same |
| CN107276587A (en) * | 2017-08-16 | 2017-10-20 | 电子科技大学 | A kind of pierce circuit with external sync function |
| US9973081B1 (en) * | 2017-08-17 | 2018-05-15 | Qualcomm Incorporated | Low-power low-duty-cycle switched-capacitor voltage divider |
| JP2019110521A (en) * | 2017-12-15 | 2019-07-04 | ローム株式会社 | Switch device |
| CN108399930A (en) * | 2018-02-12 | 2018-08-14 | 宁波宇喆电子科技有限公司 | A kind of low-power consumption programming high voltage generation circuit |
| CN209105196U (en) * | 2018-09-27 | 2019-07-12 | 深圳市傲科光电子有限公司 | A kind of low power consuming clock data recovery circuit and receiver |
| CN211698123U (en) * | 2019-12-12 | 2020-10-16 | 广州大彩光电科技有限公司 | Power supply monitoring device |
| CN111277249A (en) * | 2020-01-22 | 2020-06-12 | 上海芯凌微电子有限公司 | Low-power-consumption relaxation oscillator circuit |
Non-Patent Citations (3)
| Title |
|---|
| A low-power-consumption, supply-noise-insensitive charge pump PLL with a voltage regulator for on-chip clock generating in MAPS at STAR experiment;Quan Sun等;《2008 IEEE Nuclear Science Symposium Conference Record》;全文 * |
| 一种低功耗的电子式电能表电源监控芯片;吴海强等;《现代电子技术》(第14期);全文 * |
| 一种电力专用SOC 的低功耗小面积ADPLL设计;陶伟等;《半导体技术》;第46卷(第4期);全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113484602A (en) | 2021-10-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113484602B (en) | Ultra-low power consumption programmable power supply voltage detection circuit | |
| KR100300077B1 (en) | Charge pump circuit having adaptive oscillation period | |
| CN100543631C (en) | Constant voltage outputting circuit | |
| CN105281726B (en) | A kind of electrification reset circuit | |
| CN106774575B (en) | A kind of low pressure difference linear voltage regulator | |
| CN107317568B (en) | Oscillator for eliminating offset voltage of comparator | |
| CN102832915A (en) | Programmable power-on reset system | |
| CN112947662A (en) | Low-power consumption LDO circuit based on comparator | |
| US8536909B1 (en) | Power good signal generating circuit | |
| CN115622548B (en) | High-side NMOS floating drive circuit | |
| US20090051331A1 (en) | Method and Circuit for Controlling the Refresh Rate of Sampled Reference Voltages | |
| CN103823494B (en) | The timer circuit related to temperature | |
| US11043893B1 (en) | Bias regulation system | |
| US20210041984A1 (en) | Positive and negative voltage driving circuit, chip, active stylus and driving method | |
| CN209841222U (en) | CMOS temperature sensor circuit | |
| CN103475212A (en) | Voltage pumping circuit for pumping an input voltage to generate an output voltage | |
| CN115421552B (en) | Dynamic bias low-power-consumption integrator serving as floating voltage source based on capacitor | |
| CN112104226B (en) | Wide-voltage low-power consumption strong-driving-capability pump circuit and nonvolatile memory | |
| CN108111150B (en) | Power-on reset circuit, integrated circuit and EEPROM system | |
| CN208226983U (en) | The multiplex circuit of LDO and POR | |
| CN112684843B (en) | Digital-analog hybrid linear voltage regulator system | |
| US6683505B2 (en) | High speed voltage controlled oscillator | |
| Ji et al. | A Fully-Digital LDO with Adaptive Clock and Double-Edge-Triggered Shift Register for Quick Response | |
| CN108776501B (en) | Multiplexing circuit of LDO and POR | |
| JPS617724A (en) | Bootstrap type inverter circuit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |