CN113479841B - Silicon-based micro-channel substrate preparation method - Google Patents

Silicon-based micro-channel substrate preparation method Download PDF

Info

Publication number
CN113479841B
CN113479841B CN202110563714.3A CN202110563714A CN113479841B CN 113479841 B CN113479841 B CN 113479841B CN 202110563714 A CN202110563714 A CN 202110563714A CN 113479841 B CN113479841 B CN 113479841B
Authority
CN
China
Prior art keywords
silicon
micro
parallel
copper
preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110563714.3A
Other languages
Chinese (zh)
Other versions
CN113479841A (en
Inventor
禹淼
吴杰
王政焱
王勇光
刘欣
李�杰
陈聪
朱健
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CETC 55 Research Institute
Original Assignee
CETC 55 Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CETC 55 Research Institute filed Critical CETC 55 Research Institute
Priority to CN202110563714.3A priority Critical patent/CN113479841B/en
Publication of CN113479841A publication Critical patent/CN113479841A/en
Application granted granted Critical
Publication of CN113479841B publication Critical patent/CN113479841B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/02Microstructural systems; Auxiliary parts of microstructural devices or systems containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS]
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B01PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
    • B01LCHEMICAL OR PHYSICAL LABORATORY APPARATUS FOR GENERAL USE
    • B01L3/00Containers or dishes for laboratory use, e.g. laboratory glassware; Droppers
    • B01L3/50Containers for the purpose of retaining a material to be analysed, e.g. test tubes
    • B01L3/502Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures
    • B01L3/5027Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip
    • B01L3/502707Containers for the purpose of retaining a material to be analysed, e.g. test tubes with fluid transport, e.g. in multi-compartment structures by integrated microfluidic structures, i.e. dimensions of channels and chambers are such that surface tension forces are important, e.g. lab-on-a-chip characterised by the manufacture of the container or its components
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0032Packages or encapsulation
    • B81B7/007Interconnections between the MEMS and external electrical signals
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B7/00Microstructural systems; Auxiliary parts of microstructural devices or systems
    • B81B7/0083Temperature control
    • B81B7/009Maintaining a constant temperature by heating or cooling
    • B81B7/0093Maintaining a constant temperature by heating or cooling by cooling
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00119Arrangement of basic structures like cavities or channels, e.g. suitable for microfluidic systems
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00261Processes for packaging MEMS devices
    • B81C1/00301Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81BMICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B2201/00Specific applications of microelectromechanical systems
    • B81B2201/05Microfluidics
    • B81B2201/058Microfluidics not provided for in B81B2201/051 - B81B2201/054

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Analytical Chemistry (AREA)
  • Dispersion Chemistry (AREA)
  • Health & Medical Sciences (AREA)
  • General Health & Medical Sciences (AREA)
  • Hematology (AREA)
  • Clinical Laboratory Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Weting (AREA)
  • Micromachines (AREA)

Abstract

The invention discloses a preparation method of a silicon-based micro-channel substrate, and belongs to the technical field of microelectronics. The preparation method of the substrate comprises the following steps: step 1, photoetching and dry etching a silicon surface to form a plurality of parallel grooves, and removing surface photoresist; step 2, depositing a metal adhesion layer and a copper seed layer on the surface, spraying photoresist, photoetching, and corroding the metal adhesion layer and the copper seed layer at the bottom of the groove by a wet method; step 3, etching the parallel micro-channels by adopting a xenon difluoride dry method to remove the photoresist; step 4, electroplating copper to fill the groove, and finishing surface electroplating metal copper planarization; and 5, etching the copper metal and the metal adhesion layer through a surface photoetching cooling liquid interface, forming the cooling liquid interface through dry etching of silicon, communicating parallel micro-channels, removing surface photoresist, and finishing the preparation of the substrate. The invention realizes the preparation of the single-layer silicon wafer micro-channel structure by a simpler process and lower cost, and effectively solves the heat dissipation problem of the electronic module and the system.

Description

Silicon-based micro-channel substrate preparation method
Technical Field
The invention relates to a preparation method of a silicon-based micro-channel substrate, and belongs to the technical field of microelectronics.
Background
Because of the improvement of chip integration, electronic modules and systems are developed in the direction of high power and high heat flux, and higher requirements are put on microelectronic heat dissipation technology. The silicon material is used as the semiconductor material which is most widely applied, has higher dielectric constant and smaller electric size compared with other integrated substrate materials, has smaller size of the same structure under the same frequency band, and further realizes shorter interconnection length and higher integration density between chips integrated by the silicon-based high-density TSV (through silicon via) vertical interconnection and multilayer wiring structure. Meanwhile, the silicon material has good heterogeneous integration characteristics, so that high fusion of different semiconductor material chips and other material substrates can be realized, and richer system functional characteristics can be realized. In addition, the silicon material has higher thermal conductivity, and has material characteristics such as thermal expansion coefficient, young's modulus and the like which are closer to those of the compound chip, thus being a good semiconductor heat dissipation material.
With the development of micro-nano processing technology, the silicon substrate micro-channel and micro-nano complex structure take away the waste heat of the heating chip by utilizing the liquid working medium with high heat capacity, so that the micro-nano processing technology becomes an effective way for heat dissipation of the high-power chip. Through processing the flow channel with the section height and width of only tens to hundreds of micrometers on the silicon substrate by photoetching and etching methods, and then utilizing the fluid to timely take away heat when flowing through the micro flow channels. The three-dimensional integrated substrate based on the bulk silicon process can solve the problem of heat management of a high-power radio frequency front-end module of a silicon structure device such as a bulk acoustic wave filter. At present, a micro-channel structure is generally realized by adopting a high aspect ratio etching process and a wafer bonding process in MEMS (micro electro mechanical system) processing technology, the process is complex, the cost is high, and a reliable preparation method of a single-layer silicon wafer micro-channel structure is not formed yet.
Disclosure of Invention
The invention provides a preparation method of a silicon-based micro-channel substrate, which adopts an MEMS processing technology, realizes the preparation of a single-layer silicon wafer micro-channel structure with a simpler process and lower cost, and effectively solves the heat dissipation problem of electronic modules and systems. Can be used for heat dissipation of high-power chips.
The invention adopts the following technical scheme for solving the technical problems:
the preparation method of the silicon-based micro-channel substrate provided by the invention comprises the following steps:
Step 1: photoetching and dry etching are carried out on the surface of silicon to form parallel grooves;
step 2: depositing a metal adhesion layer and a copper seed layer on the surface of silicon, and carrying out photoresist spraying lithography and wet etching on the adhesion layer and the copper seed layer which are positioned at the bottom of the parallel grooves;
Step 3: etching a parallel micro-channel below the parallel groove by adopting a xenon difluoride dry method;
Step 4: filling parallel grooves by electroplating copper, covering the silicon surface, thereby closing the micro-channel structure and completing the planarization of the surface electroplated metal copper;
step 5: and photoetching a cooling liquid interface on the surface of the silicon, and corroding the cooling liquid interface by a wet method so as to communicate with the parallel micro-channels and finish the preparation of the substrate.
Further, the width of the parallel grooves in the step1 ranges from 10 μm to 30 μm, and the depth-to-width ratio of the parallel grooves is larger than 1.
Further, the width of the metal adhesion layer and the copper seed layer at the bottom of the wet etching groove in the step 2 is smaller than the width of the groove.
Further, the diameter of the parallel micro-channels in the step 3 is smaller than the distance between the parallel grooves in the step1.
Further, the radius of the parallel micro-channels in the step 3 is more than 20 μm smaller than the depth of the parallel grooves in the step 1.
Further, the depth of the cooling liquid interface in the step 5 is greater than or equal to the depth of the parallel micro-channels.
Further, the cooling liquid interface in the step 5 is communicated with the parallel micro-channels in the step 3.
The beneficial effects of the invention are as follows:
1) The preparation method of the silicon-based micro-channel substrate is compatible with the silicon-based copper TSV interconnection process, and can be widely applied to integration of electronic modules and systems.
2) The preparation method of the silicon-based micro-channel substrate adopts copper as a material between the chip and the cooling liquid working medium, so that the heat dissipation characteristic of the silicon substrate is further improved.
3) Compared with the common wafer bonding process, the preparation method of the silicon-based micro-channel substrate adopts a single-layer silicon wafer for processing, and has the advantages of simple process and lower processing cost.
Drawings
Fig. 1 is a top view of a silicon-based fluidic channel substrate.
FIG. 2 is a cross-sectional view of FIG. 1 A-A' of a silicon-based microchannel substrate.
FIG. 3 is a cross-sectional view of FIG. 1B-B' of a silicon-based microchannel substrate.
Wherein: 1. silicon; 2. a groove; 3. a copper seed layer; 4. a microchannel; 5. copper metal; 6. and a cooling liquid interface.
Detailed Description
The invention will be described in further detail with reference to the accompanying drawings.
The invention provides a preparation method of a silicon-based micro-channel substrate, which comprises the following steps of:
fig. 1-3 are block diagrams of a silicon-based micro-fluidic channel substrate, and the preparation method of the silicon substrate comprises the following steps:
1) Photoetching a pattern of parallel grooves 2 on the surface of silicon 1, wherein the width range of the grooves 2 is 10-30 mu m;
2) Forming a plurality of parallel grooves 2 by adopting inductively coupled plasma dry etching silicon, wherein the depth-to-width ratio of the grooves 2 is larger than 1;
3) Removing photoresist on the surface of the silicon 1;
4) Depositing a metal adhesion layer and a copper seed layer 3 on the surface of the silicon 1 by sputtering or evaporation;
5) Spraying photoresist on the surface of the silicon 1, wherein the photoresist covers the side wall of the groove 2, the bottom of the groove 2 is exposed, and the exposed width of the bottom of the groove 2 is smaller than the width of the groove 2;
6) Wet etching the metal adhesion layer and the copper seed layer 3 at the bottom of the trench 2;
7) Adopting xenon difluoride dry method to etch parallel micro-channels 4, wherein the diameter of the micro-channels 4 is smaller than the distance between the grooves 2, and the radius of the micro-channels 4 is more than 20 mu m smaller than the depth of the grooves 2;
8) Removing photoresist on the surface of the silicon 1 and in the groove 2;
9) Depositing metallic copper on the surface of the silicon 1 and in the groove 2 by adopting an electroplating process, and sealing the parallel micro-channels 4;
10 Adopting a mechanical grinding process to finish the planarization of the surface electroplated metal copper 5;
11 Patterning the surface of the silicon 1 by photoetching to form a cooling liquid interface 6;
12 Wet etching the copper metal and metal adhesion layer of the coolant interface 6;
13 Forming a cooling liquid interface 6 by adopting inductively coupled plasma dry etching silicon, wherein the depth of the cooling liquid interface 6 is greater than or equal to the depth of the micro-channel 4, so that the parallel micro-channel 4 is communicated;
14 The photoresist on the surface of the silicon 1 is removed.

Claims (2)

1. The preparation method of the silicon-based micro-channel substrate is characterized by comprising the following steps of:
Step 1: photoetching and dry etching are carried out on the surface of silicon to form parallel grooves;
Step 2: depositing a metal adhesion layer and a copper seed layer on the surface of silicon, and carrying out photoresist spraying lithography and wet etching on the metal adhesion layer and the copper seed layer which are positioned at the bottom of the parallel grooves;
Step 3: etching a parallel micro-channel below the parallel groove by adopting a xenon difluoride dry method;
Step 4: filling parallel grooves by electroplating copper, covering the silicon surface, thereby closing the micro-channel structure and completing the planarization of the surface electroplated metal copper;
Step 5: forming a cooling liquid interface on the silicon surface by photoetching, and corroding the cooling liquid interface by a wet method so as to communicate with the parallel micro-channels and finish the preparation of the substrate;
The widths of the metal adhesion layer and the copper seed layer at the bottom of the wet etching groove in the step2 are smaller than the width of the groove;
The diameter of the parallel micro-channels in the step 3 is smaller than the distance between the parallel grooves in the step 1;
the radius of the parallel micro-channels in the step 3 is more than 20 mu m smaller than the depth of the parallel grooves in the step 1;
And the depth of the cooling liquid interface in the step 5 is greater than or equal to the depth of the parallel micro-channels.
2. The method for preparing a silicon-based micro-fluidic channel substrate according to claim 1, wherein the width of the parallel grooves in the step 1 ranges from 10 μm to 30 μm, and the depth-to-width ratio of the parallel grooves is greater than 1.
CN202110563714.3A 2021-05-24 2021-05-24 Silicon-based micro-channel substrate preparation method Active CN113479841B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110563714.3A CN113479841B (en) 2021-05-24 2021-05-24 Silicon-based micro-channel substrate preparation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110563714.3A CN113479841B (en) 2021-05-24 2021-05-24 Silicon-based micro-channel substrate preparation method

Publications (2)

Publication Number Publication Date
CN113479841A CN113479841A (en) 2021-10-08
CN113479841B true CN113479841B (en) 2024-05-28

Family

ID=77933011

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110563714.3A Active CN113479841B (en) 2021-05-24 2021-05-24 Silicon-based micro-channel substrate preparation method

Country Status (1)

Country Link
CN (1) CN113479841B (en)

Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849589A (en) * 1971-12-20 1974-11-19 Siemens Ag Current feeding arrangement for electrical apparatus having low temperature cooled conductors
SU860176A1 (en) * 1979-03-11 1981-08-30 Предприятие П/Я А-7992 Coolant,mainly for cooling semiconductor devices
US6096656A (en) * 1999-06-24 2000-08-01 Sandia Corporation Formation of microchannels from low-temperature plasma-deposited silicon oxynitride
US6101715A (en) * 1995-04-20 2000-08-15 Daimlerchrysler Ag Microcooling device and method of making it
WO2002054475A1 (en) * 2001-01-02 2002-07-11 The Charles Stark Draper Laboratory, Inc. Method for microfabricating structures using silicon-on-insulator material
CN102082111A (en) * 2009-11-30 2011-06-01 上海华虹Nec电子有限公司 Manufacture method of deep isolation groove with air clearance
CN103204461A (en) * 2013-03-22 2013-07-17 上海宏力半导体制造有限公司 Semiconductor structure and forming method thereof
CN103377984A (en) * 2012-04-16 2013-10-30 上海华虹Nec电子有限公司 Manufacturing process method for TSV backside conduction
CN111099554A (en) * 2019-11-29 2020-05-05 杭州臻镭微波技术有限公司 Manufacturing method of TSV (through silicon Via) ground interconnection hole structure under silicon cavity in micro-system module
WO2020191985A1 (en) * 2019-03-25 2020-10-01 云南中烟工业有限责任公司 Coated silicon-based atomization chip of electronic cigarette and method for preparing same
CN112768432A (en) * 2020-12-31 2021-05-07 中国电子科技集团公司第五十五研究所 Microfluid adapter plate integrated with high-power radio frequency chip and preparation method thereof
CN112758888A (en) * 2021-02-20 2021-05-07 北京航天控制仪器研究所 Processing technology of silicon MEMS microstructure with through silicon via

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050141195A1 (en) * 2003-12-31 2005-06-30 Himanshu Pokharna Folded fin microchannel heat exchanger
EP1766682A2 (en) * 2004-06-24 2007-03-28 Technologies de l'Echange Thermique Improved cooling devices for different applications
US7396732B2 (en) * 2004-12-17 2008-07-08 Interuniversitair Microelektronica Centrum Vzw (Imec) Formation of deep trench airgaps and related applications
JP4218838B2 (en) * 2005-02-17 2009-02-04 株式会社ソニー・コンピュータエンタテインメント Power supply system, power supply apparatus, and electronic circuit driving method
ITTO20050478A1 (en) * 2005-07-12 2007-01-13 St Microelectronics Srl PROCEDURE FOR THE REALIZATION OF CAVITIES 'BURIED WITHIN A SEMICONDUCTOR BODY AND SEMICONDUCTOR BODY MADE THESE
TWI461689B (en) * 2010-04-01 2014-11-21 Univ Nat Cheng Kung Biomedical chip comprising dry powder reagent for blood coagulation test
EP2384816B1 (en) * 2010-05-04 2018-04-04 IMEC vzw Method of manufacturing a nanochannel device

Patent Citations (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849589A (en) * 1971-12-20 1974-11-19 Siemens Ag Current feeding arrangement for electrical apparatus having low temperature cooled conductors
SU860176A1 (en) * 1979-03-11 1981-08-30 Предприятие П/Я А-7992 Coolant,mainly for cooling semiconductor devices
US6101715A (en) * 1995-04-20 2000-08-15 Daimlerchrysler Ag Microcooling device and method of making it
US6096656A (en) * 1999-06-24 2000-08-01 Sandia Corporation Formation of microchannels from low-temperature plasma-deposited silicon oxynitride
WO2002054475A1 (en) * 2001-01-02 2002-07-11 The Charles Stark Draper Laboratory, Inc. Method for microfabricating structures using silicon-on-insulator material
CN102082111A (en) * 2009-11-30 2011-06-01 上海华虹Nec电子有限公司 Manufacture method of deep isolation groove with air clearance
CN103377984A (en) * 2012-04-16 2013-10-30 上海华虹Nec电子有限公司 Manufacturing process method for TSV backside conduction
CN103204461A (en) * 2013-03-22 2013-07-17 上海宏力半导体制造有限公司 Semiconductor structure and forming method thereof
WO2020191985A1 (en) * 2019-03-25 2020-10-01 云南中烟工业有限责任公司 Coated silicon-based atomization chip of electronic cigarette and method for preparing same
CN111099554A (en) * 2019-11-29 2020-05-05 杭州臻镭微波技术有限公司 Manufacturing method of TSV (through silicon Via) ground interconnection hole structure under silicon cavity in micro-system module
CN112768432A (en) * 2020-12-31 2021-05-07 中国电子科技集团公司第五十五研究所 Microfluid adapter plate integrated with high-power radio frequency chip and preparation method thereof
CN112758888A (en) * 2021-02-20 2021-05-07 北京航天控制仪器研究所 Processing technology of silicon MEMS microstructure with through silicon via

Also Published As

Publication number Publication date
CN113479841A (en) 2021-10-08

Similar Documents

Publication Publication Date Title
US7713789B2 (en) Semiconductor device with a high thermal dissipation efficiency
WO2022241848A1 (en) Silicon-based fan-out packaging structure and preparation method therefor
CN1988764B (en) Method of making an electronic device cooling system
US7259080B2 (en) Glass-type planar substrate, use thereof, and method for the production thereof
CN110010491B (en) Manufacturing process of cubic structure of multilayer stacked radio frequency microsystem
CN111689460B (en) Manufacturing method of TSV ground interconnection hole structure under silicon cavity in microsystem module
CN116130436B (en) Packaging structure integrated with porous micro-channel heat dissipation structure array and preparation method thereof
US10784115B2 (en) Method of etching microelectronic mechanical system features in a silicon wafer
CN114446907A (en) Active heat dissipation packaging method and structure for three-dimensional integrated TSV pin fin micro channel
CN111081655B (en) Electronic packaging structure and manufacturing method thereof
CN114975312A (en) Silicon-based three-dimensional packaging structure embedded with micro-channel and manufacturing method thereof
CN115799194B (en) Wafer heat dissipation micro-channel, preparation method and three-dimensional integration method
CN1988763A (en) Method of making an electronic device cooling system
CN111952194A (en) Liquid cooling heat dissipation process for radio frequency chip
CN111968944A (en) Ultrathin stacking process for radio frequency module
CN103199086B (en) There is silicon substrate pinboard of the micro-channel structure of band function of shielding and preparation method thereof
WO2022241846A1 (en) Lead bonding structure comprising embedded manifold type micro-channel and preparation method for lead bonding structure
CN113479841B (en) Silicon-based micro-channel substrate preparation method
CN111968921B (en) PCB assembly mode with liquid heat dissipation function
CN108682660B (en) Miniature cooling unit and integration method and device thereof
CN112802821B (en) Aluminum-based adapter plate with double-sided multilayer wiring and preparation method thereof
CN112234037B (en) Embedded diamond silicon-based micro-fluid heat dissipation adapter plate and preparation method thereof
KR102423373B1 (en) Semiconductor device and manufacturing method thereof
CN113174620B (en) Electroplating method of plating solution flow velocity reinforced TSV metal column
KR100460180B1 (en) The Heat Pipe using Porous Silicon Layer for Cooling Electronic Devices

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant