CN113471234A - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN113471234A CN113471234A CN202110736494.XA CN202110736494A CN113471234A CN 113471234 A CN113471234 A CN 113471234A CN 202110736494 A CN202110736494 A CN 202110736494A CN 113471234 A CN113471234 A CN 113471234A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 38
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- 238000005530 etching Methods 0.000 claims description 30
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- 238000009792 diffusion process Methods 0.000 claims description 17
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 5
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- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
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- 238000005468 ion implantation Methods 0.000 abstract description 12
- 238000002360 preparation method Methods 0.000 abstract description 5
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/14632—Wafer-level processed structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
According to the back-illuminated image sensor and the preparation method thereof provided by the invention, P-type ions are doped in the epitaxial structure while the epitaxial structure grows in the groove between the adjacent N-type structures. And furthermore, an ion implantation process is not required to be executed after the epitaxial structure is completely grown, so that the problem of poor implantation effect caused by too large depth-to-width ratio of the groove is avoided, and the performance of the finally prepared semiconductor device is improved.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
The back-illuminated image sensor product is a semiconductor device for collecting and processing images, and a Photodiode (PD) is applied to a CIS product as a photoelectric conversion device, so that the CIS product can convert optical signals into electrical signals for storage and display.
The existing CIS product has adopted a Back-illuminated (Back-illuminated) process, that is, after completing MOS transistors and metal wiring, a semiconductor substrate is ground on the Back side of the semiconductor substrate (in order to reduce the thickness of the semiconductor substrate), so that the Back side of the semiconductor substrate is used as a light-sensitive window, and the front side of the semiconductor substrate is bonded to other auxiliary semiconductor substrates to realize a light processing function. A basic unit of the CMOS image sensor is called a pixel, and is composed of 1 photodiode and 3 or 4 MOS transistors.
At present, with the improvement of living standard of people, the quality requirement of people on the back-illuminated image sensor is higher and higher. While the higher the pixel, the higher the quality of the back-illuminated image sensor. Therefore, the back-illuminated image sensor is increasingly developed toward a small-sized pixel. However, as the area of the pixel unit is continuously reduced, the aspect ratio of the pixel region is increased. Therefore, when the back-illuminated image sensor is prepared, the existing ion doping process cannot meet the requirements generally, and the finally prepared back-illuminated image sensor has poor performance.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which aim to solve the problem of poor ionic performance in the preparation process of the conventional back-illuminated image sensor.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate;
implanting N-type ions into the substrate to form an N-type doped layer;
etching the N-type doped layer to form a plurality of slots at least penetrating through the N-type doped layer, wherein the slots divide the N-type doped layer to form a plurality of N-type structures, and the width of each slot is smaller than that of each N-type structure;
and growing an epitaxial structure in the groove, and doping P-type ions in the epitaxial structure to form a plurality of P-type structures while growing the epitaxial structure, wherein the P-type structures and the N-type structures are alternately arranged.
Optionally, the method for forming a plurality of trenches penetrating through at least the N-type doped layer includes:
sequentially forming a hard mask material layer and a photoresist layer on the N-type doped layer, wherein an opening is formed in the photoresist layer;
and etching the hard mask material layer by taking the photoresist layer as a mask to form a hard mask layer, etching the N-type doping layer by taking the hard mask layer as a mask, and extending the opening at least into the N-type doping layer to form the slot.
Optionally, the method for etching the hard mask layer and the N-type doped layer is dry etching, and an etching selection ratio of the etching gas of the dry etching to the N-type doped layer and the hard mask layer is greater than 10: 1.
Optionally, the etching gas includes: a mixture gas of hydrobromic acid gas, chlorine gas, hydrogen chloride gas and polyhalogen gas.
Optionally, before forming the photoresist layer, the method further includes: forming a hard mask material layer on the substrate;
and, while etching the hard mask layer, the method further comprises: and etching the anti-reflection material layer to form an anti-reflection layer and extend the opening into the anti-reflection layer.
Optionally, the depth of the groove is 15-20 times of the width of the groove.
Optionally, the method for forming the P-type structure includes:
and growing an epitaxial structure from the bottom of the groove, and performing a P ion diffusion process at least twice in the growth process of the epitaxial structure to dope P ions in the epitaxial structure to form a P-type structure, wherein the P ion diffusion process is performed at least twice when the epitaxial structure grows to different preset heights.
Optionally, the predetermined height is equal to the sum of the heights of the epitaxial structures grown at each time.
Optionally, the height of the epitaxial structure grown each time is calculated according to the following formula to obtain:
D＝(2n/(17-n))*H
wherein D represents: the height of the epitaxial structure at each growth;
n represents: the growth times of the epitaxial structure are n is a positive integer which is more than or equal to 1 and less than 11;
h represents: the depth of the slot.
Optionally, the epitaxial structure doped with P ions protrudes from the N-type structure, and the method includes:
and performing a chemical mechanical polishing process on the epitaxial structure doped with the P ions to remove at least the part of the epitaxial structure doped with the P ions, which protrudes out of the top surface of the N-type structure, so as to form a P-type structure and enable the top surface of the P-type structure to be flush with the top surface of the N-type structure.
In the invention, P-type ions are doped in the epitaxial structure while the epitaxial structure is grown in the groove between the adjacent N-type structures. Therefore, an ion implantation process is not required to be performed after the epitaxial structure is completely grown, the problem of poor implantation effect caused by too large depth-to-width ratio of the groove is avoided, and the performance of the finally prepared semiconductor device is improved.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 to 9 are process diagrams of a manufacturing method of a semiconductor device in an embodiment of the present invention;
wherein the reference numbers are as follows:
1-N type structure;
a 10-N type layer; 100-a substrate;
2-a hard mask layer; 20-a layer of hard mask material;
30-a layer of antireflective material;
4-a photoresist layer;
a 5-P type structure; 50-epitaxial structure;
6-a device layer;
61-a first dielectric layer; 62-a metal interconnect layer;
7-second dielectric layer.
Detailed Description
The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 2 to 9 are process diagrams of a method for manufacturing a semiconductor device in an embodiment of the present invention. A method for manufacturing the semiconductor device in this embodiment will be described below with reference to fig. 1 to 9.
In step S10, as shown in fig. 2, a substrate 100 is provided.
In this embodiment, the substrate 100 may include a semiconductor material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, continuing to refer to fig. 2, N-type ions are implanted into the substrate 100 to form an N-type doped layer 10.
In the present embodiment, the N-type ions implanted into the substrate 100 may include phosphorus ions. And the energy of the N-type ion implantation is 300 KeV-2000 KeV. The depth of the N-type ion implantation into the substrate 100 is 2.5um to 3.5 um.
Also in the present embodiment, an N-type ion implantation process may be performed on the substrate 100 once. It is also possible to perform a plurality of N-type ion implantation processes on the substrate 100 and successively reduce the depth of the N-type ion implantation into the substrate 100. And after the N-type ion implantation process is performed, an annealing process is performed on the substrate 100, so that the N-type ion concentration in the finally formed N-type doped layer 10 is uniform.
In step S30, as shown in fig. 3 to 4, the N-type doped layer 10 is etched to form a plurality of trenches 1A penetrating at least through the N-type doped layer, the N-type doped layer 10 is divided into a plurality of N-type structures 1 by the trenches 1A, wherein the width of the trenches 1A is smaller than the width of the N-type structures 1. The N-type structure 1 is used to form a pixel structure of a back-illuminated image sensor.
In this embodiment, the depth of the slot 1A is 1.2 to 1.5 times the thickness of the N-type structure 1. Thus, the slots 1A can completely isolate adjacent N-type structures 1. And the depth of the slot 1A is 15-25 times of the width of the slot 1A.
With continued reference to fig. 3 and 4, in the present embodiment, the method of forming a plurality of trenches 1A at least penetrating through the N-type doped layer 10 includes the following steps one to three.
In the first step, as shown in fig. 3, a hard mask material layer 20 and a photoresist layer 4 are sequentially formed on the N-type doped layer 10, and an opening 4A is formed in the photoresist layer 4.
The hard mask material layer 20 is made of silicon nitride or silicon oxynitride. The layer of hard mask material 20 has a thickness of
The thickness of the photoresist layer 4 is
In the second step, as shown in fig. 4, the hard mask material layer 20 is etched by using the photoresist layer 4 as a mask to form a hard mask layer 2, the N-type doped layer 10 is etched by using at least the hard mask layer 2 as a mask, and the opening 4A extends into at least the N-type doped layer 10 to form the trench 1A.
In this embodiment, after the hard mask material layer 20 and the photoresist layer 4 are sequentially formed on the N-type doped layer 10, the hard mask material layer 20 is etched by using the photoresist layer 4 as a mask, and at least a portion of the photoresist layer 4 is etched away in this process. Continuing to etch the N-type doped layer 10 without stopping the etching process, and in the process, if the photoresist layer 4 is completely etched away, etching the N-type doped layer 10 by using the hard mask layer 2 as a mask; and if the photoresist layer 4 is not completely etched, etching the N-type doped layer 10 by using the residual photoresist layer 4 and the hard mask layer 2 as masks.
In the embodiment, the etching method is dry etching, and the etching selection ratio of the etching gas of the dry etching to the N-type doped layer and the hard mask layer is greater than 10: 1. And, the etching gas comprises: a mixture gas of hydrobromic acid gas, chlorine gas, hydrogen chloride gas and polyhalogen gas.
Optionally, in the second step, the etching of the hard mask material layer 20 and the etching of the N-type doped layer 10 may be performed step by step. Namely, after the hard mask material layer 20 is etched to form the hard mask layer 2 by using the photoresist layer 4 as a mask, the photoresist layer 4 remaining on the hard mask layer 2 is removed. And etching the N-type doped layer 10 by taking the hard mask layer 2 as a mask.
Further, before forming the photoresist layer 4, the method further includes: a layer of antireflective material 30 is formed on the layer of hardmask material 20. Wherein, the thickness of the anti-reflection material layer 30 is:
while etching the hard mask material layer 20, the method further comprises: the anti-reflection material layer 30 is etched to form an anti-reflection layer (not shown) and extend the opening 4A into the anti-reflection layer (not shown).
In addition, in the present embodiment, after etching the N-type doped layer 10, the method includes performing an ashing process on the substrate 100, so as to remove the remaining photoresist layer 4.
In step S40, referring to fig. 4 to 9, in this embodiment, an epitaxial structure 50 is grown in the trench 1A, and P-type ions are doped in the epitaxial structure 50 to form a plurality of P-type structures 5 while the epitaxial structure 50 is grown, wherein the P-type structures 5 and the N-type structures 1 are alternately arranged.
In the present embodiment, P-type ions are doped in the epitaxial structure 50 while the epitaxial structure 50 is grown in the trench 1A between the adjacent N-type structures 1. Therefore, an ion implantation process is not required to be performed after the epitaxial structure 50 is completely grown, so that the problem of poor implantation effect caused by an excessively large aspect ratio of the trench 1A is avoided, and the performance of the finally prepared semiconductor device is improved.
In this embodiment, the method for forming the P-type structure includes: growing an epitaxial structure 50 from the bottom of the trench 1A, and performing a P-ion diffusion process at least twice during the growth of the epitaxial structure 50 to form a P-type structure 5, wherein the P-ion diffusion process is performed at least twice when the epitaxial structure 50 is grown to different predetermined heights. Specifically, the method of forming the P-type structure 5 includes the following steps.
The method comprises the following steps: as shown in fig. 5 to 7, an epitaxial structure 50 is grown from the bottom of the trench 1A, and when the epitaxial structure 50 is grown to a first predetermined height, a P ion diffusion process is performed on the epitaxial structure 50 to perform P ion doping on the grown epitaxial structure 50.
Step two: continuing epitaxial growth on the P-ion-doped epitaxial structure 50 until the epitaxial structure 50 grows to a second predetermined height, and performing a P-ion diffusion process on the epitaxial structure 50 again. Wherein the content of the first and second substances,
and repeating the second step until the epitaxial structure 50 grows to be at least flush with the N-type structure 1, stopping epitaxial growth, and executing a final P ion diffusion process to perform final P ion implantation on the epitaxial structure 50.
In the present embodiment, a P ion diffusion process is performed on the epitaxial structure 50, wherein P ions may be diffused only into the un-implanted epitaxial structure 50, or may be continuously implanted into the underlying P ion-implanted epitaxial structure 50. When the P ion implantation process is performed when the epitaxial structure 50 is grown to different heights, the P ion implantation process may be performed only once or multiple times, and the specific details are not limited herein.
Wherein the predetermined height d is equal to the sum of the heights of the epitaxial structures grown each time.
The height of the epitaxial structure 50 for each growth is calculated according to the following formula to obtain:
D＝(2n/(17-n))*H
wherein D represents: the height of the epitaxial structure 50 at each growth; n represents: the number of times of growing the epitaxial structure, n is an integer greater than or equal to 1 and less than 17; h represents: the depth of the slot 1A.
For example, in the present embodiment, the epitaxial structure 50 is grown for the first time in the trench 1A, the height D1 of the epitaxial structure 50 grown for the first time is (2/(17-1)) H1/8H, and then, the predetermined height is 1/8H when the first P-ion diffusion process is performed on the epitaxial structure 50 grown for the first time, that is, the ion diffusion process is performed for the first time. Thereafter, the epitaxial structure 50 is grown for the second time on the epitaxial structure 50 grown for the first time, and a second P ion diffusion process is performed on the epitaxial structure 50 grown for the second time, where the height D2 of the epitaxial structure 50 grown for the second time is (2 × 2/(17-2)) H4/15H, and then the predetermined height D1+ D2 is 1/8H +4/15H when the ion diffusion process is performed for the second time. Finally, the epitaxial structure 50 is grown for the third time on the epitaxial structure 50 grown for the second time, and the height D2 of the epitaxial structure 50 grown for the third time is (2 × 3/(17-3)) H5/7H, so that when the ion diffusion process is performed for the third time, the predetermined height is D1+ D2+ D3 is 1/8H +4/15H + 5/7H. In this embodiment, the epitaxial structure 50 is grown three times, and in an alternative embodiment, the epitaxial structure may be grown the rest of the times. The number of times of growing the epitaxial structure 50 and the number of times n of performing the P ion diffusion process are positive integers greater than or equal to 1 and less than 11. Wherein, the best effect is obtained when the number of times of growing the epitaxial structure 50 and the number of times of performing the P-ion diffusion process n is 5.
In this embodiment, the epitaxial structure 50 doped with the P ions protrudes from the N-type structure 1, and the method includes: and performing a chemical mechanical polishing process on the epitaxial structure 50 doped with the P ions to remove at least a portion of the epitaxial structure 50 doped with the P ions protruding from the top surface of the N-type structure 1 to form a P-type structure 5, and making the top surface of the P-type structure 5 flush with the top surface of the N-type structure 1.
In the present embodiment, the height of the epitaxial structure 50 protruding the top surface of the N-type structure 1 after doping with P ions is
In addition, in the present embodiment, the epitaxial structure 50 doped with P ions further protrudes from the top surface of the hard mask layer 2.
In the embodiment, since the epitaxial structure 50 doped with P ions protrudes from the top surface of the N-type structure 1, the epitaxial structure 50 doped with P ions is polished by a chemical mechanical mask process, so that the epitaxial structure 50 doped with P ions is flush with the top surface of the N-type structure 1, and the surfaces of the epitaxial structure 50 doped with P ions and the N-type structure 1 are planarized. So as to improve the uniformity of the structure of the subsequent process and improve the product performance.
In addition, in this embodiment, when the portion of the epitaxial structure 50 protruding from the N-type structure 1 after the P-doped ions are removed by grinding, the hard mask layer 2 on the top surface of the N-type structure 1 may also be removed by grinding. After the portion of the epitaxial structure 50 doped with P ions protruding from the N-type structure 1 is removed by grinding, the grinding may be continued to remove the thickness of the portion of the epitaxial structure 50 doped with P ions and the N-type structure 1 by grinding, so as to form a P-type structure. In this example, removal by grinding
Is measured. This is done to make the top surfaces of the N-type structure 1 and the P-type structure 5 more planar.
And, in the present embodiment, the doped P-type ions may include B ions (boron ions) or BF2Ions (difluoride ion).
Further, as shown in fig. 9, after the P-type structure 5 is formed, a device layer 7 may be further formed on the P-type structure 5 and the N-type structure 1, where the device layer 7 includes a first dielectric layer 71 and a metal interconnection structure 72 formed in the first dielectric layer 71. In addition, a second dielectric layer 6 is formed on the device layer 7. The first dielectric layer 71 and the second dielectric layer 6 are made of silicon oxide. The second dielectric layer 6 is used for protecting the device layer 7.
Further, the embodiment also discloses a semiconductor device, which is prepared by the preparation method of the semiconductor device. Wherein the semiconductor device is a back-illuminated image sensor.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
implanting N-type ions into the substrate to form an N-type doped layer;
etching the N-type doped layer to form a plurality of slots at least penetrating through the N-type doped layer, wherein the slots divide the N-type doped layer to form a plurality of N-type structures, and the width of each slot is smaller than that of each N-type structure;
and growing an epitaxial structure in the groove, and doping P-type ions in the epitaxial structure to form a plurality of P-type structures while growing the epitaxial structure, wherein the P-type structures and the N-type structures are alternately arranged.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a plurality of trenches extending through at least the N-type doped layer comprises:
sequentially forming a hard mask material layer and a photoresist layer on the N-type doped layer, wherein an opening is formed in the photoresist layer;
and etching the hard mask material layer by taking the photoresist layer as a mask to form a hard mask layer, etching the N-type doping layer by taking the hard mask layer as a mask, and extending the opening at least into the N-type doping layer to form the slot.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the method for etching the hard mask layer and the N-type doped layer is dry etching, and an etching selection ratio of the etching gas for the dry etching to the N-type doped layer and the hard mask layer is greater than 10: 1.
4. The method of manufacturing a back semiconductor device according to claim 3, wherein the etching gas comprises: a mixture gas of hydrobromic acid gas, chlorine gas, hydrogen chloride gas and polyhalogen gas.
5. The method for manufacturing a semiconductor device according to claim 2, wherein before forming the photoresist layer, the method further comprises: forming a hard mask material layer on the substrate;
and, while etching the hard mask layer, the method further comprises: and etching the anti-reflection material layer to form an anti-reflection layer and extend the opening into the anti-reflection layer.
6. The method for manufacturing a semiconductor device according to claim 1, wherein a depth of the groove is 15 to 20 times a width of the groove.
7. The method for manufacturing a semiconductor device according to claim 1, wherein the method for forming the P-type structure comprises:
and growing an epitaxial structure from the bottom of the groove, and performing a P ion diffusion process at least twice in the growth process of the epitaxial structure to dope P ions in the epitaxial structure to form a P-type structure, wherein the P ion diffusion process is performed at least twice when the epitaxial structure grows to different preset heights.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the predetermined height is equal to a sum of heights of the epitaxial structures grown each time.
9. The method for manufacturing a semiconductor device according to claim 8, wherein the height of the epitaxial structure for each growth is calculated according to the following formula to obtain: d ═ 2 n/(17-n)). H
Wherein D represents: the height of the epitaxial structure at each growth;
n represents: the growth times of the epitaxial structure are n is a positive integer which is more than or equal to 1 and less than 11;
h represents: the depth of the slot.
10. The method of manufacturing a semiconductor device according to claim 7, wherein the epitaxial structure after doping with P ions protrudes beyond the N-type structure, the method comprising:
and performing a chemical mechanical polishing process on the epitaxial structure doped with the P ions to remove at least the part of the epitaxial structure doped with the P ions, which protrudes out of the top surface of the N-type structure, so as to form a P-type structure and enable the top surface of the P-type structure to be flush with the top surface of the N-type structure.
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