CN113451343A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
- Publication number
- CN113451343A CN113451343A CN202110739263.4A CN202110739263A CN113451343A CN 113451343 A CN113451343 A CN 113451343A CN 202110739263 A CN202110739263 A CN 202110739263A CN 113451343 A CN113451343 A CN 113451343A
- Authority
- CN
- China
- Prior art keywords
- type
- layer
- semiconductor device
- epitaxial structure
- etching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims description 51
- 239000004065 semiconductor Substances 0.000 title claims description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 238000005468 ion implantation Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims description 30
- 239000000463 material Substances 0.000 claims description 27
- 229920002120 photoresistant polymer Polymers 0.000 claims description 23
- 239000007789 gas Substances 0.000 claims description 22
- 150000002500 ions Chemical class 0.000 claims description 20
- -1 boron ions Chemical class 0.000 claims description 7
- 238000001312 dry etching Methods 0.000 claims description 6
- 230000000149 penetrating effect Effects 0.000 claims description 6
- 239000000126 substance Substances 0.000 claims description 4
- BMYNFMYTOJXKLE-UHFFFAOYSA-N 3-azaniumyl-2-hydroxypropanoate Chemical compound NCC(O)C(O)=O BMYNFMYTOJXKLE-UHFFFAOYSA-N 0.000 claims description 3
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 claims description 3
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 claims description 3
- 229910000041 hydrogen chloride Inorganic materials 0.000 claims description 3
- 239000000203 mixture Substances 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000007517 polishing process Methods 0.000 claims description 3
- 238000002360 preparation method Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 106
- 238000000227 grinding Methods 0.000 description 5
- 239000002184 metal Substances 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000003667 anti-reflective effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003811 SiGeC Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
- H01L27/14687—Wafer level processing
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
According to the preparation method of the back-illuminated image sensor, the P-type ion implantation is firstly carried out on the substrate to form the P-type doping layer, then the P-type doping layer is etched to form the groove, and the width of the groove is larger than that of the P-type structure formed after the groove is divided. Therefore, the aspect ratio of the epitaxial structure subsequently grown in the groove is reduced, and the implantation effect can be improved when the N-type ion implantation is performed on the epitaxial structure, so as to improve the performance of the finally prepared back-illuminated image sensor.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a preparation method of a semiconductor device.
Background
The back-illuminated image sensor product is a semiconductor device for collecting and processing images, and a Photodiode (PD) is applied to a CIS product as a photoelectric conversion device, so that the CIS product can convert optical signals into electrical signals for storage and display.
The existing CIS product has adopted a Back-illuminated (Back-illuminated) process, that is, after completing MOS transistors and metal wiring, a semiconductor substrate is ground on the Back side of the semiconductor substrate (in order to reduce the thickness of the semiconductor substrate), so that the Back side of the semiconductor substrate is used as a light-sensitive window, and the front side of the semiconductor substrate is bonded to other auxiliary semiconductor substrates to realize a light processing function. A basic unit of the CMOS image sensor is called a pixel, and is composed of 1 photodiode and 3 or 4 MOS transistors.
At present, with the improvement of living standard of people, the quality requirement of people on the back-illuminated image sensor is higher and higher. While the higher the pixel, the higher the quality of the back-illuminated image sensor. Therefore, the back-illuminated image sensor is increasingly developed toward a small-sized pixel. However, as the area of the pixel unit is continuously reduced, the aspect ratio of the pixel region is increased. So that when a back-illuminated image sensor is prepared,
the existing ion doping process can not meet the requirements generally, and the performance of the finally prepared back-illuminated image sensor is poor.
Disclosure of Invention
The invention aims to provide a semiconductor device and a preparation method thereof, which aim to solve the problem that the performance is reduced due to damage in the existing preparation process of the semiconductor device.
In order to solve the above technical problem, the present invention provides a method for manufacturing a semiconductor device, including:
providing a substrate;
implanting P-type ions into the substrate to form a P-type doped layer;
etching the P-type doped layer to form a plurality of grooves at least penetrating through the P-type doped layer, wherein the grooves divide the P-type doped layer to form a plurality of P-type structures, and the width of each groove is larger than that of each P-type structure;
and growing an epitaxial structure in the groove, and carrying out N-type ion implantation on the epitaxial structure to form a plurality of N-type structures, wherein the N-type structures and the P-type structures are alternately arranged.
Optionally, the method for forming a plurality of trenches penetrating through at least the P-type doped layer includes:
sequentially forming a hard mask material layer and a photoresist layer on the P-type doping layer, wherein an opening is formed in the photoresist layer;
and etching the hard mask material layer by taking the photoresist layer as a mask to form a hard mask layer, etching the P-type doping layer by taking the hard mask layer as a mask, and extending the opening at least into the P-type doping layer to form the slot.
Optionally, the method for etching the hard mask layer and the P-type doped layer is dry etching, and the etching selectivity ratio of the etching gas of the dry etching to the P-type doped layer and the hard mask layer is greater than 10: 1.
Optionally, the etching gas includes: a mixture gas of hydrobromic acid gas, chlorine gas, hydrogen chloride gas and polyhalogen gas.
Optionally, before forming the photoresist layer, the method further includes: forming an anti-reflection material layer on the hard mask material layer;
and, while etching the hard mask layer, the method further comprises: and etching the anti-reflection material layer to form an anti-reflection layer and extend the opening into the anti-reflection layer.
Optionally, the depth of the groove is 1.2-1.5 times of the thickness of the P-type structure.
Optionally, growing an epitaxial structure in the trench includes:
growing an initial epitaxial structure in the groove, and enabling the initial epitaxial structure to protrude out of the top surface of the P-type structure;
and performing a chemical mechanical polishing process on the initial epitaxial structure to remove at least a part of the initial epitaxial structure protruding out of the top surface of the P-type structure so as to form an epitaxial structure and make the top surface of the epitaxial structure and the top surface of the P-type structure flush.
Optionally, the height of the initial epitaxial structure protruding the P-type structure is
Optionally, the method for implanting P-type ions into the substrate includes: performing a plurality of times of P-type ion implantation processes, and gradually reducing the depth of the P-type ions implanted into the substrate; and/or the presence of a gas in the gas,
the method for carrying out N-type ion implantation on the epitaxial structure comprises the following steps: and executing a plurality of N-type ion implantation processes, and gradually reducing the depth of the N-type ions implanted into the epitaxial structure.
Optionally, the implanted P-type ions include boron ions or difluorinated Pentium ions; and, the implanted N-type ions include: a phosphorus ion.
In the invention, the substrate is firstly subjected to P-type ion implantation to form a P-type doped layer, then the P-type doped layer is etched to form a groove, and the width of the groove is larger than that of a P-type structure formed after being divided by the groove. Therefore, the aspect ratio of the epitaxial structure subsequently grown in the slot is reduced, and the implantation effect can be improved when the N-type ion implantation is performed on the epitaxial structure, so as to improve the performance of the finally prepared semiconductor device.
Drawings
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 2 to 8 are process diagrams of a manufacturing method of a semiconductor device in an embodiment of the present invention;
wherein the reference numbers are as follows:
1-P type structure;
a 10-P type doped layer; 100-a substrate;
2-a hard mask layer; 20-a layer of hard mask material;
30-a layer of antireflective material;
4-a photoresist layer;
5-an epitaxial structure; 50-an initial epitaxial structure;
a 6-N type structure;
7-a device layer;
71-a first dielectric layer; 72-metal interconnect layer;
8-a second dielectric layer.
Detailed Description
The semiconductor device and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific examples. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Fig. 1 is a flowchart of a method of manufacturing a semiconductor device according to an embodiment of the present invention; fig. 2 to 7 are process diagrams of a method for manufacturing a semiconductor device in an embodiment of the present invention. A method for manufacturing the semiconductor device in this embodiment will be described below with reference to fig. 1 to 7.
In step S10, as shown in fig. 2, a substrate 100 is provided.
In this embodiment, the substrate 100 may include a semiconductor material, a conductor material, or any combination thereof, and may have a single-layer structure or a multi-layer structure. Thus, the substrate may be a semiconductor material such as Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III/V or II/VI compound semiconductors. Layered substrates such as, for example, Si/SiGe, Si/SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator may also be included.
In step S20, continuing to refer to fig. 2, P-type ions are implanted into the substrate 100 to form a P-type doped layer 10.
In the present embodiment, the P-type ions implanted into the substrate 100 may include B ions (boron ions) or BF2Ions (difluoride ion). And the energy of the P-type ion implantation is 300 KeV-2000 KeV. The depth of the P-type ion implantation into the substrate 100 is 2.5um to 3.5 um.
Also in the present embodiment, a P-type ion implantation process may be performed on the substrate 100 once. It is also possible to perform a plurality of P-type ion implantation processes on the substrate 100 and successively reduce the depth of the P-type ion implantation into the substrate 100. And after the P-type ion implantation process is performed, an annealing process is performed on the substrate 100, so that the concentration of P-type ions in the finally formed P-type doped layer 10 is uniform.
In step S20, as shown in fig. 3 to 4, the P-type doped layer 10 is etched to form a plurality of trenches 1A penetrating at least the P-type doped layer, the trenches 1A divide the P-type doped layer 10 into a plurality of P-type structures 1, wherein the width of the trenches 1A is greater than the width of the P-type structures 1.
In this embodiment, P-type ion implantation is performed on the substrate 100 to form the P-type doped layer 10, and then the P-type doped layer 10 is etched to form the trench 1A, so that the width of the trench 1A is greater than the width of the P-type structure 1 divided by the trench 1A. Therefore, the aspect ratio of the epitaxial structure subsequently grown in the trench 1A is reduced, and thus, when N-type ion implantation is performed on the epitaxial structure, the implantation effect can be improved, so as to improve the performance of the finally prepared semiconductor device.
In this embodiment, the depth of the slot 1A is 1.2 to 1.5 times the thickness of the P-type structure 1. Thus, the slots 1A can completely isolate adjacent P-type structures 1.
With continued reference to fig. 3 and 4, in the present embodiment, the method of forming a plurality of trenches 1A penetrating at least the P-type doped layer 10 includes the following steps one to three.
In the first step, as shown in fig. 3, a hard mask material layer 20 and a photoresist layer 4 are sequentially formed on the P-type doped layer 10, and an opening 4A is formed in the photoresist layer 4.
The hard mask material layer 20 is made of silicon nitride or silicon oxynitride. The layer of hard mask material 20 has a thickness of
The thickness of the photoresist layer 4 is
In the second step, the hard mask material layer 20 is etched by using the photoresist layer 4 as a mask to form a hard mask layer 2, the P-type doping layer 10 is etched by using at least the hard mask layer 2 as a mask, and the opening 4A extends into at least the P-type doping layer 10 to form the trench 1A.
In this embodiment, after the hard mask material layer 20 and the photoresist layer 4 are sequentially formed on the P-type doped layer 10, the hard mask material layer 20 is etched by using the photoresist layer 4 as a mask, and at least a portion of the photoresist layer 4 is etched away in this process. Continuing to etch the P-type doped layer 10 without stopping the etching process, and in the process, if the photoresist layer 4 is completely etched away, etching the P-type doped layer 10 by using the hard mask layer 2 as a mask; and if the photoresist layer 4 is not completely etched, etching the P-type doped layer 10 by using the residual photoresist layer 4 and the hard mask layer 2 as masks.
In the embodiment, the etching method is dry etching, and the etching selection ratio of the etching gas of the dry etching to the P-type doped layer and the hard mask layer is greater than 10: 1. And, the etching gas comprises: a mixture gas of hydrobromic acid gas, chlorine gas, hydrogen chloride gas and polyhalogen gas.
Optionally, in the second step, the etching of the hard mask material layer 20 and the etching of the P-type doped layer 10 may be performed step by step. Namely, after the hard mask material layer 20 is etched to form the hard mask layer 2 by using the photoresist layer 4 as a mask, the photoresist layer 4 remaining on the hard mask layer 2 is removed. And etching the P-type doped layer 10 by taking the hard mask layer 2 as a mask.
Further, before forming the photoresist layer 4, the method further includes: a layer of antireflective material 30 is formed on the layer of hardmask material 20. Wherein, the thickness of the anti-reflection material layer 30 is:
while etching the hard mask material layer 20, the method further comprises: the anti-reflection material layer 30 is etched to form an anti-reflection layer (not shown) and extend the opening 4A into the anti-reflection layer (not shown).
In addition, in the present embodiment, after etching the P-type doped layer 10, the method includes performing an ashing process on the substrate 100, so as to remove the residual photoresist layer 4.
In step S30, referring to fig. 4 to 7, in the present embodiment, an epitaxial structure 5 is grown in the trench 1A, and N-type ion implantation is performed on the epitaxial structure 5 to form a plurality of N-type structures 6, where the N-type structures 6 and the P-type structures 1 are alternately arranged. The N-type structure 6 is used to form a pixel structure of a back-illuminated image sensor.
In the present embodiment, as shown in fig. 5 to 6, the method of growing the epitaxial structure 5 in the trench 1A includes the following first step and second step.
In a first step, an initial epitaxial structure 50 is grown in the trench 1A, and the initial epitaxial structure 50 protrudes from the top surface of the P-type structure 1.
In the present embodiment, the initial epitaxial structure 50 protrudes above the top surface of the P-type structure 1 by a height of
In addition, in the present embodiment, the initial epitaxial structure 50 further protrudes from the top surface of the hard mask layer 2.
In a second step, a chemical mechanical polishing process is performed on the initial epitaxial structure 50 to remove at least a portion of the initial epitaxial structure 50 protruding above the top surface of the P-type structure 1, so as to form an epitaxial structure 5 and make the top surface of the epitaxial structure 5 and the top surface of the P-type structure 1 flush.
In the present embodiment, since the initial epitaxial structure 50 protrudes from the top surface of the P-type structure 1, the epitaxial structure 5 is polished by a chemical mechanical mask process so as to make the top surfaces of the epitaxial structure 5 and the P-type structure 1 flush, thereby planarizing the surfaces formed by the epitaxial structure 5 and the P-type structure 1. So as to improve the uniformity of the structure of the subsequent process and improve the product performance.
In addition, in this embodiment, when the portion of the initial epitaxial structure 50 protruding from the P-type structure 1 is removed by grinding, the hard mask layer 2 on the top surface of the P-type structure 1 may also be removed by grinding. After the grinding process is performed to remove the portion of the initial epitaxial structure 50 protruding from the P-type structure 1, the grinding process may be continued to grind the P-type structure 1 and the initial epitaxial structure 1Epitaxial structure 50 is then lapped to remove a portion of its thickness to form the final epitaxial structure 5. In this example, removal by grinding
Is measured. This is done to make the top surfaces of the P-type structure 1 and the epitaxial structure 5 more planar.
And, in the present embodiment, the N-type ions implanted into the epitaxial structure 5 may include phosphorus ions. And the energy of the N-type ion implantation is 300 KeV-3000 KeV.
In addition, in the present embodiment, an N-type ion implantation process may be performed on the epitaxial structure 5 once. It is also possible to perform the N-type ion implantation process on the epitaxial structure 5 a plurality of times and successively reduce the depth of the N-type ion implantation into the epitaxial structure 5. And after the N-type ion implantation process is performed, performing an annealing process again on the substrate 100, so as to make the N-type ion concentration in the finally formed N-type structure 6 uniform. In the present embodiment, the N-type structure is used to form a pixel of the semiconductor device.
Further, as shown in fig. 8, after the N-type structure 6 is formed, a device layer 7 may be further formed on the N-type structure 6 and the P-type structure 1, wherein the device layer 7 includes a first dielectric layer 71 and a metal interconnection structure 72 formed in the first dielectric layer 71. In addition, a second dielectric layer 8 is formed on the device layer 7. The first dielectric layer 71 and the second dielectric layer 8 are made of silicon oxide. The second dielectric layer 8 is used for protecting the device layer 7.
Further, the embodiment also discloses a semiconductor device, which is prepared by the preparation method of the semiconductor device. Wherein the semiconductor device is a back-illuminated image sensor.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (10)
1. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
implanting P-type ions into the substrate to form a P-type doped layer;
etching the P-type doped layer to form a plurality of grooves at least penetrating through the P-type doped layer, wherein the grooves divide the P-type doped layer to form a plurality of P-type structures, and the width of each groove is larger than that of each P-type structure;
and growing an epitaxial structure in the groove, and carrying out N-type ion implantation on the epitaxial structure to form a plurality of N-type structures, wherein the N-type structures and the P-type structures are alternately arranged.
2. The method of manufacturing a semiconductor device according to claim 1, wherein the step of forming a plurality of trenches penetrating at least the P-type doped layer comprises:
sequentially forming a hard mask material layer and a photoresist layer on the P-type doping layer, wherein an opening is formed in the photoresist layer;
and etching the hard mask material layer by taking the photoresist layer as a mask to form a hard mask layer, etching the P-type doping layer by taking the hard mask layer as a mask, and extending the opening at least into the P-type doping layer to form the slot.
3. The method for manufacturing a semiconductor device according to claim 2, wherein the method for etching the hard mask layer and the P-type doped layer is dry etching, and an etching selection ratio of the etching gas for the dry etching to the P-type doped layer and the hard mask layer is greater than 10: 1.
4. The method of manufacturing a back semiconductor device according to claim 3, wherein the etching gas comprises: a mixture gas of hydrobromic acid gas, chlorine gas, hydrogen chloride gas and polyhalogen gas.
5. The method for manufacturing a semiconductor device according to claim 2, wherein before forming the photoresist layer, the method further comprises: forming a hard mask material layer on the substrate;
and, while etching the hard mask layer, the method further comprises: and etching the anti-reflection material layer to form an anti-reflection layer and extend the opening into the anti-reflection layer.
6. The method of manufacturing a semiconductor device according to claim 1, wherein a depth of the trench is 1.2 times to 1.5 times a thickness of the P-type structure.
7. The method of fabricating a semiconductor device according to claim 1, wherein growing an epitaxial structure within the trench comprises:
growing an initial epitaxial structure in the groove, and enabling the initial epitaxial structure to protrude out of the top surface of the P-type structure;
and performing a chemical mechanical polishing process on the initial epitaxial structure to remove at least a part of the initial epitaxial structure protruding out of the top surface of the P-type structure so as to form an epitaxial structure and make the top surface of the epitaxial structure and the top surface of the P-type structure flush.
8. The method of manufacturing a semiconductor device according to claim 7, wherein the initial epitaxial structure protrudes above the P-type structure by a height of
9. The method for manufacturing a semiconductor device according to claim 1, wherein the method for implanting P-type ions into the substrate comprises: executing a plurality of times of P-type ion implantation processes, wherein the depth of the P-type ion implantation into the substrate is gradually reduced; and/or the presence of a gas in the gas,
the method for implanting N-type ions into the substrate comprises the following steps: and executing a plurality of N-type ion implantation processes, wherein the depth of the N-type ion implantation into the substrate is gradually reduced.
10. The method for manufacturing a semiconductor device according to claim 1, wherein the P-type ions to be implanted include boron ions or boron difluoride ions; and, the implanted N-type ions include: a phosphorus ion.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110739263.4A CN113451343A (en) | 2021-06-30 | 2021-06-30 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110739263.4A CN113451343A (en) | 2021-06-30 | 2021-06-30 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113451343A true CN113451343A (en) | 2021-09-28 |
Family
ID=77814492
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110739263.4A Pending CN113451343A (en) | 2021-06-30 | 2021-06-30 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113451343A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150243763A1 (en) * | 2014-02-24 | 2015-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Performance boost by silicon epitaxy |
| CN104952896A (en) * | 2015-05-28 | 2015-09-30 | 格科微电子（上海）有限公司 | Manufacturing method of image sensor using deep trench isolation |
| US20160329365A1 (en) * | 2015-05-04 | 2016-11-10 | Semiconductor Components Industries, Llc | Pixel isolation regions formed with conductive layers |
| CN106229324A (en) * | 2016-09-14 | 2016-12-14 | 豪威科技(上海)有限公司 | Imageing sensor and preparation method thereof |
| CN107863361A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| US20180269237A1 (en) * | 2017-03-14 | 2018-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structure for reducing crosstalk between pixels and fabrication method thereof |
| US20190172860A1 (en) * | 2016-08-31 | 2019-06-06 | G-Ray Switzerland Sa | Electromagnetic radiation detector comprising charge transport across a bonded interface |
| CN111987116A (en) * | 2020-08-28 | 2020-11-24 | 上海华力微电子有限公司 | Backside illuminated image sensor and manufacturing method thereof |
-
2021
- 2021-06-30 CN CN202110739263.4A patent/CN113451343A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20150243763A1 (en) * | 2014-02-24 | 2015-08-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Performance boost by silicon epitaxy |
| US20160329365A1 (en) * | 2015-05-04 | 2016-11-10 | Semiconductor Components Industries, Llc | Pixel isolation regions formed with conductive layers |
| CN104952896A (en) * | 2015-05-28 | 2015-09-30 | 格科微电子（上海）有限公司 | Manufacturing method of image sensor using deep trench isolation |
| US20190172860A1 (en) * | 2016-08-31 | 2019-06-06 | G-Ray Switzerland Sa | Electromagnetic radiation detector comprising charge transport across a bonded interface |
| CN106229324A (en) * | 2016-09-14 | 2016-12-14 | 豪威科技(上海)有限公司 | Imageing sensor and preparation method thereof |
| CN107863361A (en) * | 2016-09-22 | 2018-03-30 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method and electronic installation |
| US20180269237A1 (en) * | 2017-03-14 | 2018-09-20 | Taiwan Semiconductor Manufacturing Co., Ltd. | Isolation structure for reducing crosstalk between pixels and fabrication method thereof |
| CN111987116A (en) * | 2020-08-28 | 2020-11-24 | 上海华力微电子有限公司 | Backside illuminated image sensor and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3193370B1 (en) | Method of manufacturing a cmos image sensor | |
| US8017425B2 (en) | Method for fabricating an image sensor capable of increasing photosensitivity | |
| KR101485653B1 (en) | Cmos image sensors and method for forming the same | |
| US8278130B2 (en) | Back side illumination image sensor and method for manufacturing the same | |
| US20220384496A1 (en) | Back-side deep trench isolation structure for image sensor | |
| US9368540B2 (en) | CIS image sensors with epitaxy layers and methods for forming the same | |
| US11869761B2 (en) | Back-side deep trench isolation structure for image sensor | |
| US8178913B2 (en) | Semiconductor device and method for manufacturing same | |
| JP5428479B2 (en) | Solid-state imaging device manufacturing method, solid-state imaging device, and electronic apparatus | |
| CN115004372A (en) | Structure and material engineering methods for signal-to-noise ratio enhancement of optoelectronic devices | |
| KR20180062441A (en) | High dielectric constant dielectric layer forming method, image sensor device, and manufacturing method thereof | |
| CN107425018B (en) | Method for manufacturing semiconductor device | |
| CN110112237B (en) | Method for manufacturing photodiode and corresponding photodiode | |
| CN113451343A (en) | Method for manufacturing semiconductor device | |
| CN113540140B (en) | Back-illuminated complementary metal oxide semiconductor image sensor and preparation method thereof | |
| US20150206789A1 (en) | Method of modifying polysilicon layer through nitrogen incorporation for isolation structure | |
| CN113471234B (en) | Semiconductor device and method for manufacturing the same | |
| CN115831989A (en) | Image sensor pixel with deep trench isolation structure | |
| CN113363274B (en) | Image sensor and method of manufacturing the same | |
| US20230131599A1 (en) | Image sensor pixel with deep trench isolation structure | |
| US20040043530A1 (en) | Methods of making shallow trench-type pixels for CMOS image sensors | |
| US20230420473A1 (en) | Deep trench isolation structure and methods for fabrication thereof | |
| US20220367245A1 (en) | Shallow trench isolation (sti) structure for cmos image sensor | |
| CN114743999A (en) | Forming method for image sensor and image sensor | |
| CN117334629A (en) | Semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210928 |
|
| RJ01 | Rejection of invention patent application after publication |