CN117334629A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN117334629A
CN117334629A CN202311240885.8A CN202311240885A CN117334629A CN 117334629 A CN117334629 A CN 117334629A CN 202311240885 A CN202311240885 A CN 202311240885A CN 117334629 A CN117334629 A CN 117334629A
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China
Prior art keywords
layer
deep trench
substrate
isolation
deep
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仇峰
廖黎明
胡林辉
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GTA Semiconductor Co Ltd
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GTA Semiconductor Co Ltd
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Priority to CN202311240885.8A priority Critical patent/CN117334629A/en
Publication of CN117334629A publication Critical patent/CN117334629A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure

Abstract

The invention provides a semiconductor device and a preparation method thereof. The invention realizes self-aligned ion implantation to form the deep well region connected with the buried layer by forming the initial groove with the bottom positioned on the buried layer in the process of forming the deep groove and using the mask plate for forming the deep groove, and no extra photomask is needed to be added in the traditional process; the isolation layer is formed on the side wall of the deep groove, the conductive structure which is filled in the deep groove and is in contact with the substrate at the bottom of the deep groove is further formed in the deep groove, so that the deep groove isolation structure has an isolation effect and a function of communicating the substrate, the substrate equipotential is improved, the application range is wide, and the deep groove isolation structure can be popularized to more technical platforms.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The invention relates to the technical field of semiconductors, in particular to a semiconductor device and a preparation method thereof.
Background
With the development of semiconductor technology, the feature size of semiconductor devices is smaller and smaller, and in particular, after the semiconductor process enters into a deep submicron stage, the trench isolation technology is becoming more and more important to realize high-integration and high-performance devices. The deep trench isolation structure (Deep Trench Oxide isolation, DTI for short) is a common high-voltage device isolation structure and is mainly applied to process platforms such as BCD, SGT, TVS and the like.
In the manufacture of transistors, such as PMOS, deep N-wells are implanted into a substrate to isolate the P-well from the P-type substrate. The existing technology generally adopts a special Mask (Mask) to carry out ion implantation to form a deep N well, thereby adding at least one Mask technology and improving the complexity and the cost of the manufacturing process. In addition, because the Aspect Ratio (AR) of the deep trench is large, when the oxide is filled in the deep trench to form the deep trench isolation structure, the oxide is not easy to fill to form a cavity, which affects the isolation capability of the device.
Please refer to fig. 1, which is a schematic diagram of a conventional deep trench isolation structure. As shown in fig. 1, deep trench isolation structures 19 are typically formed by etching a deep trench 101 into substrate 10 using hard mask structure 11 as a mask, and filling oxide 12. Because the depth-width ratio of the deep trench 101 is large, when the oxide 12 is filled in the deep trench 101, the oxide 12 is not easy to fill up to form the cavity 102, and the isolation capability of the device is affected.
Disclosure of Invention
The invention aims to solve the technical problem of providing a semiconductor device and a preparation method thereof, which can realize self-aligned ion implantation without adding an extra photomask to form a deep well region connected with a buried layer, and can also enable the prepared deep trench isolation structure to have an isolation effect and a function of communicating a substrate so as to improve the equipotential of the substrate.
In order to solve the above problems, the present invention provides a method for manufacturing a semiconductor device, the method comprising the steps of: providing a substrate, wherein a buried layer of a first conductivity type is formed in the substrate, and a patterned hard mask layer is formed on the surface of the substrate; etching the substrate to form an initial groove by taking the patterned hard mask layer as a mask plate and the buried layer as an etching stop layer; forming a deep well region of the first conductivity type covering the side wall and the bottom of the initial trench, wherein the deep well region is in contact with the buried layer; continuing etching along the initial trench to form a deep trench extending to the inside of the substrate below the buried layer; forming a first isolation layer in the deep trench and flattening to form a deep trench isolation structure
In some embodiments, the step of forming the deep trench isolation structure further comprises: forming the first isolation layer which at least continuously covers the side wall and the bottom of the deep trench; removing the first isolation layer at the bottom of the deep trench; and forming a conductive structure filling the deep trench, wherein the first isolation layer and the conductive structure in the deep trench jointly form the deep trench isolation structure, and the conductive structure is contacted with the substrate at the bottom of the deep trench.
In order to solve the above-described problems, the present invention also provides a semiconductor device including: a substrate, wherein a buried layer of a first conductivity type is formed in the substrate, a patterned hard mask layer is formed on the surface of the substrate, and the substrate is also provided with a deep trench extending to the inside of the substrate; a deep well region of a first conductivity type formed on a sidewall of the deep trench above the buried layer and in contact with the buried layer; and a deep trench isolation structure formed within the deep trench, the deep trench isolation structure including a first isolation layer covering the deep trench.
In some embodiments, the deep trench isolation structure further comprises a conductive structure; the first isolation layer covers the side wall of the deep trench and exposes the substrate at least at part of the bottom of the deep trench; the conductive structure fills the deep trench and contacts the substrate at the bottom of the deep trench.
According to the technical scheme, the initial trench with the bottom positioned on the buried layer is formed in the process of forming the deep trench, and the self-aligned ion implantation is realized by using the mask plate for forming the deep trench to form the deep well region connected with the buried layer, so that an additional photomask is not required to be added in the traditional process; the isolation layer is formed on the side wall of the deep groove, the conductive structure which is filled in the deep groove and is in contact with the substrate at the bottom of the deep groove is further formed in the deep groove, so that the deep groove isolation structure has an isolation effect and a function of communicating the substrate, the substrate equipotential is improved, the application range is wide, and the deep groove isolation structure can be popularized to more technical platforms.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments of the present invention will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the morphology of a prior deep trench isolation structure;
FIG. 2 is a schematic diagram illustrating steps of a method for fabricating a deep trench isolation structure according to an embodiment of the present invention;
fig. 3A to fig. 8D are schematic views of a device structure formed by main steps of a method for fabricating a deep trench isolation structure according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
An embodiment of the invention provides a method for manufacturing a semiconductor device.
Referring to fig. 2 to 8D together, fig. 2 is a schematic step diagram of a method for fabricating a deep trench isolation structure according to an embodiment of the present invention, and fig. 3A to 8D are schematic device structure diagrams formed by main steps of the method for fabricating a deep trench isolation structure according to an embodiment of the present invention.
As shown in fig. 2, the preparation method of the deep trench isolation structure according to the embodiment includes the following steps: s1, providing a substrate, wherein a buried layer of a first conductivity type is formed in the substrate, and a patterned hard mask layer is formed on the surface of the substrate; s2, etching the substrate to form an initial groove by taking the patterned hard mask layer as a mask and the buried layer as an etching stop layer; s3, forming a deep well region of the first conductivity type covering the side wall and the bottom of the initial trench, wherein the deep well region is in contact with the buried layer; s4, continuing etching along the initial groove to form a deep groove extending to the inside of the substrate below the buried layer; and S5, forming a first isolation layer in the deep trench and flattening to form a deep trench isolation structure.
Referring to step S1 and fig. 3B, a substrate 30 is provided, a buried layer 31 of a first conductivity type is formed in the substrate 30, and a patterned hard mask layer 32 is formed on the surface of the substrate 30.
The substrate 30 is used to support the device structure thereon. In this embodiment, the substrate 30 may include a Silicon (Si) substrate, a Germanium (Ge) substrate, a Silicon Germanium (SiGe) substrate, a Silicon-On-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, or the like; the substrate 30 may also be a stacked structure such as a silicon/silicon germanium stack or the like. In this embodiment, a silicon substrate is taken as an example of the substrate 30.
In the present embodiment, a buried layer (Burry) 31 of the first conductivity type is formed in the substrate 30. Specifically, the buried layer 31 may be formed by diffusing a highly doped region in the substrate 30 in a region immediately below the transistor structure, and then epitaxially growing an epitaxial layer thereon; the epitaxial layer is buried under the buried layer, and then a transistor is manufactured on the epitaxial layer. In some embodiments, the buried layer 31 may be an N-type buried layer.
In this embodiment, the patterned hard mask layer 32 includes a first dielectric layer 321 covering the substrate 30, a second dielectric layer 322 covering the first dielectric layer 321, and a third dielectric layer 323 covering the second dielectric layer 322. Specifically, the step of providing a substrate 30 further includes: (1) Providing a substrate 30, wherein a buried layer 31 of a first conductivity type is formed in the substrate 30, and a first dielectric material layer 3210, a second dielectric material layer 3220 covering the first dielectric material layer 3210, and a third dielectric material layer 3230 covering the second dielectric material layer 3220 are formed on the surface of the substrate 30, as shown in fig. 3A; (2) Forming a patterned photoresist layer 33 on the surface of the third dielectric material layer 3230, and etching the first dielectric material layer 3210, the second dielectric material layer 3220 and the third dielectric material layer 3230 by using the patterned photoresist layer 33 as a mask, to form a first dielectric layer 321, a second dielectric layer 322 and a third dielectric layer 323, where the first dielectric layer 321, the second dielectric layer 322 and the third dielectric layer 323 form a patterned hard mask layer 32, as shown in fig. 3B. Photoresists (PR) are also known as photoresists, which are organic compounds that are sensitive to light and change in solubility in a developer after exposure to ultraviolet light. The pattern on the mask can be transferred to the photoresist layer on the top layer of the wafer surface through the photoresist.
In some embodiments, the material of the first dielectric layer 321 is an oxide material (e.g., silicon dioxide), the material of the second dielectric layer 322 is a nitride material (e.g., silicon nitride), the material of the third dielectric layer 323 is an oxide material (e.g., silicon dioxide), and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer. The first dielectric layer 321 covers the top surface of the substrate 30, so that damage to the top surface of the substrate 30 caused by subsequent processes can be avoided. The second dielectric layer 322 may be used to improve the topography of subsequently formed device structures. The third dielectric layer 323 may be used as a barrier layer for a subsequent polishing process in which it is partially or completely removed.
Referring to step S2 and fig. 4, the substrate 30 is etched to expose a portion of the buried layer 31 by using the patterned hard mask layer 32 as a mask and the buried layer 31 as an etching stop layer, so as to form an initial trench 301. The angle at which the initial trench 301 is etched may be set according to design requirements.
Referring to step S3 and fig. 5, a deep well region 34 of the first conductivity type is formed to cover the sidewall and bottom of the initial trench 301, and the deep well region 34 is in contact with the buried layer 31. Specifically, the deep well region 34 may be formed along with etching the mask for forming the initial trench 301, so that a photomask process is not required to be added.
In some embodiments, step S3 further comprises: ion implantation of the first conductivity type is performed on the sidewall and the bottom of the initial trench 301 by using an oblique implantation method, so as to form the deep well region 34. The deep well region 34 is in contact with the buried layer 31 and has the same conductivity type, so that a U-shaped semi-enclosed isolation ring is formed in the substrate 30, and isolation is formed between a well region formed in the isolation ring and a same type substrate. Specifically, the patterned hard mask layer 32 is used as a mask, and an oblique angle implantation mode is adopted to form the deep well region 34. An "angled implant" is defined as an implant that has an angle of incidence other than at right angles to the substrate 30, i.e., an angle of incidence other than 90 °. Thus, an "angled implant" refers to an implant having an angle of incidence with the substrate 30 between 0 ° and less than 90 °, and more particularly between 5 ° and about 15 °.
In some embodiments, the deep well region 34 is a deep N-well region, and the buried layer is an N-type buried layer. The deep N well region and the N type buried layer form a semi-enclosed N type isolation ring in the substrate 30, so that the P well and the P type substrate can be isolated, and the PMOS transistor can be manufactured conveniently. For example, a mask for forming the initial trench 301 is etched, and N-type ions are implanted, so that a deep N-well region is formed on the sidewall and the bottom of the initial trench 301; the deep N well region is contacted with the N type buried layer. The angled implant may be performed using N-type dopants such As arsenic (As), phosphorus (P), etc.
Referring to step S4 and fig. 6, etching is continued along the initial trench 301 to form a deep trench 309 extending into the substrate 30 below the buried layer 31. The deep trench 309 may be formed by continuing etching along the initial trench 301 using the patterned photoresist layer 33 and the patterned hard mask layer 32 as a mask. After the patterned photoresist layer 33 is removed, the patterned hard mask layer 32 may be used as a mask, and etching may be continued along the initial trench 301 to form the deep trench 309. The depth and angle of the deep trench 309 etch as the target trench may be set according to design requirements.
In some embodiments, referring to step S5 and fig. 7, a first isolation layer 35 is formed in the deep trench 309 and planarized to form a deep trench isolation structure. In this embodiment, the first isolation layer 35 filling the deep trench 309 is formed and planarized, and the first isolation layer 35 within the deep trench 309 constitutes the deep trench isolation structure. The first isolation layer 35 may be formed by atomic deposition.
Because the Aspect Ratio (AR) of the deep trench is large, when the deep trench is filled with the deposited isolation material to form the deep trench isolation structure, the isolation material may not be filled easily to form a cavity, which affects the isolation capability of the device. To this end, the present invention provides further improvements in deep trench isolation structures.
In some embodiments, the step of forming the deep trench isolation structure of step S5 further comprises: s51, forming the first isolation layer 35 continuously covering at least the sidewalls 3091 and the bottom 3092 of the deep trench 309, as shown in fig. 8A; s52, removing the first isolation layer 35 located at the bottom 3092 of the deep trench 309, as shown in fig. 8B; s53, forming a conductive structure 36 filling the deep trench 309, where the first isolation layer 35 and the conductive structure 36 in the deep trench 309 together form the deep trench isolation structure 39, and the conductive structure 36 contacts the substrate 30 at the bottom 3092 of the deep trench 309, as shown in fig. 8D.
Referring to step S51 and fig. 8A, the first isolation layer 35 is formed to continuously cover at least the sidewalls 3091 and the bottom 3092 of the deep trench 309.
In some embodiments, the step of forming the first isolation layer 35 covering at least the sidewalls 3091 and the bottom 3092 of the deep trench 309 further comprises: silicon consumption growth is performed by thermal oxidation, and an oxide layer (e.g., a silicon dioxide film) is formed as the first isolation layer 35, which continuously covers at least the sidewalls 3091 and the bottom 3092 of the deep trench 309. In some embodiments, TEOS (tetraethoxysilane, also known as tetraethyl silicate) can be used as a silicon source, and silicon-consuming growth is performed by adopting a thermal oxidation mode to generate a silicon dioxide film; the film can be used as a dielectric layer, an isolation layer and a protective layer. Specifically, the first isolation layer 35 also covers the surface of the hard mask layer 32.
Referring to step S52 and fig. 8B, the first isolation layer 35 at the bottom 3092 of the deep trench 309 is removed. In this embodiment, the step of removing the first isolation layer 35 located at the bottom 3092 of the deep trench 309 further comprises: the first isolation layer 35 at the bottom 3092 of the deep trench 309 is removed by a mask-less Etch. Because the thickness of the first isolation layer 35 at the bottom 3092 of the deep trench 309 is thinner and is far smaller than the thickness of the film layer on the surface of the substrate 30 in the base, the first isolation layer 35 at the bottom 3092 of the deep trench 309 can be removed by etching without a mask, while the film layers at other parts are not affected basically, so that no additional mask is required to be added in the conventional process, the application range is wide, and the method can be popularized to more technical platforms.
Referring to step S53 and fig. 8D, a conductive structure 36 is formed to fill the deep trench 309, the first isolation layer 35 and the conductive structure 36 in the deep trench 309 together form the deep trench isolation structure 39, and the conductive structure 36 contacts the substrate 30 at the bottom 3092 of the deep trench 309. Since the deep trench isolation structure 39 includes the first isolation layer 35 formed in the deep trench 309 and the conductive structure 36 contacting the substrate 30, the deep trench isolation structure 39 has an isolation effect and a function of communicating with the substrate, and thus the substrate equipotential is improved.
In this embodiment, the first isolation layer 35 further covers the surface of the hard mask layer 32, and the step of forming the conductive structure filling the deep trench further includes: forming a conductive material layer 360 filled in the deep trench 309, contacting the substrate 30 at the bottom 3092 of the deep trench 309, and covering the surface of the first isolation layer 35 by in-situ doping of polysilicon, as shown in fig. 8C; the first isolation layer 35 and the conductive material layer 360 on the surface of the hard mask layer 32 are removed by polishing, and the conductive material layer 360 remaining in the deep trench 309 serves as the conductive structure 36, as shown in fig. 8D. The top surface of the deep trench isolation structure 39 is substantially flush with the surface of the remaining hard mask layer 32, specifically the surface of the second dielectric layer 322. In-situ doping is a doping method in which impurities are doped in raw materials for preparing the material, namely doping and material preparation are carried out simultaneously; in-situ doping of polysilicon is to deposit polysilicon while introducing a gas containing impurities. The planarization is performed by a polishing process, specifically, a Chemical Mechanical Polishing (CMP) process; excess polysilicon and oxide are polished off by CMP to form a planar surface. In this embodiment, the third dielectric layer 323 is removed entirely during the polishing process.
Based on the same inventive concept, an embodiment of the present invention also provides a semiconductor device.
Fig. 7 is a schematic diagram of a semiconductor device according to an embodiment of the invention. As shown in fig. 7, the semiconductor device provided in this embodiment includes: substrate 30, buried layer 31, deep well region 34, and a deep trench isolation structure comprising a first isolation layer 35.
Specifically, the substrate 30 has a buried layer 31 of the first conductivity type formed therein, and the substrate 30 further has a deep trench 309 extending into the substrate 30; the deep well region 34 has a first conductivity type, and the deep well region 34 is formed on the sidewall of the deep trench 309 above the buried layer 31 and is in contact with the buried layer 31; the first isolation layer 35 fills the deep trench 309, forming the deep trench isolation structure.
Since the deep well region 34 is in contact with the buried layer 31 and has the same conductivity type, a U-shaped semi-enclosed isolation ring is formed in the substrate 30, so that isolation is formed between a well region formed in the isolation ring and a same type substrate.
In some embodiments, the buried layer 31 is an N-type buried layer, the deep well region 34 is a deep N-well region, and the material of the first isolation layer 35 is an oxide material. The deep N well region and the N type buried layer form a semi-enclosed N type isolation ring in the substrate 30, so that the P well and the P type substrate can be isolated, and the PMOS transistor can be manufactured conveniently.
Fig. 8D is a schematic diagram of a semiconductor device according to another embodiment of the invention. As shown in fig. 8D, the semiconductor device provided in this embodiment includes: substrate 30, buried layer 31, deep well region 34, and a deep trench isolation structure comprising a first isolation layer 35 and a conductive structure 36.
Specifically, the substrate 30 has a buried layer 31 of the first conductivity type formed therein, and the substrate 30 further has a deep trench 309 extending into the substrate 30. The deep well region 34 has a first conductivity type, and the deep well region 34 is formed on a sidewall of the deep trench 309 above the buried layer 31 and is in contact with the buried layer 31. The deep trench isolation structure 39 is formed within the deep trench 309 and includes a first isolation layer 35 and a conductive structure 36; the first isolation layer 35 covers the sidewalls 3091 of the deep trench 309 and exposes the substrate 30 at least partially at the bottom 3092 of the deep trench 309; the conductive structure 36 fills the deep trench 309 and contacts the substrate 30 at the bottom 3092 of the deep trench 309, increasing the substrate 30 equipotential.
In some embodiments, the buried layer 31 is an N-type buried layer, and the deep well region 34 is a deep N-well region. The deep N well region and the N type buried layer form a semi-enclosed N type isolation ring in the substrate 30, so that the P well and the P type substrate can be isolated, and the PMOS transistor can be manufactured conveniently.
In some embodiments, the material of the first isolation layer 35 is an oxide material, and the material of the conductive structure 36 is doped polysilicon. Since the deep trench isolation structure 39 includes an oxide isolation layer formed in the deep trench 309 and doped polysilicon in contact with the substrate 30, the deep trench isolation structure 39 has an isolation effect, and also has a function of communicating with the substrate, thereby improving the substrate equipotential.
In this embodiment, the top surface of the deep trench isolation structure 39 is substantially flush with the surface of the remaining hard mask layer 32 (specifically, the surface of the second dielectric layer 322).
In the above description, descriptions of well-known components and techniques are omitted so as to not unnecessarily obscure the present invention. In the foregoing embodiments, each embodiment is mainly described for differences from other embodiments, and the same/similar parts between the embodiments are referred to each other.
According to the embodiment, the isolation layer is formed on the side wall of the deep groove, the conductive structure which fills the deep groove and is in contact with the substrate at the bottom of the deep groove is formed in the deep groove, and the isolation layer and the conductive structure in the deep groove jointly form the deep groove isolation structure, so that the deep groove isolation structure has an isolation effect, has a function of communicating the substrate, and improves the substrate equipotential. In addition, the process does not need to add an extra photomask on the traditional process, has wide application range and can be popularized to more technical platforms.
It should be noted that in this document, relational terms such as "first" and "second" are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, the statement "comprises" and "comprising" does not exclude the presence of other elements than those listed in any process, method, article, or apparatus that comprises the element. In addition, the embodiments of the present invention and the features in the embodiments may be combined with each other without collision.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. It should be noted that modifications and adaptations to the present invention may occur to one skilled in the art without departing from the principles of the present invention and are intended to be comprehended within the scope of the present invention.

Claims (12)

1. A method of manufacturing a semiconductor device, the method comprising the steps of:
providing a substrate, wherein a buried layer of a first conductivity type is formed in the substrate, and a patterned hard mask layer is formed on the surface of the substrate;
etching the substrate to form an initial groove by taking the patterned hard mask layer as a mask plate and the buried layer as an etching stop layer;
forming a deep well region of the first conductivity type covering the side wall and the bottom of the initial trench, wherein the deep well region is in contact with the buried layer;
continuing etching along the initial trench to form a deep trench extending to the inside of the substrate below the buried layer; and
and forming a first isolation layer in the deep trench and flattening to form a deep trench isolation structure.
2. The method of claim 1, wherein the step of forming a deep well region of the first conductivity type covering sidewalls and bottom of the initial trench further comprises:
and performing ion implantation of a first conduction type on the side wall and the bottom of the initial groove by adopting an oblique angle implantation mode to form the deep well region.
3. The method of claim 1, wherein the step of forming a deep trench isolation structure further comprises:
and forming and flattening the first isolation layer filled in the deep trench, wherein the first isolation layer in the deep trench forms the deep trench isolation structure.
4. The method of claim 1, wherein the step of forming a deep trench isolation structure further comprises:
forming the first isolation layer which at least continuously covers the side wall and the bottom of the deep trench;
removing the first isolation layer at the bottom of the deep trench;
and forming a conductive structure filling the deep trench, wherein the first isolation layer and the conductive structure in the deep trench jointly form the deep trench isolation structure, and the conductive structure is contacted with the substrate at the bottom of the deep trench.
5. The method of claim 4, wherein the step of forming a first isolation layer covering at least sidewalls and a bottom of the deep trench further comprises:
and performing silicon consumption growth in a thermal oxidation mode, and forming an oxide layer which at least continuously covers the side wall and the bottom of the deep trench as the first isolation layer.
6. The method of claim 4, wherein the step of removing the first isolation layer at the bottom of the deep trench further comprises:
and removing the first isolation layer at the bottom of the deep trench in a non-mask etching mode.
7. The method of claim 4, wherein the first isolation layer further covers the hard mask layer surface;
the step of forming a conductive structure filling the deep trench further comprises:
forming a conductive material layer which fills the deep trench, is in contact with the substrate at the bottom of the deep trench and covers the surface of the first isolation layer by adopting an in-situ doped polysilicon mode;
and grinding and removing the first isolation layer and the conductive material layer on the surface of the hard mask layer, wherein the conductive material layer remained in the deep trench is used as the conductive structure.
8. The method of claim 1, wherein the hard mask layer comprises a first dielectric layer overlying the substrate, a second dielectric layer overlying the first dielectric layer, and a third dielectric layer overlying the second dielectric layer.
9. The method of claim 8, wherein the substrate is a silicon substrate, the material of the first dielectric layer is an oxide material, the material of the second dielectric layer is a nitride material, the material of the first dielectric layer is an oxide material, and the thickness of the second dielectric layer is greater than the thickness of the first dielectric layer.
10. A semiconductor device, comprising:
a substrate, wherein a buried layer of a first conductivity type is formed in the substrate, a patterned hard mask layer is formed on the surface of the substrate, and the substrate is also provided with a deep trench extending to the inside of the substrate;
a deep well region of a first conductivity type formed on a sidewall of the deep trench above the buried layer and in contact with the buried layer; and
and the deep trench isolation structure is formed in the deep trench and comprises a first isolation layer covering the deep trench.
11. The semiconductor device of claim 10, wherein the deep trench isolation structure further comprises a conductive structure;
the first isolation layer covers the side wall of the deep trench and exposes the substrate at least at part of the bottom of the deep trench;
the conductive structure fills the deep trench and contacts the substrate at the bottom of the deep trench.
12. The semiconductor device of claim 11, wherein the buried layer is an N-type buried layer, the deep well region is a deep N-well region, the material of the first isolation layer is an oxide material, and the material of the conductive structure is doped polysilicon.
CN202311240885.8A 2023-09-22 2023-09-22 Semiconductor device and method for manufacturing the same Pending CN117334629A (en)

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