CN107863361A - A kind of semiconductor devices and its manufacture method and electronic installation - Google Patents
A kind of semiconductor devices and its manufacture method and electronic installation Download PDFInfo
- Publication number
- CN107863361A CN107863361A CN201610843991.9A CN201610843991A CN107863361A CN 107863361 A CN107863361 A CN 107863361A CN 201610843991 A CN201610843991 A CN 201610843991A CN 107863361 A CN107863361 A CN 107863361A
- Authority
- CN
- China
- Prior art keywords
- layer
- deep trench
- epitaxial layer
- isolation structure
- trench isolation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 118
- 238000000034 method Methods 0.000 title claims abstract description 114
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 48
- 238000009434 installation Methods 0.000 title claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 161
- 239000000758 substrate Substances 0.000 claims abstract description 59
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 48
- 229920005591 polysilicon Polymers 0.000 claims abstract description 48
- 239000011248 coating agent Substances 0.000 claims abstract description 32
- 238000000576 coating method Methods 0.000 claims abstract description 32
- 230000026267 regulation of growth Effects 0.000 claims abstract description 5
- 239000000463 material Substances 0.000 claims description 80
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 70
- 229920002120 photoresistant polymer Polymers 0.000 claims description 37
- 239000012774 insulation material Substances 0.000 claims description 32
- 238000000059 patterning Methods 0.000 claims description 31
- 239000000377 silicon dioxide Substances 0.000 claims description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 18
- 229910052710 silicon Inorganic materials 0.000 claims description 18
- 239000010703 silicon Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 230000008021 deposition Effects 0.000 claims description 11
- 230000002093 peripheral effect Effects 0.000 claims description 11
- 230000004888 barrier function Effects 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 6
- 125000006850 spacer group Chemical group 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000011049 filling Methods 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 368
- 239000007789 gas Substances 0.000 description 34
- 229910052751 metal Inorganic materials 0.000 description 24
- 239000002184 metal Substances 0.000 description 24
- 238000005530 etching Methods 0.000 description 22
- 229910052581 Si3N4 Inorganic materials 0.000 description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 21
- 239000012212 insulator Substances 0.000 description 20
- 239000011229 interlayer Substances 0.000 description 20
- 238000006243 chemical reaction Methods 0.000 description 18
- 230000008569 process Effects 0.000 description 17
- 239000011521 glass Substances 0.000 description 16
- 239000011810 insulating material Substances 0.000 description 15
- 238000001020 plasma etching Methods 0.000 description 15
- -1 a-C Chemical compound 0.000 description 12
- MWUXSHHQAYIFBG-UHFFFAOYSA-N nitrogen oxide Inorganic materials O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 12
- 238000001312 dry etching Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 10
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 8
- CPELXLSAUQHCOX-UHFFFAOYSA-N Hydrogen bromide Chemical compound Br CPELXLSAUQHCOX-UHFFFAOYSA-N 0.000 description 8
- 229910052796 boron Inorganic materials 0.000 description 8
- 238000005229 chemical vapour deposition Methods 0.000 description 8
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 8
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 8
- 238000001289 rapid thermal chemical vapour deposition Methods 0.000 description 8
- 239000000126 substance Substances 0.000 description 8
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 8
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 8
- 239000004744 fabric Substances 0.000 description 7
- 235000015220 hamburgers Nutrition 0.000 description 7
- 239000012535 impurity Substances 0.000 description 7
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 6
- 229910017214 AsGa Inorganic materials 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 229910052721 tungsten Inorganic materials 0.000 description 6
- 230000003287 optical effect Effects 0.000 description 5
- 230000005693 optoelectronics Effects 0.000 description 5
- 239000012071 phase Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 description 4
- 239000006173 Good's buffer Substances 0.000 description 4
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 4
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 4
- XSKXPHGJRMYISG-UHFFFAOYSA-N [Si](OCC)(OCC)(OCC)OCC.[P] Chemical compound [Si](OCC)(OCC)(OCC)OCC.[P] XSKXPHGJRMYISG-UHFFFAOYSA-N 0.000 description 4
- 230000009471 action Effects 0.000 description 4
- 230000003321 amplification Effects 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 229910052790 beryllium Inorganic materials 0.000 description 4
- 229910052793 cadmium Inorganic materials 0.000 description 4
- 229910052804 chromium Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 4
- 239000007792 gaseous phase Substances 0.000 description 4
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 229910000042 hydrogen bromide Inorganic materials 0.000 description 4
- 238000003384 imaging method Methods 0.000 description 4
- 238000010884 ion-beam technique Methods 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 229910052749 magnesium Inorganic materials 0.000 description 4
- 238000003801 milling Methods 0.000 description 4
- 229910052750 molybdenum Inorganic materials 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 229910052763 palladium Inorganic materials 0.000 description 4
- 229910052698 phosphorus Inorganic materials 0.000 description 4
- 239000011574 phosphorus Substances 0.000 description 4
- 230000005622 photoelectricity Effects 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910052709 silver Inorganic materials 0.000 description 4
- 239000004332 silver Substances 0.000 description 4
- 230000003068 static effect Effects 0.000 description 4
- 229910052718 tin Inorganic materials 0.000 description 4
- 229910052719 titanium Inorganic materials 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 229910052725 zinc Inorganic materials 0.000 description 4
- 229910052726 zirconium Inorganic materials 0.000 description 4
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 3
- 238000000407 epitaxy Methods 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 229910052753 mercury Inorganic materials 0.000 description 3
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 229910052582 BN Inorganic materials 0.000 description 2
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 2
- 229920001665 Poly-4-vinylphenol Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 239000004793 Polystyrene Substances 0.000 description 2
- 229910020177 SiOF Inorganic materials 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 2
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 239000000872 buffer Substances 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 2
- 229910052731 fluorine Inorganic materials 0.000 description 2
- 239000011737 fluorine Substances 0.000 description 2
- 125000001153 fluoro group Chemical group F* 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 238000000608 laser ablation Methods 0.000 description 2
- 238000003701 mechanical milling Methods 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229920002223 polystyrene Polymers 0.000 description 2
- 229910000077 silane Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000004528 spin coating Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000031709 bromination Effects 0.000 description 1
- 238000005893 bromination reaction Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 1
- 150000003949 imides Chemical class 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 1
- 229910017464 nitrogen compound Inorganic materials 0.000 description 1
- 150000002830 nitrogen compounds Chemical class 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
Abstract
The present invention provides a kind of semiconductor devices and its manufacture method and electronic installation, is related to technical field of semiconductors.This method includes：Semiconductor substrate is provided, includes some predetermined regions as photodiode region formed with the first epitaxial layer, first epitaxial layer on a semiconductor substrate；In the first epitaxial layer deep trench is formed between adjacent photodiode area；Laying is formed on the bottom of deep trench and side wall；Polysilicon layer is formed in deep trench, the top surface of the polysilicon layer is less than the top surface of the first extension, to be partially filled with deep trench；Coating is formed on the polysilicon layer in deep trench, deep trench isolation structure is formed to fill full deep trench；The epitaxial layer of growth regulation two on the surface of the first epitaxial layer, and the top surface of the second epitaxial layer is higher than the top surface of deep trench isolation structure.The method according to the invention, the isolation performance between adjacent photodiode is improved, improve the performance and yield of device.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its manufacture method and electronics
Device.
Background technology
In technical field of semiconductors, imaging sensor is a kind of semiconductor device that optical imagery can be converted into electric signal
Part.Imaging sensor can generally be divided into charge coupled cell (CCD) and complementary metal oxide semiconductor (CMOS) image
Sensor.The advantages of ccd image sensor is higher to image sensitivity, and noise is small, but ccd image sensor and other devices
Part it is integrated relatively difficult, and the power consumption of ccd image sensor is higher.By contrast, cmos image sensor has technique
Simply, easily integrated with other devices, small volume, in light weight, small power consumption, low cost and other advantages.Cmos image sensor quilt at present
It is widely used in digital camera, camera cell phone, DV, medical camera device (such as gastroscope), automobile-used camera device
Among field.
Figure 1A to Fig. 1 C is refer to, Figure 1A to Fig. 1 C is a kind of structural representation of existing cmos image sensor, existing
Some cmos image sensors include Semiconductor substrate, some pixel lists in matrix arrangement in the Semiconductor substrate
Member and shallow trench isolation (STI) 11 between adjacent pixel cell, each pixel cell generally include photoelectricity
Diode 10 and transistor, photodiode 10 are used for opto-electronic conversion, and transistor is used for the telecommunications for changing photodiode 10
Number amplification after export.The shallow trench isolation 11 is used for the isolation of adjacent pixel, also simultaneously as between adjacent photodiode
Isolation, also injected in addition in common process usually using VTNH, between adjacent photodiode 10 in the semiconductor substrate
VTNH injection regions 12 are formed, VTNH injection regions 12 are also used as the isolation between adjacent photodiode.Wherein, incident light
(as shown in arrow in Figure 1A and Figure 1B) enters in pixel cell from the front of Semiconductor substrate, incident photon (Incidence
Photons) scheduled photodiode is captured so as to produce photoelectron, and photoelectron is by the n+ layers of the predetermined photodiode
Collect.
Generally by the method for the well depth for increasing photodiode region, to improve the performance of photodiode and scope.Such as
Shown in Figure 1B, it is the schematic diagram after the well depth for adding photodiode region, after the well depth of photodiode region is added,
STI depth should be increased preferably to isolate photodiode, but the etching of groove that fab is isolated for shallow trench
The isolating power of ability and VTNH ion implantings is very limited, and normal sti trench trench etch and VTNH ion implantings can not reach
To deeper depth, it is thus impossible to be isolated well to the photodiode region with deeper well depth, cause adjacent light
The problem of electrical crosstalk (electrical crosstalk) occurs between electric diode, and electrical crosstalk is mainly entered by photoelectron
Enter caused by the photodiode adjacent with predetermined photodiode, the appearance of cross-interference issue can influence cmos image sensor
The quality of the image of final output, crosstalk is bigger, and the quality of the image of final output is poorer.
Therefore, it is necessary to a kind of semiconductor devices and its manufacture method are proposed, to solve above-mentioned technical problem.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will enter in specific embodiment part
One step describes in detail.The Summary of the present invention is not meant to attempt to limit technical scheme claimed
Key feature and essential features, the protection domain for attempting to determine technical scheme claimed is not meant that more.
In view of the shortcomings of the prior art, a kind of manufacture method of semiconductor devices is provided in the embodiment of the present invention one, including：
Semiconductor substrate is provided, included on the semiconductor substrate formed with the first epitaxial layer, first epitaxial layer
Some predetermined regions as photodiode region；
In first epitaxial layer deep trench is formed between the adjacent photodiode region；
Laying is formed on the bottom of the deep trench and side wall；
Polysilicon layer is formed in the deep trench, the top surface of the polysilicon layer is less than the top surface of first extension, with
It is partially filled with the deep trench；
Coating is formed on the polysilicon layer in the deep trench, deep trench is formed to fill the full deep trench
Isolation structure；
The epitaxial layer of growth regulation two on the surface of first epitaxial layer, and the top surface of second epitaxial layer is higher than institute
State the top surface of deep trench isolation structure.
Further, the method for forming the deep trench comprises the following steps：
Sacrifice layer and hard mask layer are sequentially formed on the surface of first epitaxial layer；
The photoresist layer of patterning is formed on the hard mask layer, the photoresist layer of the patterning includes some open
Mouthful, the positions and dimensions of the predetermined deep trench formed of opening definition；
Using the photoresist layer of the patterning as mask, the hard mask layer, the sacrifice layer and part institute are etched successively
The first epitaxial layer is stated, to form the deep trench between the adjacent photodiode region in first epitaxial layer.
Further, the method for forming the polysilicon layer comprises the following steps：
Deposition forms polysilicon layer, to fill the deep trench, and spills into the top of the hard mask layer；
Etch-back removes the part polysilicon layer, so that the top of the remaining polysilicon layer is less than outside described first
Prolong the top surface of layer.
Further, the method for forming the coating comprises the following steps：
Deposition forms coating on the hard mask layer and in the deep trench；
Planarization is carried out to the coating to stop on the hard mask layer；
Remove the hard mask layer and the sacrifice layer.
Further, formed and the deep trench isolation knot in peripheral virtual pixel area in the front of second epitaxial layer
The contact hole of structure electrical connection, negative pressure is electrically connected to by the deep trench isolation structure in peripheral virtual pixel area.
Further, the material of the sacrifice layer includes oxide, the material of the hard mask layer include SiN, a-C, BN and
One or more in SiON.
Further, the material of the coating includes silica, and the material of the laying includes silica.
The embodiment of the present invention two provides a kind of manufacture method of semiconductor devices, and methods described includes：
Semiconductor substrate is provided；
Insulation material layer is formed on the semiconductor substrate；
The insulation material layer is patterned, to be formed to each other by some deep trench isolation structures of separated by openings, wherein,
Some deep trench isolation structures are respectively arranged between adjacent photodiode region；
The first epitaxial layer is formed on the semiconductor substrate, and first epitaxial layer fills adjacent deep trenches isolation structure
Between opening, and the top surface of first epitaxial layer be higher than the deep trench isolation structure top surface.
Further, before the insulation material layer is formed, in addition to the is formed on the surface of the Semiconductor substrate
The step of two epitaxial layers.
Further, the method for forming the deep trench isolation structure comprises the following steps：
Hard mask layer is formed on the surface of the insulation material layer；
The photoresist layer of patterning is formed on the hard mask layer, the photoresist layer definition of the patterning is predetermined to be formed
Deep trench isolation structure pattern；
Using the photoresist layer of the patterning as mask, the hard mask layer and spacer material layer are etched successively, is stopped at
In the Semiconductor substrate, to be formed to each other by some deep trench isolation structures of separated by openings；
And the photoresist layer and the hard mask layer are removed.
Further, the material of the insulation material layer includes silica.
Further, the material of the hard mask layer includes the one or more in SiN, a-C, BN and SiON.
Further, the thickness range of the insulation material layer is 3000~30000 angstroms.
Another aspect of the present invention also provides a kind of semiconductor devices, including：
Semiconductor substrate, the epitaxial layer being formed in the Semiconductor substrate, and if being formed in the epitaxial layer
Dry photodiode region, and the deep trench isolation knot in the epitaxial layer being arranged between the adjacent photodiode region
Structure, wherein, the top surface of the deep trench isolation structure is less than the top surface of the epitaxial layer.
Further, the deep trench isolation structure includes the polysilicon layer of filling, and surrounds the polysilicon layer surrounding
The insulating barrier on surface.
Further, the insulating barrier includes the laying for surrounding the polysilicon layer bottom and side wall, and positioned at described
Coating on polysilicon layer top surface.
Further, the material of the coating includes silica, and the material of the laying includes silica.
Further, the epitaxial layer front formed with peripheral virtual pixel area in the deep trench isolation structure
The contact hole of electrical connection, the deep trench isolation structure in peripheral virtual pixel area is electrically connected to negative pressure.
Further, the deep trench isolation structure is made up of insulation material layer.
Further, the material of the insulation material layer includes silica.
Further aspect of the present invention also provides a kind of electronic installation, and it includes foregoing semiconductor devices.
Manufacturing method according to the invention, using deep trench isolation structure, improve between adjacent photodiode every
From performance, the appearance of cross-interference issue between the deeper adjacent photodiode of well depth is avoided, and then improves the performance of device
And yield.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.Shown in the drawings of this hair
Bright embodiment and its description, for explaining the principle of the present invention.
In accompanying drawing：
Figure 1A-Fig. 1 C show a kind of structural representation of existing cmos image sensor, wherein, Figure 1B is to add
Schematic diagram after the well depth of photodiode region, Fig. 1 C are the top view of the structure of cmos image sensor；
Fig. 2A to Fig. 2 K shows a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention
The sectional view of the structure of formation；
Fig. 3 A to Fig. 3 G show a kind of related step of the manufacture method of semiconductor devices in another embodiment of the present invention
Suddenly the sectional view of the structure formed；
Fig. 4 shows a kind of indicative flowchart of the manufacture method of semiconductor devices of one embodiment of the invention；
Fig. 5 shows a kind of indicative flowchart of the manufacture method of semiconductor devices of another embodiment of the present invention；
Fig. 6 A and Fig. 6 B show a kind of structural representation of semiconductor devices in one embodiment of the invention, wherein,
Fig. 6 A are sectional view, and Fig. 6 B are top view；
Fig. 7 A and Fig. 7 B show a kind of structural representation of semiconductor devices in another embodiment of the present invention, its
In, Fig. 7 A are sectional view, and Fig. 7 B are top view；
Fig. 8 shows the schematic diagram of the electronic installation in one embodiment of the invention.
Embodiment
In the following description, a large amount of concrete details are given to provide more thorough understanding of the invention.So
And it is obvious to the skilled person that the present invention can be able to without one or more of these details
Implement.In other examples, in order to avoid obscuring with the present invention, do not enter for some technical characteristics well known in the art
Row description.
It should be appreciated that the present invention can be implemented in different forms, and it should not be construed as being limited to what is proposed here
Embodiment.On the contrary, providing these embodiments disclosure will be made thoroughly and complete, and will fully convey the scope of the invention to
Those skilled in the art.In the accompanying drawings, for clarity, the size and relative size in Ceng He areas may be exaggerated.From beginning to end
Same reference numerals represent identical element.
It should be understood that when element or layer be referred to as " ... on ", " with ... it is adjacent ", " being connected to " or " being coupled to " it is other
When element or layer, its can directly on other elements or layer, it is adjacent thereto, be connected or coupled to other elements or layer, or
Person may have element or layer between two parties.On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " directly
It is connected to " or when " being directly coupled to " other elements or layer, then element or layer between two parties is not present.It should be understood that although it can make
Various elements, part, area, floor and/or part are described with term first, second, third, etc., these elements, part, area, floor and/
Or part should not be limited by these terms.These terms be used merely to distinguish an element, part, area, floor or part with it is another
One element, part, area, floor or part.Therefore, do not depart from present invention teach that under, the first element discussed below, portion
Part, area, floor or part are represented by the second element, part, area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... under ", " ... it
On ", " above " etc., herein can for convenience description and by using so as to describe an element shown in figure or feature with
The relation of other elements or feature.It should be understood that in addition to the orientation shown in figure, spatial relationship term is intended to also include making
With the different orientation with the device in operation.For example, if the device upset in accompanying drawing, then, is described as " under other elements
Face " or " under it " or " under it " element or feature will be oriented to other elements or feature " on ".Therefore, exemplary art
Language " ... below " and " ... under " it may include upper and lower two orientations.Device can additionally be orientated (be rotated by 90 ° or its
It is orientated) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as the limitation of the present invention.Make herein
Used time, " one " of singulative, "one" and " described/should " be also intended to include plural form, unless context is expressly noted that separately
Outer mode.It is also to be understood that term " composition " and/or " comprising ", when in this specification in use, determining the feature, whole
Number, step, operation, the presence of element and/or part, but be not excluded for one or more other features, integer, step, operation,
The presence or addition of element, part and/or group.Herein in use, term "and/or" includes any and institute of related Listed Items
There is combination.
Describe to send out herein with reference to the cross-sectional view of the schematic diagram of the desirable embodiment (and intermediate structure) as the present invention
Bright embodiment.As a result, it is contemplated that due to caused by such as manufacturing technology and/or tolerance from the change of shown shape.Therefore,
Embodiments of the invention should not necessarily be limited to the given shape in area shown here, but including due to for example manufacturing caused shape
Shape deviation.For example, it is shown as that the injection region of rectangle generally has circle at its edge or bending features and/or implantation concentration ladder
Degree, rather than the binary change from injection region to non-injection regions.Equally, the disposal area can be caused by injecting the disposal area formed
Some injections in area between the surface passed through during injection progress.Therefore, the area shown in figure is substantially schematic
, their shape is not intended the true form in the area of display device and is not intended to limit the scope of the present invention.
In order to thoroughly understand the present invention, detailed step and detailed structure will be proposed in following description, so as to
Explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail as follows, but except these detailed descriptions
Outside, the present invention can also have other embodiment.
Embodiment one
In order to solve the technical problem that presently, there are, improve the isolation performance between the deeper photodiode region of well depth,
The invention provides a kind of manufacture method of semiconductor devices, as shown in figure 4, it is mainly included the following steps that：
Step S401：Semiconductor substrate is provided, on the semiconductor substrate formed with the first epitaxial layer, outside described first
Prolonging layer includes some predetermined regions as photodiode region；
Step S402：In first epitaxial layer deep trench is formed between the adjacent photodiode region；
Step S403：Laying is formed on the bottom of the deep trench and side wall；
Step S404：Polysilicon layer is formed in the deep trench, the top surface of the polysilicon layer is less than first extension
Top surface, to be partially filled with the deep trench；
Step S405：Coating is formed on the polysilicon layer in the deep trench, to fill the full deep trench
Form deep trench isolation structure；
Step S406：The epitaxial layer of growth regulation two on the surface of first epitaxial layer, and make second epitaxial layer
Top surface is higher than the top surface of the deep trench isolation structure.
Manufacturing method according to the invention, deep trench isolation structure, the deep trench are formed between adjacent photodiode
Isolation structure includes the laying positioned at bottom, the polysilicon layer on laying and the coating on polysilicon layer,
The structure (Hamburger Structure) in approximate hamburger is constituted, using the deep trench isolation structure, improves adjacent photo
Isolation performance between diode, avoids the appearance of cross-interference issue, and then improves the performance and yield of device.
Below, the preparation method of the semiconductor devices of the present invention is described in detail with reference to figure 2A to Fig. 2 K, wherein, figure
2A to Fig. 2 K shows the structure that a kind of correlation step of the manufacture method of semiconductor devices in one embodiment of the invention is formed
Sectional view.
First, as shown in Figure 2 A, there is provided Semiconductor substrate 200, on the semiconductor substrate formed with the first epitaxial layer
201, there are some photodiode regions defined in first epitaxial layer 201.
Specifically, the constituent material of Semiconductor substrate 200 can use undoped with monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) is laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the composition material of Semiconductor substrate
Material selects monocrystalline silicon.
The material of first epitaxial layer 201 is semi-conducting material, its can be Si, SiB, SiGe, SiC, SiP, SiGeB,
SiCP, AsGa or other iii-vs binary or ternary compound.In the present embodiment, the material of the first epitaxial layer 201 is Si.
Can use the known any suitable selective epitaxial growth of those skilled in the art method be formed this first
Epitaxial layer 201, for example, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecule
One kind in beam epitaxy (MBE).The selective epitaxial growth can be carried out in UHV/CVD reaction chambers.
The thickness of first epitaxial layer 201 can carry out reasonable set according to the demand of specific device, exemplarily, outside first
The thickness for prolonging layer 201 can be 5000 angstroms~50000 angstroms, and above-mentioned number range is only as an example, can also be that other are suitable
Scope.
First epitaxial layer 201 includes some regions for being intended as photodiode region.
Then, as shown in Figure 2 B, sacrifice layer 202 and hard mask are sequentially formed on the surface of first epitaxial layer 201
Layer 203, forms the photoresist layer 204 of patterning on the hard mask layer 203, and the photoresist layer 204 of the patterning includes
Some openings, the opening are used for defining the positions and dimensions of the deep trench of predetermined formation.
Specifically, the material of the sacrifice layer 202 can be any suitable material well known to those skilled in the art, this
In embodiment, the material of the sacrifice layer includes silica.
The hard mask layer 203 include silicon nitride (SiN), SiCN, SiC, amorphous carbon (a-C), boron nitride (BN), SiOF and
One or more in SiON.In the present embodiment, it is preferred that the material of the hard mask layer includes SiN.
Chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) or physical vaporous deposition (PVD) can be used
The sacrifice layer 202 and the hard mask layer 203 are formed Deng suitable technique.
The photoresist layer 204 of patterning is formed on the hard mask layer 203, the patterning can be formed by photoetching process
Photoresist layer 204, be included in spin coating photoresist layer on hard mask layer 203, and carry out the processes such as exposure imaging, so that patterning
Photoresist layer 204 form some openings, the positions and dimensions of those predetermined deep trench formed of opening definition.
Wherein, the region between adjacent photodiode region forms deep trench, therefore the photoresist layer patterned covers
Cover in the first epitaxial layer and made a reservation for the position for forming photodiode region.
Then, as shown in Figure 2 C, it is mask with the photoresist layer 204 of the patterning, etches the hard mask layer successively
203rd, the sacrifice layer 202 and part first epitaxial layer 201, with the adjacent photoelectricity in first epitaxial layer 201
Deep trench is formed between diode region, and removes the photoresist layer 204 of the patterning.
It can be mask first with the photoresist layer 204 of the patterning, etch the hard mask layer 203 and described successively
Sacrifice layer 202, etching gas can use the gaseous mixture of the gas based on chlorine or the gas based on hydrogen bromide or both
Body.Using dry method etch technology, dry method etch technology includes but is not limited to：Reactive ion etching (RIE), ion beam milling, etc.
Plasma or laser cutting.Dry etching is carried out preferably by one or more RIE step.The flow of etching gas
Scope can be 0~200 cc/min (sccm), and reaction room pressure can be 5~20 milli millimetress of mercury (mTorr).
Then, the photoresist layer of patterning is removed, the method for removing the photoresist layer of patterning can be the method for ashing.
Then, according to the first epitaxial layer of opening etching 201 formed in hard mask layer 203 and sacrifice layer 202, to form depth
Groove 205a.The etchant of generally use is fluorine-containing gas, such as CF4Or CHF3.Dry etching can be used, such as instead
Answer any combination of ion(ic) etching, ion beam milling, plasma etching, laser ablation or these methods.It can use single
Engraving method, or more than one engraving method can also be used.Etching gas includes HBr, Cl2、CH2F2、O2One kind
Or several gases, and some addition gas such as nitrogen, argon gas.The range of flow of the etching gas can be 0~150 cube li
M/min (sccm), reaction room pressure can be 3~50 millitorrs (mTorr), the condition in radio-frequency power for 600W~1500W
Lower carry out plasma etching.
Wherein, deep trench 205a altitude range can be 1000~10000 angstroms, can also be other arbitrarily suitable numbers
Value.
In an embodiment of the present invention, the opening formed in the hard mask layer 203 and sacrifice layer 202 defines deep trench
Region and active region, the active region refer to photodiode region.
It is noted that if under given conditions, deep trench has larger depth, then can in etching process
Shape wide at the top and narrow at the bottom can be formed, namely its width being open is more than the width of its bottom.
Then, as shown in Figure 2 D, laying 2051 is formed on the bottom of the deep trench 205a and side wall.
Exemplarily, shape on the bottom of the deep trench 205a and side wall and on the surface of the hard mask layer 203
Into laying 2051.
Laying 2051 can include any one of several gasket materials, include but is not limited to：Silicon oxide liner cushion material
With silicon nitride liner material, in the present embodiment, laying preferably includes silicon oxide liner cushion material.Can use include but unlimited
In：The method of chemical gaseous phase depositing process and physical gas-phase deposite method forms laying.Generally, laying has from about
200 to about 1000 angstroms of thickness.
Then, continue as shown in Figure 2 D, deposition forms polysilicon layer 2052, to fill the deep trench 205a, and overflows
To the top of the hard mask layer 203.
Any one formation polysilicon layer 2052 of several methods can also be used.Non-limiting examples include chemical gaseous phase
Deposition process and physical gas-phase deposite method.
Low-pressure chemical vapor phase deposition (LPCVD) technique can be selected in the forming method of polysilicon layer 2052.Form the polycrystalline
The process conditions of silicon include：Reacting gas is silane (SiH4), the range of flow of the silane can be 100~200 cubic centimetres/
Minute (sccm), such as 150sccm；Temperature range can be 700~750 degrees Celsius in reaction chamber；React cavity pressure can be 250~
350 millimetress of mercury (mTorr), such as 300mTorr；Buffer gas is may also include in the reacting gas, the buffer gas can be
Helium or nitrogen, the range of flow of the helium and nitrogen can be 5~20 liters/min (slm), such as 8slm, 10slm or 15slm.
Then, as shown in Figure 2 E, etch-back removes the part polysilicon layer 2052, so that the remaining polysilicon layer
Top be less than first epitaxial layer 201 top surface, to be partially filled with the deep trench 205a.
In one example, the methods of can first passing through cmp, is by the polysilicon layer of the top of hard mask layer 203
2052 remove, then the step of carry out etch-back.
The etch back process can use wet etching or dry etching.In the specific embodiment of the present invention,
Dry etching can be used to perform etch back process, dry method etch technology includes but is not limited to：Reactive ion etching (RIE), from
Beamlet etching, plasma etching or laser cutting.For example with plasma etching, etching gas can use and be based on oxygen
Gas (O2- based) gas.Specifically, using relatively low RF energy and low pressure and highdensity plasma gas can be produced
Body realizes dry etching.As an example, using plasma etch process, the etching gas used is based on oxygen
(O2- based) gas, the range of flow of etching gas can be 50 cc/mins (sccm)~150 cubic centimetre/point
Clock (sccm), reaction room pressure can be 5 millitorrs (mTorr)~20 millitorr (mTorr).Wherein, the etching gas of dry etching
It can also be bromination hydrogen, carbon tetrafluoride gas or gas of nitrogen trifluoride.It should be noted that above-mentioned engraving method is only
It is exemplary, it is not limited to which this method, those skilled in the art can also select other conventional methods.
Then, as shown in Figure 2 F, deposition forms coating on the hard mask layer 203 and in the deep trench
2053。
The material of the coating 2053 can be arbitrarily suitable insulating materials, non-limiting examples include oxide,
Nitride and nitrogen oxides, especially, silica, silicon nitride and silicon oxynitride, or such as comprising polyvinyl phenol, gather
The insulating materials of acid imide or siloxanes etc..In the present embodiment, it is preferred that the material of coating 2053 includes silica.
Including but not limited to chemical gaseous phase depositing process and physical gas-phase deposite method can be used to form coating 2053,
It is for instance possible to use the method for high density plasma CVD (HDP) forms coating 2053.
Then, as shown in Figure 2 G, planarization is carried out to the coating 2053 to stop on the hard mask layer 203.
Using the surface of flatening process processing coating 2053, cmp (CMP) technique such as is used, to expose
Hard mask layer 203.Wherein, the foregoing laying 2051 on the surface of hard mask layer 203 can also remove in the lump, and due to
High grinding rate of the cmp to coating 2053, it is also possible to so that the coating 2053 above polysilicon layer is by portion
Grinding is divided to remove, and after making CMP, the top surface of remaining coating 2053 is less than the top surface of the hard mask layer 203.
Then, as shown in Fig. 2 H and Fig. 2 I, the hard mask layer 203 and the sacrifice layer 202 are removed.
Specifically, suitable method may be selected according to the material of hard mask layer 203 and sacrifice layer 202 to remove it, including
But it is not limited to dry etching or wet etching.
Exemplarily, hard mask layer 203 is silicon nitride, can be molten first by hot phosphoric acid when sacrifice layer 202 is silica
Liquid removes silicon nitride, and the hydrofluoric acid solution that reusing has high etch-rate to silica removes silicon, it is possible to use dry
Method etching removes sacrifice layer 202 with reference to the method for wet etching.
Meanwhile it can also will be above the part of covering layer 2053 on the surface of the first epitaxial layer 201 and laying 2051 removes.
By above-mentioned steps, in the first epitaxial layer 201 and then final deep trench isolation structure 205, the depth are formd
Groove isolation construction includes polysilicon layer 2052, the laying 2051 for surrounding the bottom of polysilicon layer 2052 and side wall and positioned at more
The coating 2053 of the top surface of crystal silicon layer 2052, those film layers constitute the structure in similar hamburger.
Then, as shown in fig. 2j, the epitaxial layer 206 of growth regulation two on the surface of first epitaxial layer 201, and make described
The top surface of second epitaxial layer 206 is higher than the top surface of the deep trench isolation structure 205.
The material of second epitaxial layer 206 is semi-conducting material, its can be Si, SiB, SiGe, SiC, SiP, SiGeB,
SiCP, AsGa or other iii-vs binary or ternary compound.In the present embodiment, the material of the second epitaxial layer 206 is Si.
Can use the known any suitable selective epitaxial growth of those skilled in the art method be formed this second
Epitaxial layer 206, for example, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), plasma enhanced chemical
Vapour deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecule
One kind in beam epitaxy (MBE).The selective epitaxial growth can be carried out in UHV/CVD reaction chambers.
The thickness of second epitaxial layer 206 can carry out reasonable set according to the demand of specific device, exemplarily, outside second
The thickness for prolonging layer 206 can be 3000 angstroms~20000 angstroms, for example, 3000 angstroms, 5000 angstroms, 10000 angstroms, 15000 angstroms, 20000 angstroms
Deng above-mentioned number range is only as an example, can also be other suitable scopes.
Wherein, when using the second epitaxial layer 206 of high temperature deposition, such as temperature is 300~600 DEG C, while can make depth
Damage in groove isolation construction is repaired.
After depositing the second epitaxial layer 206, in addition to the step planarized to the surface of second epitaxial layer 206
Suddenly, the method for the planarization can use chemical mechanical milling tech.
Afterwards, the manufacture craft of conventional cmos image sensor can be performed,
In one example, as shown in figure 2k, the simple manufacture craft bag for introducing following conventional cmos image sensor
The key step included：
Step S1, fleet plough groove isolation structure is formed in the second epitaxial layer 206 between adjacent pixel unit, the shallow trench
Isolated material is filled with isolation structure, isolated material can be the insulating materials such as silica or silicon nitride, adjacent for isolating
Pixel cell, and the region on adjacent photodiode top, it is located at the top of deep trench isolation structure, can also made shallow
The top of groove isolation construction is located on the top surface of deep trench isolation structure.
Step S2, some pixel cells are formed in the epitaxial layer 201 of the second epitaxial layer 206 and first, wherein, each
Pixel cell includes some transistors and photodiode (not shown), and photodiode includes having opposite lead with epitaxial layer
The doped region of electric type, for example, epitaxial layer is p-type epitaxial layer, then n-type doping area is formed in photodiode region, to form
For PN junction as photodiode, photodiode is used for opto-electronic conversion, and transistor is used for the electric signal for changing photodiode
Exported after amplification, wherein, virtual pixel area (dummy pixel) 21 is also formed with pixel cell periphery, in the virtual pixel
Foregoing deep trench isolation structure 205 is also formed with area 21.
Wherein, the well depth of the photodiode region is deeper, namely the depth of the doped region in photodiode region is deeper, example
Such as, the depth of doped region can reach 3000~25000 angstroms, for example, 3000 angstroms, 5000 angstroms, 10000 angstroms, 15000 angstroms, 20000
Angstrom, 25000 angstroms etc., the depth refers to the distance of the bottom from the top surface of the second epitaxial layer to doped region, namely photodiode
The distance between top surface of the bottom in area and the second epitaxial layer.
And due to the deep trench isolation structure formed in the present invention, the first extension formed below the second epitaxial layer 206
Layer 201 in, compared to directly in the second epitaxial layer etch form fleet plough groove isolation structure method, the present invention in deep trench every
From the bottom of structure 205 with farther with a distance from the top surface of the second epitaxial layer 206, namely the depth of deep trench isolation structure is deeper,
Therefore the deeper photodiode region of well depth can be isolated, it can make it that the bottom of deep trench isolation structure 205 can
Flushed with the bottom with photodiode region, or make the bottom of deep trench isolation structure 205 than the bottom of photodiode region
It is deeper, and then cause the deep trench isolation structure that there is good buffer action to adjacent photodiode region, effectively avoid
The appearance of electrical crosstalk problem.
Step S3, interlayer dielectric layer 207 is formed on a semiconductor substrate, multilayer wiring is formed in interlayer dielectric layer 207
Layer 209.
Interlayer dielectric layer can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or
The material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, for example, it is undoped
Silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron or
The spin cloth of coating-type glass (spin-on-glass, SOG) for adulterating phosphorus, the tetraethoxysilane (PTEOS) or doping boron that adulterate phosphorus
Tetraethoxysilane (BTEOS).
Wiring layer 209 is formed by the conductive material of the metal film of cupric etc., and metal film of the cupric etc. includes copper
It is used as main component.The metal film of cupric can include silver.The metal film of cupric can further include selected from by Al, Au, Pt,
One or both of the group that Cr, Mo, W, Mg, Be, Zn, Pd, Cd, Hg, Si, Zr, Ti and Sn are formed different element.For example,
The metal film of cupric can be formed by electroplating technology.For example, silicide film can be formed on the surface of the metal film of cupric.
In addition to step wherein, in one example,：Formed in the front of second epitaxial layer 206 virtual with periphery
The contact hole 208 of the deep trench isolation structure 205 electrical connection in pixel region 21, by the institute in peripheral virtual pixel area 21
State deep trench isolation structure 205 and be electrically connected to negative pressure.Further, the one end of contact hole 208 electrical connection deep trench isolation structure
Polysilicon layer 2051 in 205, to realize the electrical connection with deep trench isolation structure 205, the other end electrically connects the cloth above it
Line layer, the deep trench isolation structure 205 in peripheral virtual pixel area 21 is electrically connected to negative pressure.
The material of contact hole 208 can be arbitrarily suitable metal material, such as copper, aluminium, tungsten etc..This area skill can be used
Any suitable method forms the contact hole 208 known to art personnel, will not be described here.
Afterwards, the step of forming optical filter and lenticule etc. is additionally may included on interlayer dielectric layer, is not done herein in detail
It is thin to introduce.
It is noted that the semiconductor devices that the present invention is implemented can be cmos image sensor.
Making for complete cmos image sensor also needs other technical process, repeats no more herein.
In summary, manufacturing method according to the invention, deep trench isolation structure is formed between adjacent photodiode,
The deep trench isolation structure includes the laying positioned at bottom, polysilicon layer on laying and on polysilicon layer
Coating, the structure (Hamburger Structure) in approximate hamburger is constituted, using the deep trench isolation structure, is improved
Isolation performance between adjacent photodiode, avoid going out for cross-interference issue between the deeper adjacent photodiode of well depth
It is existing, and then improve the performance and yield of device.
Embodiment two
In order to solve the problems, such as that prior art is present, the present invention also provides a kind of manufacture method of semiconductor devices, such as Fig. 5
Shown, it is mainly included the following steps that：
Step S501, there is provided Semiconductor substrate；
Step S502, forms insulation material layer on the semiconductor substrate；
Step S503, the insulation material layer is patterned, to be formed to each other by some deep trench isolations of separated by openings
Structure, wherein, some deep trench isolation structures are respectively arranged between adjacent photodiode region；
Step S504, forms the first epitaxial layer on the semiconductor substrate, and first epitaxial layer fills adjacent zanjon
Opening between recess isolating structure, and the top surface of first epitaxial layer is higher than the top surface of the deep trench isolation structure.
Manufacturing method according to the invention, by first being patterned to spacer material layer, deep trench isolation structure is formed,
The method for carrying out outer layer growth again, forms deep trench isolation structure in the epitaxial layer, and the deep trench isolation structure has insulation
Material is formed, and its depth is deeper, improves the isolation performance between adjacent photodiode, avoids the deeper adjacent light of well depth
The appearance of cross-interference issue between electric diode, and then improve the performance and yield of device.
Below, the manufacture method with reference to the semiconductor devices in another implementations of the figure 3A to Fig. 3 G to the present invention is done retouches in detail
State, wherein, Fig. 3 A to Fig. 3 G show a kind of related step of the manufacture method of semiconductor devices in another embodiment of the present invention
Suddenly the sectional view of the structure formed.
First, as shown in Figure 3A, there is provided Semiconductor substrate 300, epitaxial layer is formed on the surface of Semiconductor substrate 300
301。
Specifically, the constituent material of Semiconductor substrate 300 can use undoped with monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) is laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the composition material of Semiconductor substrate
Material selects monocrystalline silicon.
The material of epitaxial layer 301 is semi-conducting material, its can be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
AsGa or other iii-vs binary or ternary compound.In the present embodiment, the material of epitaxial layer 301 is Si.
The method of the known any suitable selective epitaxial growth of those skilled in the art can be used to form the extension
Layer 301, for example, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), PECVD
Outside deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam
Prolong one kind in (MBE).The selective epitaxial growth can be carried out in UHV/CVD reaction chambers.
The thickness of epitaxial layer 301 can carry out reasonable set, exemplarily, epitaxial layer 301 according to the demand of specific device
Thickness can be 4000 angstroms~30000 angstroms, such as 3000 angstroms, 5000 angstroms, 7000 angstroms, 9000 angstroms, 11000 angstroms, 13000 angstroms,
15000 angstroms, 18000 angstroms etc., above-mentioned number range is only as an example, can also be other suitable scopes.
The epitaxial layer 301 can also be the epitaxial layer of doping, be p-type or N-type epitaxy layer, with specific reference to the type of device
Carry out reasonable selection.
Then, as shown in Figure 3 B, insulation material layer 302a is formed in the Semiconductor substrate 300.
Specifically, insulation material layer 302a is formed on the surface of epitaxial layer 301.
The material of the insulation material layer 302a can be arbitrarily suitable insulating materials, and non-limiting examples include oxidation
Thing, nitride and nitrogen oxides, especially, silica, silicon nitride and silicon oxynitride, or such as comprising polystyrene
The insulating materials of phenol, polyimides or siloxanes etc..In the present embodiment, it is preferred that insulation material layer 302a material includes oxygen
SiClx.
Including but not limited to chemical gaseous phase depositing process and physical gas-phase deposite method can be used to form insulation material layer
302a, it is for instance possible to use the method for high density plasma CVD (HDP) forms insulation material layer 302a.
Wherein, insulation material layer 302a thickness can be 3000~30000 angstroms, for example, 3000 angstroms, 5000 angstroms, 7000
Angstrom, 9000 angstroms, 11000 angstroms, 13000 angstroms, 15000 angstroms, 18000 angstroms etc., the thickness range is only as an example, insulation material layer
The height of 302a thickness and the deep trench isolation structure formed afterwards is substantially identical, therefore, can be according to the depth of predetermined formation
The height of groove isolation construction rationally to set insulation material layer 302a thickness.
Then, as shown in Figure 3 C, hard mask layer 303 is formed on the surface of the insulation material layer 302a, described hard
The photoresist layer 304 of patterning, the predetermined zanjon formed of the definition of photoresist layer 304 of the patterning are formed on mask layer 303
The pattern of recess isolating structure.
The hard mask layer 303 include silicon nitride (SiN), SiCN, SiC, amorphous carbon (a-C), boron nitride (BN), SiOF and
One or more in SiON.In the present embodiment, it is preferred that the material of the hard mask layer 303 includes SiN.
The thickness range of the hard mask layer 303 can be 300~1000 angstroms, specifically can also be according to actual process needs
Suitably adjusted.
Chemical vapour deposition technique (CVD), atomic layer deposition method (ALD) or physical vaporous deposition (PVD) can be used
The hard mask layer 303 is formed Deng suitable technique.
The photoresist layer 304 of patterning is formed on the hard mask layer 303, the patterning can be formed by photoetching process
Photoresist layer 304, be included in spin coating photoresist layer on hard mask layer 303, and carry out the processes such as exposure imaging, so that patterning
Photoresist layer 304 form some openings, some openings define device preboardings into pixel cell regional location, quilt
The region that photoresist is covered defines the pattern of the deep trench isolation structure of predetermined formation, position, size etc..
Then, as shown in Figure 3 D, using the photoresist layer of the patterning as mask, the hard mask layer 303 is etched successively
And spacer material layer, stop on the surface of the epitaxial layer 301, to be formed to each other by some zanjons of separated by openings
Recess isolating structure 302, some deep trench isolation structures are respectively arranged between adjacent photodiode region.
It can be mask first with the photoresist layer 304 of the patterning, etch the hard mask layer 303, etching gas
The mixed gas of the gas based on chlorine or the gas based on hydrogen bromide or both can be used.Using dry etching work
Skill, dry method etch technology include but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma etching or laser
Cutting.Dry etching is carried out preferably by one or more RIE step.The range of flow of etching gas can be 0~200 cube
Cm per minute (sccm), reaction room pressure can be 5~20 milli millimetress of mercury (mTorr).
Then, the photoresist layer 304 of patterning is removed, the method for removing the photoresist layer of patterning can be the side of ashing
Method.
Then, according to the opening etching spacer material layer formed in hard mask layer 303, to form deep trench isolation structure
302.The etchant of generally use is fluorine-containing gas, such as CF4Or CHF3.Dry etching, such as reactive ion can be used
Etching, ion beam milling, plasma etching, any combination of laser ablation or these methods.Single etching can be used
Method, or more than one engraving method can also be used.Etching gas includes HBr, Cl2、CH2F2、O2It is a kind of or several
Kind gas, and some addition gas such as nitrogen, argon gas.The range of flow of the etching gas can be 0~150 cubic centimetre/point
Clock (sccm), reaction room pressure can be 3~50 millitorrs (mTorr), be carried out under conditions of radio-frequency power is 600W~1500W
Plasma etching.
In an embodiment of the present invention, the opening formed in the hard mask layer 303 defines active area, the active region
Pixel unit area is referred to, each pixel unit area includes photodiode region, therefore, after this step, in phase
Deep trench isolation structure is provided between adjacent pixel unit area.
It is noted that if under given conditions, hard mask layer 303 has larger thickness, then etched
Up-narrow and down-wide shape may be formed in journey, the top width of deep trench isolation structure 302 is less than the width of its bottom.
Then, as shown in FIGURE 3 E, the hard mask layer 303 is removed.Specifically, it is optional according to the material of hard mask layer 303
Select suitable method to remove it, including but not limited to dry etching or wet etching.
Exemplarily, hard mask layer 303 is that silicon nitride can remove silicon nitride first by the phosphoric acid solution of heat.
Then, as illustrated in Figure 3 F, epitaxial layer 305 is formed in the Semiconductor substrate 300, the epitaxial layer 305 is filled
Opening between adjacent deep trenches isolation structure 302, and the top surface of the epitaxial layer 305 is higher than the deep trench isolation structure
302 top surface.
The material of epitaxial layer 305 is semi-conducting material, its can be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
AsGa or other iii-vs binary or ternary compound.In the present embodiment, the material of epitaxial layer 305 is Si.
The method of the known any suitable selective epitaxial growth of those skilled in the art can be used to form the extension
Layer 305, for example, selective epitaxial growth can use low-pressure chemical vapor deposition (LPCVD), PECVD
Outside deposition (PECVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD) and molecular beam
Prolong one kind in (MBE).The selective epitaxial growth can be carried out in UHV/CVD reaction chambers.
The thickness of epitaxial layer 305 can carry out reasonable set, exemplarily, epitaxial layer 305 according to the demand of specific device
Thickness can be 4000 angstroms~40000 angstroms, for example, 5000 angstroms, 10000 angstroms, 15000 angstroms, 20000 angstroms, 25000 angstroms, 30000
Angstrom, 35000 angstroms etc., above-mentioned number range is only as an example, can also be other suitable scopes.
After deposit epitaxial layers 305, in addition to the step of planarized to the surface of the epitaxial layer 305, this is flat
The method of change can use chemical mechanical milling tech.
Can also be doped with N-type or p type impurity, to form N-type or p-type epitaxial layer, with specific reference to device in epitaxial layer 305
The demand of part is rationally set.
Afterwards, the manufacture craft of conventional cmos image sensor can be performed, as shown in Figure 3 G, the CMOS of routine is schemed
As the key step that the manufacture craft of sensor includes simply is introduced：
Step S1, fleet plough groove isolation structure is formed in the epitaxial layer 305 between adjacent pixel unit, shallow trench isolation
Isolated material is filled with structure, isolated material can be the insulating materials such as silica or silicon nitride, for isolating adjacent picture
Plain unit, and the region on adjacent photodiode top, it is located at the top of deep trench isolation structure, can also make shallow trench
The top of isolation structure is located on the top surface of deep trench isolation structure.
Step S2, some pixel cells are formed in the epitaxial layer 305, wherein, each pixel cell includes some crystalline substances
Body pipe and photodiode (not shown), photodiode include the doped region with epitaxial layer with opposite conduction type, example
Such as, epitaxial layer is p-type epitaxial layer, then n-type doping area is formed in photodiode region, to form PN junction as the pole of photoelectricity two
Pipe, photodiode are used for opto-electronic conversion, and transistor exports after being used for the electric signal amplification by photodiode conversion.
Wherein, the well depth of the photodiode region is deeper, namely the depth of the doped region in photodiode region is deeper, example
Such as, the depth of doped region can reach 3000~25000 angstroms, for example, 3000 angstroms, 5000 angstroms, 10000 angstroms, 15000 angstroms, 20000
Angstrom, 25000 angstroms etc., the depth refers to the distance of the bottom from the top surface of epitaxial layer 305 to doped region, namely photodiode region
The distance between the top surface of bottom and epitaxial layer 305.
And due to the deep trench isolation structure formed in the present invention, it is formed in epitaxial layer 305, compared to directly from epitaxial layer
Top surface start the method that etching forms fleet plough groove isolation structure, the bottom of the deep trench isolation structure 302 in the present invention with it is outer
Prolong that the distance of the top surface of layer 305 is farther, namely the depth of deep trench isolation structure is deeper, therefore can be to the deeper photoelectricity of well depth
Diode region is isolated, and it can cause the bottom of deep trench isolation structure 302 to be flushed with the bottom of photodiode region, or
Person makes the bottom of deep trench isolation structure 302 more deeper than the bottom of photodiode region, and then causes the deep trench isolation structure
There is good buffer action to adjacent photodiode region, effectively prevent the appearance of electrical crosstalk problem.
Step S3, interlayer dielectric layer 306 is formed on a semiconductor substrate, multilayer wiring is formed in interlayer dielectric layer 306
Layer 307.
Interlayer dielectric layer can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or
The material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, for example, it is undoped
Silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron or
The spin cloth of coating-type glass (spin-on-glass, SOG) for adulterating phosphorus, the tetraethoxysilane (PTEOS) or doping boron that adulterate phosphorus
Tetraethoxysilane (BTEOS).
Wiring layer 307 is formed by the conductive material of the metal film of cupric etc., and metal film of the cupric etc. includes copper
It is used as main component.The metal film of cupric can include silver.The metal film of cupric can further include selected from by Al, Au, Pt,
One or both of the group that Cr, Mo, W, Mg, Be, Zn, Pd, Cd, Hg, Si, Zr, Ti and Sn are formed different element.For example,
The metal film of cupric can be formed by electroplating technology.For example, silicide film can be formed on the surface of the metal film of cupric.
Afterwards, the step of forming optical filter and lenticule etc. is additionally may included on interlayer dielectric layer, is not done herein in detail
It is thin to introduce.
It is noted that the semiconductor devices that the present invention is implemented can be cmos image sensor.
Making for complete cmos image sensor also needs other technical process, repeats no more herein.
Manufacturing method according to the invention, by first being patterned to spacer material layer, deep trench isolation structure is formed,
The method for carrying out outer layer growth again, forms deep trench isolation structure in the epitaxial layer, and the deep trench isolation structure is by insulating
Material is formed, and its depth is deeper, improves the isolation performance between adjacent photodiode, avoids the deeper adjacent light of well depth
The appearance of cross-interference issue between electric diode, and then improve the performance and yield of device.
Embodiment three
The present invention also provides a kind of semiconductor devices formed using method in previous embodiment one, and the semiconductor devices is
Cmos image sensor.
Below, the structure of the semiconductor devices in one embodiment of the invention is described in detail with reference to figure 6A and Fig. 6 B.
Specifically, as shown in Figure 6A, semiconductor devices of the invention mainly includes following structure：Semiconductor substrate 400, shape
Epitaxial layer 401 described in Cheng Yu in Semiconductor substrate 400, and some photodiodes being formed in the epitaxial layer 401
Deep trench isolation structure in area 403, and the epitaxial layer 401 being arranged between the adjacent photodiode region 403
402, wherein, the top surface of the deep trench isolation structure 402 is less than the top surface of the epitaxial layer 401.
Wherein, the constituent material of Semiconductor substrate 400 can use undoped with monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) is laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the composition material of Semiconductor substrate
Material selects monocrystalline silicon.
The material of epitaxial layer 401 is semi-conducting material, its can be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
AsGa or other iii-vs binary or ternary compound.In the present embodiment, the material of epitaxial layer 401 is Si.
Wherein, the thickness range of epitaxial layer 401 can carry out reasonable set according to the requirement of practical devices, without limitation
Its thickness range can be 8000~70000 angstroms.
Exemplarily, epitaxial layer 401 can also be the epitaxial layer of the doping of doped N-type or p type impurity.
In one example, the thickness range that can also make the epitaxial layer 401 below the top surface of deep trench isolation structure 402 is
5000 angstroms~50000 angstroms, and the thickness range of epitaxial layer 401 more than top surface is 3000~20000 angstroms, above-mentioned number range is only
As an example, can also be other suitable scopes.
In one example, formed with some pixel cells in epitaxial layer 401, wherein, if each pixel cell includes
Dry transistor and photodiode region 403, photodiode region 403 include having opposite conduction type with epitaxial layer 401
Doped region, for example, epitaxial layer is p-type epitaxial layer, then n-type doping area is formed in photodiode region 403, to form PN junction work
For photodiode, photodiode is used for opto-electronic conversion, after transistor is used for the electric signal amplification by photodiode conversion
Output, wherein, virtual pixel area (dummy pixel) 41 is also formed with pixel cell periphery, in the virtual pixel area 41
It is also formed with foregoing deep trench isolation structure 402.
Wherein, the well depth of the photodiode region is deeper, namely the depth of the doped region in photodiode region is deeper, example
Such as, the depth of doped region can reach 3000~25000 angstroms, and the depth refers to the bottom from the top surface of epitaxial layer to doped region
Distance, namely the distance between top surface of the bottom of photodiode region and epitaxial layer.
It is noted that be additionally provided with the Semiconductor substrate of the areas outside of some pixel cells memory device area and
Logic circuit area (Lg), wherein memory device area can include static RAM (Static Random Access
Memory, abbreviation SRAM) area.
Further, the bottom of the bottom of the deep trench isolation structure 402 and the photodiode region 403 maintains an equal level,
Or the bottom of the deep trench isolation structure 402 is lower than the bottom of the photodiode region 403, namely the deep trench
The distance between top surface of the bottom of isolation structure 402 and the epitaxial layer 401 is more than the bottom of the photodiode region 403
The distance between top surface of the epitaxial layer 401, preferably to isolate to adjacent photodiode area 403, avoids it
Generation electrical crosstalk problem.
Exemplarily, as shown in Figure 6 A and 6 B, the deep trench isolation structure 402 includes the polysilicon layer of filling
4022, and surround the insulating barrier 4021 of the surrounded surface of polysilicon layer 4022.
The material of the insulating barrier 4021 can be arbitrarily suitable insulating materials, and its non-limiting examples includes oxidation
Thing, nitride and nitrogen oxides, especially, silica, silicon nitride and silicon oxynitride, or such as comprising polystyrene
The insulating materials of phenol, polyimides or siloxanes etc..In the present embodiment, it is preferred that the material of insulating barrier 4021 includes oxidation
Silicon.
Exemplarily, insulating barrier 4021 can also have from about 200 to about 1000 angstroms of thickness.
Further, the insulating barrier 4021 includes the laying for surrounding the polysilicon layer bottom and side wall, Yi Jiwei
Coating on the polysilicon layer top surface.
Wherein it is possible to laying and coating is set to include identical material, or different insulating materials, preferably
Ground, the material of the coating include silica, and the material of the laying includes silica.
The altitude range being located in the epitaxial layer of deep trench isolation structure 402 can be 1000~10000 angstroms, may be used also
Think other arbitrarily suitable numerical value.
Exemplarily, the deep trench isolation structure 402 can also be shape wide at the top and narrow at the bottom, namely the deep trench every
Top width from structure 402 is more than its bottom width.
Further, as shown in Figure 6B, some photodiode regions 403 are located in the Semiconductor substrate and arranged in matrix
Cloth, formed with deep trench isolation structure 402 between adjacent photodiode region 403, make each photodiode region 403 equal
Surrounded by the deep trench isolation structure of its surrounding, to isolate adjacent photodiode region 403 well.
In one example, in the epitaxial layer 401 between adjacent pixel unit formed with fleet plough groove isolation structure 404,
Isolated material is filled with the fleet plough groove isolation structure 404, isolated material can be the insulating materials such as silica or silicon nitride, use
In isolating adjacent pixel cell, and the region on adjacent photodiode top, it is located at the upper of deep trench isolation structure 402
Side, can also be such that the top of fleet plough groove isolation structure 404 is located on the top surface of deep trench isolation structure 402.
And because the deep trench isolation structure 402 in the present invention is formed in epitaxial layer 401, its top surface is less than the extension
The top surface of layer 401, the bottom of deep trench isolation structure 402 and the distance of the top surface of epitaxial layer 401 are farther, namely deep trench isolation
The depth of structure is deeper, therefore the deeper photodiode region of well depth can be isolated, and then causes the deep trench isolation
Structure has good buffer action to adjacent photodiode region, effectively prevent the appearance of electrical crosstalk problem.
In one example, formed on a semiconductor substrate formed with interlayer dielectric layer 406 in interlayer dielectric layer 406
There is multiple wiring layer 407.
Interlayer dielectric layer can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or
The material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, for example, it is undoped
Silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron or
The spin cloth of coating-type glass (spin-on-glass, SOG) for adulterating phosphorus, the tetraethoxysilane (PTEOS) or doping boron that adulterate phosphorus
Tetraethoxysilane (BTEOS).
Wiring layer 407 is formed by the conductive material of the metal film of cupric etc., and metal film of the cupric etc. includes copper
It is used as main component.The metal film of cupric can include silver.The metal film of cupric can further include selected from by Al, Au, Pt,
One or both of the group that Cr, Mo, W, Mg, Be, Zn, Pd, Cd, Hg, Si, Zr, Ti and Sn are formed different element.For example,
The metal film of cupric can be formed by electroplating technology.For example, silicide film can be formed on the surface of the metal film of cupric.
Wherein, in one example, the epitaxial layer 401 front formed with peripheral virtual pixel area 41 in institute
The contact hole 405 of the electrical connection of deep trench isolation structure 402 is stated, by the deep trench isolation knot in peripheral virtual pixel area 41
Structure 405 is electrically connected to negative pressure.Further, the polysilicon layer in the one end of contact hole 405 electrical connection deep trench isolation structure 402
4022, to realize the electrical connection with deep trench isolation structure 402, the other end electrically connects the wiring layer above it, will be peripheral empty
The deep trench isolation structure 402 intended in pixel region 41 is electrically connected to negative pressure.
The material of contact hole 405 can be arbitrarily suitable metal material, such as copper, aluminium, tungsten etc..This area skill can be used
Any suitable method forms the contact hole 405 known to art personnel, will not be described here.
Further, optical filter and lenticule are also formed with interlayer dielectric layer, is not described in detail herein.
Incident light (as shown in arrow in Fig. 6 A) enters in pixel cell from the front of Semiconductor substrate, incident photon
(Incidence photons) scheduled photodiode region 403 is captured so as to produce photoelectron, and photoelectron is predetermined by this
The n+ layers of photodiode are collected.Due to the presence of deep trench isolation structure 402 so that will not be sent out between adjacent photodiode
Raw electrical crosstalk problem.
For the cmos image sensor part of completion, it also includes other element etc., will not be repeated here.
Semiconductor device according to the invention, deep trench isolation structure, the zanjon are set between adjacent photodiode
Recess isolating structure includes polysilicon layer and surrounds the insulating barrier of polysilicon layer, constitutes the structure (Hamburger in approximate hamburger
Structure), using the deep trench isolation structure, the isolation performance between adjacent photodiode is improved, avoids crosstalk
The appearance of problem, and then improve the performance and yield of device.
Example IV
The present invention also provides a kind of semiconductor devices formed using method in foregoing implementation two, and the semiconductor devices is
Cmos image sensor.
Below, the structure of the semiconductor devices in one embodiment of the invention is described in detail with reference to figure 7A and Fig. 7 B.
Specifically, as shown in Figure 7 A, semiconductor devices of the invention includes：Semiconductor substrate 500, it is formed at and described partly leads
Epitaxial layer 501 on body substrate 500, and some photodiode regions 503, Yi Jishe being formed in the epitaxial layer 501
The deep trench isolation structure 502 being placed in the epitaxial layer 501 between the adjacent photodiode region 503, wherein, it is described
The top surface of deep trench isolation structure 502 is less than the top surface of the epitaxial layer 501.
Wherein, the constituent material of Semiconductor substrate 500 can use undoped with monocrystalline silicon, the monocrystalline doped with impurity
Silicon, silicon-on-insulator (SOI), silicon (SSOI) is laminated on insulator, SiGe (S-SiGeOI) is laminated on insulator, on insulator
SiGe (SiGeOI) and germanium on insulator (GeOI) etc..As an example, in the present embodiment, the composition material of Semiconductor substrate
Material selects monocrystalline silicon.
The material of epitaxial layer 501 is semi-conducting material, its can be Si, SiB, SiGe, SiC, SiP, SiGeB, SiCP,
AsGa or other iii-vs binary or ternary compound.In the present embodiment, the material of epitaxial layer 501 is Si.
Wherein, the thickness range of epitaxial layer 501 can carry out reasonable set according to the requirement of practical devices, without limitation
Its thickness range can be 8000~70000 angstroms.
Exemplarily, epitaxial layer 501 can also be the epitaxial layer of the doping of doped N-type or p type impurity.
In one example, the thickness range that can also make the epitaxial layer 501 below the bottom surface of deep trench isolation structure 502 is
4000 angstroms~30000 angstroms, and the thickness range of epitaxial layer 501 more than bottom surface face is 4000~40000 angstroms, above-mentioned number range
Only as an example, can also be other suitable scopes.
In one example, formed with some pixel cells in epitaxial layer 501, wherein, if each pixel cell includes
Dry transistor and photodiode region 503, photodiode region 503 include having opposite conduction type with epitaxial layer 501
Doped region, for example, epitaxial layer is p-type epitaxial layer, then n-type doping area is formed in photodiode region, using form PN junction as
Photodiode, photodiode are used for opto-electronic conversion, and transistor is used for defeated after the electric signal of photodiode conversion is amplified
Go out.
Wherein, the well depth of the photodiode region is deeper, namely the depth of the doped region in photodiode region is deeper, example
Such as, the depth of doped region can reach 3000~25000 angstroms, and the depth refers to the bottom from the top surface of epitaxial layer to doped region
Distance, namely the distance between top surface of the bottom of photodiode region and epitaxial layer.
It is noted that be additionally provided with the Semiconductor substrate of the areas outside of some pixel cells memory device area and
Logic circuit area (Lg), wherein memory device area can include static RAM (Static Random Access
Memory, abbreviation SRAM) area.
Further, the bottom of the bottom of the deep trench isolation structure 502 and the photodiode region 503 maintains an equal level,
Or the bottom of the deep trench isolation structure 502 is lower than the bottom of the photodiode region 503, namely the deep trench
The distance between top surface of the bottom of isolation structure 502 and the epitaxial layer 501 is more than the bottom of the photodiode region 503
The distance between top surface of the epitaxial layer 501, preferably to isolate to adjacent photodiode area 503, avoids it
Generation electrical crosstalk problem.
Exemplarily, as shown in figures 7 a and 7b, the deep trench isolation structure 502 is made up of insulation material layer.
The material of insulation material layer can be arbitrarily suitable insulating materials, and its non-limiting examples includes oxide, nitrogen
Compound and nitrogen oxides, especially, silica, silicon nitride and silicon oxynitride, or such as comprising polyvinyl phenol, polyamides
The insulating materials of imines or siloxanes etc..In the present embodiment, it is preferred that the material of insulation material layer includes silica.
Wherein, the height of deep trench isolation structure 502 can be 3000~30000 angstroms, for example, 3000 angstroms, 5000 angstroms,
7000 angstroms, 9000 angstroms, 11000 angstroms, 13000 angstroms, 15000 angstroms, 18000 angstroms etc..
Exemplarily, the deep trench isolation structure 502 can also be up-narrow and down-wide shape, namely the deep trench every
Top width from structure 502 is less than its bottom width.
Further, as shown in Figure 7 B, some photodiode regions 503 are located in the Semiconductor substrate and arranged in matrix
Cloth, formed with deep trench isolation structure 502 between adjacent photodiode region 503, make each photodiode region 503 equal
Surrounded by the deep trench isolation structure of its surrounding, to isolate adjacent photodiode region 503 well.
In one example, in the epitaxial layer 501 between adjacent pixel unit formed with fleet plough groove isolation structure 504,
Isolated material is filled with the fleet plough groove isolation structure 504, isolated material can be the insulating materials such as silica or silicon nitride, use
In isolating adjacent pixel cell, and the region on adjacent photodiode top, it is located at the upper of deep trench isolation structure 502
Side, can also be such that the top of fleet plough groove isolation structure 504 is located on the top surface of deep trench isolation structure 502.
And because the deep trench isolation structure 502 in the present invention is formed in epitaxial layer 501, its top surface is less than the extension
The top surface of layer 501, the bottom of deep trench isolation structure 502 and the distance of the top surface of epitaxial layer 501 are farther, namely deep trench isolation
The depth of structure is deeper, therefore the deeper photodiode region of well depth can be isolated, and then causes the deep trench isolation
Structure has good buffer action to adjacent photodiode region, effectively prevent the appearance of electrical crosstalk problem.
In one example, formed on a semiconductor substrate formed with interlayer dielectric layer 505 in interlayer dielectric layer 505
There is multiple wiring layer 506.
Interlayer dielectric layer can be silicon oxide layer, using thermal chemical vapor deposition (thermal CVD) manufacturing process or
The material layer for having doped or undoped silica that high-density plasma (HDP) manufacturing process is formed, for example, it is undoped
Silica glass (USG), phosphorosilicate glass (PSG) or boron-phosphorosilicate glass (BPSG).In addition, interlayer dielectric layer can also be doping boron or
The spin cloth of coating-type glass (spin-on-glass, SOG) for adulterating phosphorus, the tetraethoxysilane (PTEOS) or doping boron that adulterate phosphorus
Tetraethoxysilane (BTEOS).
Wiring layer 506 is formed by the conductive material of the metal film of cupric etc., and metal film of the cupric etc. includes copper
It is used as main component.The metal film of cupric can include silver.The metal film of cupric can further include selected from by Al, Au, Pt,
One or both of the group that Cr, Mo, W, Mg, Be, Zn, Pd, Cd, Hg, Si, Zr, Ti and Sn are formed different element.For example,
The metal film of cupric can be formed by electroplating technology.For example, silicide film can be formed on the surface of the metal film of cupric.
Further, optical filter and lenticule are also formed with interlayer dielectric layer, is not described in detail herein.
Incident light (as indicated by the arrow in figure 7a) enters in pixel cell from the front of Semiconductor substrate, incident photon
(Incidence photons) scheduled photodiode region 503 is captured so as to produce photoelectron, and photoelectron is predetermined by this
The n+ layers of photodiode are collected.Due to the presence of deep trench isolation structure 502 so that will not be sent out between adjacent photodiode
Raw electrical crosstalk problem.
For the cmos image sensor part of completion, it also includes other element etc., will not be repeated here.
Semiconductor device according to the invention, deep trench isolation structure, the zanjon are set between adjacent photodiode
Recess isolating structure is made up of insulating materials, and its depth is deeper, is improved the isolation performance between adjacent photodiode, is avoided
The appearance of cross-interference issue between the deeper adjacent photodiode of well depth, and then improve the performance and yield of device.
Embodiment five
Present invention also offers a kind of electronic installation, including embodiment three or implement semiconductor devices described in four, it is described
Semiconductor devices method according to embodiment one or embodiment two is prepared.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, net book, game machine, TV
Any electronic product such as machine, VCD, DVD, navigator, DPF, camera, video camera, recording pen, MP3, MP4, PSP is set
It is standby, or any intermediate products including circuit.The electronic installation of the embodiment of the present invention, due to having used above-mentioned semiconductor
Device, thus there is better performance.
Wherein, Fig. 8 shows the example of mobile phone handsets.Mobile phone handsets 800, which are equipped with, to be included in shell 801
Display portion 802, operation button 803, external connection port 804, loudspeaker 805, microphone 806 etc..
Semiconductor devices of the wherein described mobile phone handsets described in including embodiment three or example IV, the semiconductor
Device mainly includes：
Semiconductor substrate, the epitaxial layer being formed in the Semiconductor substrate, and if being formed in the epitaxial layer
Dry photodiode region, and the deep trench isolation knot in the epitaxial layer being arranged between the adjacent photodiode region
Structure, wherein, the top surface of the deep trench isolation structure is less than the top surface of the epitaxial layer.
The electronic installation of the present invention includes foregoing semiconductor devices, therefore also has the advantages of identical.
The present invention is illustrated by above-described embodiment, but it is to be understood that, above-described embodiment is only intended to
Citing and the purpose of explanation, and be not intended to limit the invention in described scope of embodiments.In addition people in the art
Member can also make more kinds of it is understood that the invention is not limited in above-described embodiment according to the teachings of the present invention
Variants and modifications, these variants and modifications are all fallen within scope of the present invention.Protection scope of the present invention by
The appended claims and its equivalent scope are defined.
Claims (21)
1. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided, includes some formed with the first epitaxial layer, first epitaxial layer on the semiconductor substrate
The predetermined region as photodiode region；
In first epitaxial layer deep trench is formed between the adjacent photodiode region；
Laying is formed on the bottom of the deep trench and side wall；
Polysilicon layer is formed in the deep trench, the top surface of the polysilicon layer is less than the top surface of first extension, with part
Fill the deep trench；
Coating is formed on the polysilicon layer in the deep trench, deep trench isolation is formed to fill the full deep trench
Structure；
The epitaxial layer of growth regulation two on the surface of first epitaxial layer, and the top surface of second epitaxial layer is higher than the depth
The top surface of groove isolation construction.
2. manufacture method as claimed in claim 1, it is characterised in that the method for forming the deep trench comprises the following steps：
Sacrifice layer and hard mask layer are sequentially formed on the surface of first epitaxial layer；
The photoresist layer of patterning is formed on the hard mask layer, the photoresist layer of the patterning includes some openings, institute
State the positions and dimensions of the predetermined deep trench formed of opening definition；
Using the photoresist layer of the patterning as mask, the hard mask layer, the sacrifice layer and part described are etched successively
One epitaxial layer, to form the deep trench between the adjacent photodiode region in first epitaxial layer.
3. manufacture method as claimed in claim 2, it is characterised in that forming the method for the polysilicon layer includes following step
Suddenly：
Deposition forms polysilicon layer, to fill the deep trench, and spills into the top of the hard mask layer；
Etch-back removes the part polysilicon layer, so that the top of the remaining polysilicon layer is less than first epitaxial layer
Top surface.
4. manufacture method as claimed in claim 3, it is characterised in that the method for forming the coating comprises the following steps：
Deposition forms coating on the hard mask layer and in the deep trench；
Planarization is carried out to the coating to stop on the hard mask layer；
Remove the hard mask layer and the sacrifice layer.
5. manufacture method as claimed in claim 1, it is characterised in that formed in the front of second epitaxial layer empty with periphery
Intend the contact hole of the deep trench isolation structure electrical connection in pixel region, by the deep trench in peripheral virtual pixel area
Isolation structure is electrically connected to negative pressure.
6. manufacture method as claimed in claim 2, it is characterised in that the material of the sacrifice layer includes oxide, described hard
The material of mask layer includes the one or more in SiN, a-C, BN and SiON.
7. manufacture method as claimed in claim 1, it is characterised in that the material of the coating includes silica, the lining
The material of bed course includes silica.
8. a kind of manufacture method of semiconductor devices, it is characterised in that methods described includes：
Semiconductor substrate is provided；
Insulation material layer is formed on the semiconductor substrate；
The insulation material layer is patterned, to be formed to each other by some deep trench isolation structures of separated by openings, wherein, it is described
Some deep trench isolation structures are respectively arranged between adjacent photodiode region；
The first epitaxial layer is formed on the semiconductor substrate, and first epitaxial layer is filled between adjacent deep trenches isolation structure
Opening, and the top surface of first epitaxial layer be higher than the deep trench isolation structure top surface.
9. manufacture method as claimed in claim 8, it is characterised in that before the insulation material layer is formed, be additionally included in
The step of the second epitaxial layer being formed on the surface of the Semiconductor substrate.
10. manufacture method as claimed in claim 8, it is characterised in that forming the method for the deep trench isolation structure includes
Following steps：
Hard mask layer is formed on the surface of the insulation material layer；
The photoresist layer of patterning is formed on the hard mask layer, the photoresist layer of the patterning defines the depth of predetermined formation
The pattern of groove isolation construction；
Using the photoresist layer of the patterning as mask, the hard mask layer and spacer material layer are etched successively, are stopped at described
In Semiconductor substrate, to be formed to each other by some deep trench isolation structures of separated by openings；
And the photoresist layer and the hard mask layer are removed.
11. manufacture method as claimed in claim 8, it is characterised in that the material of the insulation material layer includes silica.
12. manufacture method as claimed in claim 10, it is characterised in that the material of the hard mask layer includes SiN, a-C, BN
With the one or more in SiON.
13. manufacture method as claimed in claim 8, it is characterised in that the thickness range of the insulation material layer be 3000~
30000 angstroms.
A kind of 14. semiconductor devices, it is characterised in that including：
Semiconductor substrate, the epitaxial layer being formed in the Semiconductor substrate, and some light being formed in the epitaxial layer
Deep trench isolation structure in photodiode region, and the epitaxial layer being arranged between the adjacent photodiode region,
Wherein, the top surface of the deep trench isolation structure is less than the top surface of the epitaxial layer.
15. semiconductor devices as claimed in claim 14, it is characterised in that the deep trench isolation structure includes the more of filling
Crystal silicon layer, and surround the insulating barrier of the polysilicon layer surrounded surface.
16. semiconductor devices as claimed in claim 15, it is characterised in that the insulating barrier includes surrounding the polysilicon layer
Bottom and the laying of side wall, and the coating on the polysilicon layer top surface.
17. semiconductor devices as claimed in claim 16, it is characterised in that the material of the coating includes silica, institute
Stating the material of laying includes silica.
18. semiconductor devices as claimed in claim 15, it is characterised in that the epitaxial layer front formed with periphery
The contact hole of deep trench isolation structure electrical connection in virtual pixel area, by the zanjon in peripheral virtual pixel area
Recess isolating structure is electrically connected to negative pressure.
19. semiconductor devices as claimed in claim 14, it is characterised in that the deep trench isolation structure is by insulation material layer
Form.
20. semiconductor devices as claimed in claim 19, it is characterised in that the material of the insulation material layer includes oxidation
Silicon.
21. a kind of electronic installation, it is characterised in that including the semiconductor devices as described in any one of claim 14 to 20.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610843991.9A CN107863361A (en) | 2016-09-22 | 2016-09-22 | A kind of semiconductor devices and its manufacture method and electronic installation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610843991.9A CN107863361A (en) | 2016-09-22 | 2016-09-22 | A kind of semiconductor devices and its manufacture method and electronic installation |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107863361A true CN107863361A (en) | 2018-03-30 |
Family
ID=61698902
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610843991.9A Pending CN107863361A (en) | 2016-09-22 | 2016-09-22 | A kind of semiconductor devices and its manufacture method and electronic installation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107863361A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112736103A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of image sensor and semiconductor device structure |
| CN113451343A (en) * | 2021-06-30 | 2021-09-28 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| CN115911074A (en) * | 2023-02-02 | 2023-04-04 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN117790523A (en) * | 2024-02-23 | 2024-03-29 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459186A (en) * | 2007-12-14 | 2009-06-17 | 东部高科股份有限公司 | Image sensor and method for manufacturing the same |
| WO2011070693A1 (en) * | 2009-12-07 | 2011-06-16 | パナソニック株式会社 | Solid-state imaging device |
| CN104637968A (en) * | 2015-02-15 | 2015-05-20 | 格科微电子（上海）有限公司 | Image sensor adopting deep groove isolation and manufacturing method thereof |
| CN104952896A (en) * | 2015-05-28 | 2015-09-30 | 格科微电子（上海）有限公司 | Manufacturing method of image sensor using deep trench isolation |
| CN105810696A (en) * | 2014-12-31 | 2016-07-27 | 格科微电子（上海）有限公司 | Backside deep trench-isolated backside-illuminated image sensor manufacturing method |
-
2016
- 2016-09-22 CN CN201610843991.9A patent/CN107863361A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101459186A (en) * | 2007-12-14 | 2009-06-17 | 东部高科股份有限公司 | Image sensor and method for manufacturing the same |
| WO2011070693A1 (en) * | 2009-12-07 | 2011-06-16 | パナソニック株式会社 | Solid-state imaging device |
| CN105810696A (en) * | 2014-12-31 | 2016-07-27 | 格科微电子（上海）有限公司 | Backside deep trench-isolated backside-illuminated image sensor manufacturing method |
| CN104637968A (en) * | 2015-02-15 | 2015-05-20 | 格科微电子（上海）有限公司 | Image sensor adopting deep groove isolation and manufacturing method thereof |
| CN104952896A (en) * | 2015-05-28 | 2015-09-30 | 格科微电子（上海）有限公司 | Manufacturing method of image sensor using deep trench isolation |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112736103A (en) * | 2020-12-23 | 2021-04-30 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of image sensor and semiconductor device structure |
| CN112736103B (en) * | 2020-12-23 | 2022-09-20 | 华虹半导体(无锡)有限公司 | Deep trench isolation forming method of image sensor and semiconductor device structure |
| CN113451343A (en) * | 2021-06-30 | 2021-09-28 | 武汉新芯集成电路制造有限公司 | Method for manufacturing semiconductor device |
| CN115911074A (en) * | 2023-02-02 | 2023-04-04 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
| CN117790523A (en) * | 2024-02-23 | 2024-03-29 | 合肥晶合集成电路股份有限公司 | Image sensor and manufacturing method thereof |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3193370B1 (en) | Method of manufacturing a cmos image sensor | |
| KR101738248B1 (en) | Image sensor and fabricating the same | |
| TWI520319B (en) | Semiconductor device and method for fabricating the same | |
| US8304816B2 (en) | Image sensor capable of increasing photosensitivity | |
| US20210335861A1 (en) | Back-side deep trench isolation structure for image sensor | |
| JP2008506271A (en) | Formation of active region using semiconductor growth process without STI integration | |
| CN107863361A (en) | A kind of semiconductor devices and its manufacture method and electronic installation | |
| US11715666B2 (en) | Method of fabricating semiconductor device | |
| US20220384496A1 (en) | Back-side deep trench isolation structure for image sensor | |
| TWI796625B (en) | Integrated circuit, image sensor, and method of forming the same | |
| CN107464813A (en) | A kind of semiconductor devices and preparation method thereof and electronic installation | |
| US8419853B2 (en) | Stacked semiconductor device and related method | |
| US8168509B2 (en) | Etching methods and methods of manufacturing a CMOS image sensor using the same | |
| CN107425018B (en) | Method for manufacturing semiconductor device | |
| KR20110135768A (en) | Fabricating method of a semiconductor device | |
| CN107546179A (en) | A kind of semiconductor devices and its manufacture method | |
| TWI832079B (en) | Integrated chip and method of forming the same | |
| CN102299112A (en) | Method for manufacturing trench and shallow trench isolation structure | |
| CN107275330B (en) | semiconductor device, preparation method thereof and electronic device | |
| JP2023138453A (en) | image sensor | |
| TW202406123A (en) | Optical structure and method for manufacturing the same | |
| JP2023024342A (en) | Image sensor and method of fabricating the same | |
| CN109244088A (en) | A kind of semiconductor devices and preparation method thereof, electronic device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20180330 |
|
| RJ01 | Rejection of invention patent application after publication |