CN113466657B - Circuit board for chip testing, chip testing system and method - Google Patents
Circuit board for chip testing, chip testing system and method Download PDFInfo
- Publication number
- CN113466657B CN113466657B CN202110613745.5A CN202110613745A CN113466657B CN 113466657 B CN113466657 B CN 113466657B CN 202110613745 A CN202110613745 A CN 202110613745A CN 113466657 B CN113466657 B CN 113466657B
- Authority
- CN
- China
- Prior art keywords
- conductive
- circuit board
- chip
- tested
- testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Testing Of Individual Semiconductor Devices (AREA)
Abstract
The embodiment of the application provides a circuit board for chip testing, a chip testing system and a method, wherein the circuit board comprises: the circuit board comprises a circuit board, a first number of conductive pieces arranged along a first direction, a second number of conductive pieces arranged along a second direction, a third number of conductive pieces arranged along the second direction, a fourth number of conductive pieces arranged along the second direction, a sixth number of conductive pieces arranged in the electric connection area of the circuit board, and a sixth number of conductive pieces arranged in the electric connection area of the circuit board, wherein each conductive piece is used for being electrically connected with one test point of a chip to be tested in the test operation; the protective layer is adhered to the surface of each conductive piece, and the orthographic projection area of the protective layer on the circuit board completely covers the orthographic projection area of the first number of conductive pieces on the circuit board; a connection port disposed at the electrical connection region, the connection port for connecting test equipment in the test operation.
Description
Technical Field
The present application relates to the field of semiconductor technology, and relates to, but is not limited to, a circuit board for chip testing, a chip testing system and a method.
Background
In the manufacturing process of semiconductor chip products, it is necessary to test the manufactured chip or die (die) and analyze the performance of the chip or die by detecting the signal flow inside the chip or die.
In the related art, Chip On Board (COB) technology is commonly used for Chip testing of semiconductors. Testing of die is usually achieved by wire bonding (bonding) the test point on die to the gold finger of the COB.
Disclosure of Invention
In view of the above, embodiments of the present application provide a circuit board for chip testing, a chip testing system and a method thereof.
In a first aspect, an embodiment of the present application provides a circuit board for chip testing, including:
the chip testing device comprises a first number of conductive pieces distributed along a first direction, wherein the conductive pieces are arranged in an electric connection area of the circuit board, and each conductive piece is used for being electrically connected with one testing point of a chip to be tested in the testing operation; wherein the first number is at least a positive integer greater than or equal to 2;
a protective layer adhered to the surface of each conductive member; the orthographic projection area of the protective layer on the circuit board completely covers the orthographic projection area of the first number of conductive pieces on the circuit board;
a connection port disposed at the electrical connection region, the connection port for connecting test equipment in the test operation.
In some embodiments, each of the conductive members includes at least two conductive regions arranged in a second direction intersecting the first direction;
the protective layer includes at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers a corresponding one of the conductive regions of each of the conductive members of the first number of conductive members.
In some embodiments, in the second direction, adjacent edges of every two adjacent sub-protection layers directly contact or overlap each other;
each sub-protection layer comprises at least one sealing strip arranged in the first direction;
each sealing strip covers a corresponding one of the conductive areas of at least one of the conductive members.
In some embodiments, the material of the conductive member comprises an oxidizable conductive material; the material of the sealing strip at least comprises polyvinyl chloride and rubber.
In some embodiments, the conductive member and the connection port are electrically connected through an internal circuit of the circuit board; the circuit board further comprises a chip bearing area;
the chip bearing area is used for bearing and fixing the chip to be tested.
In some embodiments, the conductive member includes: a first conductive contact; the connection port includes any one of: the second conductive contact piece, the plug and the jack;
the first conductive contact piece and the second conductive contact piece are made of the same or different materials.
In a second aspect, an embodiment of the present application provides a chip testing system, which includes the above circuit board and testing equipment;
the circuit board is used for connecting the chip to be tested and the test equipment.
In a third aspect, an embodiment of the present application provides a chip testing method, which is applied to a chip testing system, where the chip testing system includes a circuit board and a testing device electrically connected to the circuit board; the circuit board at least comprises conductive pieces arranged along a first direction and a protective layer adhered to the surface of each conductive piece; each conductive member comprises at least two conductive areas arranged in a second direction intersecting the first direction; the protective layer comprises at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers a corresponding conductive area of each conductive piece in the first number of conductive pieces; the method comprises the following steps:
removing part of the sub-protection layer on the surfaces of the conductive pieces so that each conductive piece in a second number of conductive pieces exposes a corresponding conductive area, wherein the second number is smaller than or equal to the first number;
respectively and electrically connecting each test point on the first chip to be tested with the corresponding exposed conductive area of the conductive piece by using a connecting wire;
and testing the first chip to be tested through the test equipment.
In some embodiments, after the connecting wires are used to electrically connect the plurality of test points on the chip to be tested with the exposed conductive areas of the corresponding conductive parts, respectively, a protective cover is installed on the circuit board; wherein, the orthographic projection area of the protective cover on the circuit board completely covers the orthographic projection area of the first number of conductive pieces on the circuit board and the orthographic projection area of the connecting wires on the circuit board.
In some embodiments, an orthographic projection area of the protective cover on the circuit board completely covers an orthographic projection area of the chip to be tested on the circuit board, and an edge of the protective cover is in direct contact with the circuit board.
In some embodiments, the method further comprises:
taking out the first chip to be tested;
removing part of the sub-protection layer on the surfaces of the conductive pieces so that each conductive piece in a third number of conductive pieces exposes a corresponding one of the conductive areas, wherein the third number is smaller than or equal to the first number;
respectively and electrically connecting each test point on the second chip to be tested with the corresponding exposed conductive area of the conductive piece by using a connecting wire;
and testing the second chip to be tested through the testing equipment.
In some embodiments, each of the sub-protection layers includes at least one sealing stripe arranged in the first direction; each sealing strip covers a corresponding one of the conductive areas of at least one of the conductive pieces;
when testing a plurality of chips to be tested, the sealing strips are sequentially removed from one end, close to the chip to be tested, of each conducting piece along the second direction.
The circuit board, the chip testing system and the method for chip testing provided by the embodiment of the application, wherein the circuit board comprises: electrically conductive, the bonding in each of arranging along first direction of first quantity electrically conductive surperficial protective layer and connection port, electrically conductive be used for carrying out the electricity with a test point of the chip that awaits measuring and be connected, electrically conductive and connection port pass through the internal circuit of circuit board and are connected, connection port is used for connecting test equipment to test the chip that awaits measuring through test equipment, because electrically conductive protective layer on surface can protect electrically conductive not by the oxidation, so, can realize testing a plurality of chips through the circuit board, improved the practicality of circuit board.
Drawings
In the drawings, which are not necessarily drawn to scale, like reference numerals may describe similar components in different views. Like reference numerals having different letter suffixes may represent different examples of similar components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed herein.
FIG. 1A is a schematic diagram illustrating a structure of a COB die on which a die is placed according to the related art;
FIG. 1B is a schematic diagram illustrating a wire bonding structure of a die and a COB according to the related art;
FIG. 1C is a schematic view showing a structure of a resin sealing in the related art;
FIG. 1D is a schematic view of a related art seal structure using a protective cap;
fig. 2A is an alternative schematic structural diagram of a circuit board for chip testing according to an embodiment of the present disclosure;
fig. 2B is an alternative structural diagram of the protection layer provided in the embodiment of the present application;
fig. 2C is an alternative structural diagram of the protection layer provided in the embodiment of the present application;
fig. 2D is an alternative structural diagram of a protection layer provided in an embodiment of the present application;
fig. 2E is an alternative structural diagram of a circuit board according to an embodiment of the present disclosure;
fig. 3A is a schematic structural diagram of fixing a chip to be tested on a circuit board according to an embodiment of the present disclosure;
fig. 3B is a schematic structural diagram of routing a chip to be tested according to the embodiment of the present application;
fig. 3C is a schematic structural diagram of routing a chip to be tested according to the embodiment of the present application;
fig. 3D is a schematic structural diagram of routing a chip to be tested according to the embodiment of the present application;
FIG. 4 is a schematic diagram of an alternative structure of a chip test system according to an embodiment of the present disclosure;
fig. 5 is an alternative flowchart of a chip testing method according to an embodiment of the present disclosure.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, specific technical solutions of the present invention will be described in further detail below with reference to the accompanying drawings in the embodiments of the present application. The following examples are intended to illustrate the present application but are not intended to limit the scope of the present application.
In the following description, suffixes such as "module" or "unit" used to denote elements are used only for facilitating the explanation of the present application, and have no specific meaning in themselves. Thus, "module" or "unit" may be used mixedly.
The COB is commonly used for chip testing of semiconductors, and generally, a single die is selected, and the selected die is connected to a gold finger of the COB through a wire bonding, so that the die is tested. Fig. 1A is a schematic diagram illustrating a structure of placing a die on a COB in the related art, and fig. 1B is a schematic diagram illustrating a structure of wire bonding the die and the COB in the related art, as shown in fig. 1A and 1B, first, the die 101 is placed in a specific region on the COB 102; secondly, the die 101 and the gold finger 1021 in the COB 102 are electrically connected through a lead 103; finally, COB 102 is connected to a testing apparatus (not shown) through port 1022 to implement testing of die 101 by the testing apparatus.
In the related art, since the surface of the die or the leads are easily touched when the COB is manually picked and placed during the test process, the die or the leads are damaged, and finally the test is impossible, the die is usually sealed by resin or a protective cover is added at the position of the die. Fig. 1C is a schematic structural diagram of a related art that employs resin sealing, and it can be seen that the die 101, the lead 103, and the gold finger 1021 are covered by the resin 104 to protect the die 101 and the lead 103. Fig. 1D is a schematic structural diagram of a related art that is sealed by a protective cover, and it can be seen that the protective cover 105 is disposed above the die 101, the lead 103, and the gold finger 1021 on the COB to protect the die 101 and the lead 103.
However, although the die and the lead can be protected well by the resin sealing protection method, the resin sealing method is complicated in process and high in cost, and the die is difficult to be taken out after the test is finished; in addition, the resin may cause pollution to the gold finger, and the second wire bonding on the same gold finger cannot be realized.
The inventor of the present disclosure has noticed that, for the protection method of adding the protective cover, since the gold finger is always exposed to the atmospheric environment, the surface of the gold finger is very easily oxidized, which causes the routing difficulty again. Consequently, also make COB can't do the secondary use again to the protection mode that adds the protecting cover, COB's practicality is relatively poor. Therefore, it is desirable to provide a circuit board that allows a plurality of different chips to be tested separately at different time periods.
Based on the above problems in the related art, embodiments of the present application provide a circuit board, a chip testing system, and a method for testing a chip, which can test a plurality of different chips through the circuit board, thereby improving the practicability of the circuit board.
Fig. 2A is an alternative schematic structural diagram of a circuit board for chip testing according to an embodiment of the present application, and as shown in fig. 2A, the circuit board 20 includes: a first number of conductive elements 201, a protective layer 202 adhered to the surface of each conductive element, and a connection port 203.
In this embodiment, the first number of conductive members are sequentially arranged along a first direction. The conductive members 201 are disposed in an electrical connection region of the circuit board, and each conductive member is configured to be electrically connected to a test point of a chip to be tested in a test operation, where the first number is at least a positive integer greater than or equal to 2, for example, the first number is 6 or 12.
In the embodiment of the present application, the material of the conductive member includes an oxidizable conductive material, such as copper, silver, or aluminum, and thus, the conductive member is easily oxidized and failed.
In some embodiments, the conductive member 201 may be a metal conductive strip or a first conductive contact, and the first conductive contact may be a gold finger.
In the embodiment of the present application, the circuit board includes a carrying area (not shown in fig. 2A) and an electrical connection area a, where the electrical connection area a is used to connect the chip to be tested with the testing apparatus. The test points are test pads of the chip to be tested, and the electrical performance test of the chip to be tested can be realized by measuring the test signal of each test point.
Here, the number of the conductive members (i.e. the first number) is greater than or equal to the number of the test points of the chip to be tested, so that each test point can be correspondingly connected with one conductive member.
In some embodiments, when the first number of the conductive elements is equal to the second number of the test points, the sequence of the conductive elements 201 is the same as the sequence of the test points of the chip to be tested, so that the sequence of the conductive elements can be used as the sequence of the test points to be tested, thereby avoiding errors occurring in the test process.
In this embodiment, the protection layer 202 is an adhesive layer, and the protection layer 202 can be adhered to the surfaces of the first number of conductive devices to isolate the external environment of the conductive devices, so that the conductive devices are not oxidized in the atmospheric environment, and the conductive devices are prevented from failing.
In some embodiments, the orthographic projection area of the protective layer on the circuit board completely covers the orthographic projection area of the first number of conductive members on the circuit board. The protective layer has one and only one layer.
And a connection port 203 disposed in the electrical connection area a, where the connection port is used to connect a test device (not shown in fig. 2A) in a test operation, so as to test the chip to be tested through the test device.
In some embodiments, the connection port 203 comprises any one of: the second conductive contact piece, the plug and the jack; the second conductive contact piece and the first conductive contact piece are made of the same or different materials. In some embodiments, the second conductive contact may also be a gold finger. When the connection port 203 is a second conductive contact, the same conductive contact is arranged on the test equipment, and the circuit board is connected with the test equipment through the connection port by routing between the second conductive contact and the contact on the test equipment. When the connection port 203 is a plug, the test equipment is provided with a jack corresponding to the plug, and the circuit board and the test equipment are connected by connecting the plug and the jack. When the connection port 203 is a jack, a plug corresponding to the jack is provided on the test equipment, and the circuit board and the test equipment are connected by connecting the jack and the plug.
The test equipment is used for measuring signals on each conductive piece, and obtaining signals of each test point of the chip to be tested by measuring the signals on each conductive piece, namely, the electrical performance test or the failure analysis test of the chip to be tested is realized.
The circuit board for chip testing that this application embodiment provided includes: electrically conductive, the bonding in each of arranging along first direction of first quantity electrically conductive surperficial protective layer and connection port, electrically conductive be used for carrying out the electricity with a test point of the chip that awaits measuring and be connected, electrically conductive and connection port pass through the internal circuit of circuit board and are connected, connection port is used for connecting test equipment to test the chip that awaits measuring through test equipment, because electrically conductive protective layer on surface can protect electrically conductive not by the oxidation, so, can realize testing a plurality of chips through the circuit board, improved the practicality of circuit board.
In some embodiments, each of the conductive members includes at least two conductive regions arranged in a second direction intersecting the first direction; the protective layer comprises at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers one conductive region of each conductive piece in the first number of conductive pieces; in the second direction, adjacent edges of every two adjacent sub-protection layers are in direct contact.
In some embodiments, each of the sub-protection layers includes at least one sealing stripe arranged in the first direction; each sealing strip covers one conductive area of at least one conductive piece.
In some embodiments, the first direction may be perpendicular to the second direction. Here, the arrangement direction (i.e., the first direction) of the first number of conductive members is defined as an X-axis direction, and the second direction is defined as a Y-axis direction.
Fig. 2B is an alternative structural schematic diagram of the passivation layer provided in the embodiment of the present application, and as shown in fig. 2B, the passivation layer 201 includes two sub-passivation layers, namely a sub-passivation layer 2021 and a sub-passivation layer 2022, which are arranged in the Y-axis direction. Wherein each sub-protection layer covers one of the conductive regions of each of the first number of conductive devices, for example, the sub-protection layer 2021 covers the conductive region 2011 of the first conductive device, and the sub-protection layer 2022 covers the conductive region 2012 of the first conductive device; in the Y-axis direction, adjacent sides of the two adjacent sub-protective layers 2021 and 2022 are in direct contact. In the embodiment of the present application, the sub-protection layer 2021 includes a single sealing tape 2021; the sub-protection layer 2022 is a single sealing strip 2022.
With continued reference to fig. 2B, in an alternative implementation, a single sealing strip 2021 or/and a single sealing strip 2022 covers at least part of each of all the conductive members arranged in the X-axis direction; in the Y-axis direction, adjacent sides (sides extending in the X-axis direction) of the bead 2021 or the bead 2022 are in contact. It should be noted that in some embodiments, the seal strips adjacent to each other in the Y-axis direction may also partially overlap.
Fig. 2C is an optional schematic structural diagram of the protective layer provided in the embodiment of the present application, and as shown in fig. 2C, in an optional implementation manner, the protective layer includes 5 sub-protective layers sequentially arranged in the Y-axis direction, and each sub-protective layer includes 3 sealing strips sequentially arranged in the X-axis direction. Each seal strip in the X-axis direction in fig. 2C covers each conductive region of at least one conductive member in the X-axis direction, for example, seal strip 1' or seal strip 2' or seal strip 3' or seal strip 4' or seal strip 5' covers one conductive region of each of the two conductive members. In addition, adjacent edges of any two adjacent seal strips among the seal strips 1', 2', 3', 4' and 5' in the Y-axis direction are in contact. For example, the seal strip 1 'and the seal strip 2' are in contact at their adjacent edges (edges extending in the X-axis direction), and the seal strip 3 'and the seal strip 4' are in contact at their adjacent edges (edges extending in the X-axis direction).
Fig. 2D is an optional schematic structural diagram of the protective layer provided in the embodiment of the present application, and as shown in fig. 2D, in an optional implementation manner, the protective layer includes 5 sub-protective layers sequentially arranged in the Y-axis direction, which are respectively a sealing strip 1 ", a sealing strip 2", a sealing strip 3 ", a sealing strip 4", and a sealing strip 5 "; each sub-protection layer comprises a first number of sealing strips which are sequentially arranged in the X-axis direction, namely, one sealing strip is arranged on the surface of each conductive piece in the X-axis direction. Adjacent edges of any two adjacent sealing strips in the sealing strips 1', 2', 3', 4' and 5' in the Y-axis direction are in contact. For example, the seal strip 2 "is in contact with the adjacent edge (edge extending in the X-axis direction) of the seal strip 3", and the seal strip 4 "is in contact with the adjacent edge (edge extending in the X-axis direction) of the seal strip 5".
In some embodiments, adjacent edges of two adjacent sealing strips in the plurality of sealing strips arranged along the X-axis direction are in contact with each other or are spaced by a preset distance, and the preset distance is smaller than the distance between the adjacent conductive pieces.
In the process of testing a chip to be tested, the sealing strip is removed, so that the conductive piece is exposed out of a conductive area, and the test point of the chip to be tested is tested by routing between the conductive area and the test point. Because the sealing strip can be used for protecting each conductive area of the conductive piece, each conductive area can be connected with the test point in a routing mode, and therefore the circuit board provided by the embodiment of the application can be used for measuring a plurality of chips to be measured.
It should be noted that the number of the seal strips in the X-axis direction and the number of the seal strips in the Y-axis direction shown in fig. 2C and 2D are merely examples, and the number of the seal strips in the X-axis direction and the number of the seal strips in the Y-axis direction may be set to other applicable numbers. For example, by making the protective layer include a plurality of seal bars in the X-axis direction, it is possible to expose only an appropriate number of conductive members in the case where the number of conductive members is larger than the number of test points on the chip, while protecting the remaining conductive members with the seal bars.
In some embodiments, the material of the sealing strip at least comprises polyvinyl chloride and rubber, and the polyvinyl chloride and the rubber are both high molecular polymers, so that the sealing strip can have viscosity and can be adhered to the surface of the conductive piece.
In some embodiments, the sealing strips may be replaced in whole or in part by insulating tapes, for example, the protective layer may be composed of a plurality of insulating tapes, or the protective layer may be formed by a plurality of insulating tapes and a plurality of sealing strips alternately. In other embodiments, the sealing strip may be replaced by any other suitable sealing material.
In some embodiments, the conductive member and the connection port are electrically connected through an internal circuit of the circuit board.
Here, the Circuit Board includes, but is not limited to, a Printed Circuit Board (PCB).
In some embodiments, the circuit board further comprises a chip carrier region; the chip bearing area is used for bearing and fixing the chip to be tested.
Fig. 2E is an optional schematic structural diagram of the circuit board provided in the embodiment of the present application, and as shown in fig. 2E, the circuit board 20 includes an electrical connection region a and a chip bearing region B, where the chip bearing region B is used for bearing and fixing the chip to be tested.
Here, the chip to be tested may be fixed in the chip carrying region B by a thermosol or a jig.
Next, a specific process of testing a chip to be tested is described by taking the circuit board in the above embodiment as an example: after the COB is manufactured, covering the gold finger (corresponding to the conductive piece in the above embodiment) with a plurality of sealing strips (the arrangement direction of the gold finger is the same) at the position of the gold finger; tearing off any sealing strip during routing, and adding a protective cover after routing; if the COB routing is needed again, after the protective cover and the crystal grains are taken down, another sealing strip is torn down for routing.
As shown in fig. 3A, for a schematic structural diagram of fixing a chip to be tested on a circuit board according to an embodiment of the present application, as shown in fig. 3A, the circuit board 30 includes: a conductive member 301, a sealing tape 302 adhered to the surface of the conductive member, and a connection port 303. The conductive piece comprises 3 conductive areas arranged in the Y direction, and each conductive area in the Y-axis direction is covered by one sealing strip. The chip 304 to be tested is fixed on the circuit board 30, and the chip 304 to be tested includes a test point 3041. As shown in fig. 3B, for a schematic structural diagram of routing a chip to be tested according to an embodiment of the present application, first, a sealing strip is torn off to expose a conductive region 3011 of each conductive component; next, each test point 3041 is connected (e.g., electrically connected) to the exposed conductive region 3011 through a plurality of metal lines 3042, and a protective cover is added on the surfaces of the chip 304 to be tested, the conductive device 301, and the metal lines 3042 to protect the chip 304 to be tested and the metal lines 3042 from being damaged, so as to test the chip 304 to be tested.
In the embodiment of the present application, in the process of testing the chip 304 to be tested, the parts of the conductive members that are not wire bonded are protected by the sealing strips, so that the parts of the conductive members that are not wire bonded are not oxidized.
After the testing of the chip 304 to be tested is completed, the chip 304 to be tested and the metal lines 3042 are removed from the circuit board 30.
Fig. 3C is a schematic diagram of a structure for routing another chip 306 to be tested according to the embodiment of the present application, and as shown in fig. 3C, the chip 306 to be tested is continuously tested through the circuit board 30, that is, the circuit board 30 and the chip 306 to be tested are routed and connected, and the specific connection process is as follows: tearing off a sealing strip again to expose a conductive region 3012 of each conductive piece; each test point 3061 is electrically connected with the exposed conductive area 3012 through a plurality of metal lines 3062, and a protective cover 305 is added on the surfaces of the chip 306 to be tested, the conductive piece 301 and the metal lines 3062 to protect the chip 306 to be tested and the metal lines 3062 from being damaged, so that the chip 306 to be tested is tested.
It should be noted that, in the process of testing the chip 306 to be tested, since the conductive region 3011 is already used, the conductive region 3011 has already failed.
After the testing of the chip 306 to be tested is completed, the chip 306 to be tested and the plurality of metal wires 3062 are removed from the circuit board 30.
Fig. 3D is a schematic diagram of a structure for routing another chip 307 to be tested according to the embodiment of the present application, and as shown in fig. 3D, the chip 307 to be tested is continuously tested through the circuit board 30, that is, the circuit board 30 and the chip 307 to be tested are routed and connected, and the specific connection process is as follows: tearing off a sealing strip again to expose a conductive region 3013 of each conductive piece; each test point 3071 is electrically connected with the exposed conductive region 3013 through a plurality of metal lines 3072, and a protective cover 305 is added on the surfaces of the chip 307 to be tested, the conductive member 301 and the metal lines 3072 to protect the chip 307 to be tested and the metal lines 3072 from being damaged, thereby realizing the test of the chip 307 to be tested.
It should be noted that, in the process of testing the chip 307 to be tested, since the conductive region 3011 and the conductive region 3012 are already used, both the conductive region 3011 and the conductive region 3012 have already failed.
After testing of the chip 307 under test is completed, the chip 307 under test and the metal lines 3072 are removed from the circuit board 30.
In the embodiment of the application, other areas on the gold fingers which are not wire bonded are protected from being oxidized by the sealing strips. And each conductive piece in the circuit board is divided into at least three conductive areas by the sealing strip, and only one sealing strip is torn when the chip to be tested is tested each time, so that the circuit board can be used for testing the three chips to be tested, the circuit board can be used for multiple times, the practicability of the circuit board is improved, and the cost of chip testing is saved.
It should be noted that, as mentioned above, the number of the conductive regions corresponding to each conductive member in the circuit board is not limited to three, and may also be five, seven or other suitable numbers.
An embodiment of the present application provides a chip testing system, and fig. 4 is an optional schematic structural diagram of the chip testing system provided in the embodiment of the present application, and as shown in fig. 4, the chip testing system 40 includes: a circuit board 401 and test equipment 402.
The circuit board 401 is configured to connect a chip 403 to be tested and the test device 402, so as to test the chip 403 to be tested through the test device 402.
Here, the circuit board 401 at least includes a connection port 4011, the test equipment also includes a port 4021, and the connection port 4011 is connected to the port 4021 on the test equipment, so as to connect the circuit board 401 and the test equipment 402. In some embodiments, the types of the connection port 4011 and the port 4021 are the same or matched, for example, the connection port 4011 and the port 4021 are both gold fingers, and the connection between the circuit board and the test equipment is realized by wire bonding between the gold fingers.
In some embodiments, the circuit board 401 further includes a chip carrying area, and the chip carrying area is used for fixedly carrying and fixing the chip 403 to be tested.
In some embodiments, the circuit board 301 further comprises: the circuit board comprises a first number of conductive pieces arranged along a first direction, wherein the conductive pieces are arranged in an electric connection area of the circuit board, and each conductive piece is used for being electrically connected with one test point of a chip to be tested in a test operation; wherein the first number is a positive integer greater than 1.
In some embodiments, the circuit board 301 further comprises: a protective layer adhered to the surface of each conductive member; the orthographic projection area of the protective layer on the circuit board completely covers the orthographic projection area of the first number of conductive pieces on the circuit board.
In some embodiments, the circuit board 301 further comprises: a connection port disposed at the electrical connection region, the connection port for connecting test equipment in the test operation.
In some embodiments, each of the conductive members includes at least two conductive regions arranged in a second direction intersecting the first direction; the protective layer comprises at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers one conductive region of each conductive piece in the first number of conductive pieces; in the second direction, adjacent edges of every two adjacent sub-protection layers are in direct contact.
In some embodiments, each of the sub-protection layers includes at least one sealing stripe arranged in the first direction; each of the seal strips covers one of the conductive regions of at least one of the conductive members.
In some embodiments, the material of the sealing strip comprises at least polyvinyl chloride and rubber.
The circuit board in the embodiment of the present application has the same structure as the circuit board provided in the above embodiment, and for technical features not disclosed in the embodiment of the present application in detail, please refer to the above embodiment for understanding, and details are not described here.
The chip test system that this application embodiment provided includes circuit board and test equipment, because the circuit board can realize carrying out performance test to a plurality of chips that await measuring, so make chip test system also can realize testing a plurality of chips that await measuring, greatly practiced thrift the cost of chip test.
In addition, the embodiment of the application also provides a chip testing method, which is applied to the chip testing system in the embodiment, wherein the chip testing system comprises a circuit board and testing equipment electrically connected with the circuit board; the circuit board at least comprises a first number of conductive pieces arranged along a first direction and a protective layer adhered to the surface of each conductive piece; each conductive member comprises at least two conductive areas arranged in a second direction intersecting the first direction; the protective layer includes at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers a corresponding one of the conductive regions of each of the conductive members of the first number of conductive members. Fig. 5 is an optional schematic flow chart of a chip testing method provided in an embodiment of the present application, and as shown in fig. 5, the method includes the following steps:
step S501, removing a part of the sub-protection layer on the surfaces of the conductive devices, so that each conductive device in the second number of conductive devices exposes a corresponding one of the conductive regions.
Wherein the second number is less than or equal to the first number.
Here, in the second direction, adjacent sides of every two adjacent sub-protection layers directly contact or overlap each other; each sub-protection layer comprises at least one sealing strip arranged in the first direction; each sealing strip covers one conductive area of at least one conductive piece.
Step S502, each test point on the first chip to be tested is electrically connected to a corresponding conductive region where the conductive member is exposed by using a connection line.
In the embodiment of the application, when each pair of chips is tested, any one of two adjacent sealing strips in the second direction is removed to expose one conductive area of each conductive piece, one conductive area of each conductive piece is used for being electrically connected with one test point of the chip to be tested, so that the circuit board is used for testing a plurality of chips to be tested.
In the embodiment of the present application, the second number is equal to the number of the test points on the first chip to be tested.
Step S503, testing the first chip to be tested through the testing device.
And measuring signals on each conductive piece through the test equipment so as to test the chip to be tested.
In some embodiments, after electrically connecting each test point on the chip to be tested with one of the exposed conductive regions of the corresponding conductive device by using the connection line, the method further includes:
and step S10, mounting a protective cover on the circuit board.
The orthographic projection area of the protective cover on the circuit board completely covers the orthographic projection area of the first number of the conductive pieces on the circuit board and the orthographic projection area of the connecting wires on the circuit board, and the orthographic projection area of the protective cover on the circuit board completely covers the orthographic projection area of the chip to be tested on the circuit board.
In this application embodiment, the edge of protection lid with the upper surface direct contact of circuit board, the visor is used for the protection await measuring the chip with electrically connected line between the conducting region.
In some embodiments, the method further comprises the steps of:
and step S11, taking out the first chip to be tested.
Step S12, removing a part of the sub-protection layer on the surfaces of the conductive devices, so that each conductive device in a third number of conductive devices exposes a corresponding one of the conductive regions, wherein the third number is less than or equal to the first number.
Step S13, electrically connecting each test point on the second chip to be tested with the exposed conductive region of the corresponding conductive device by using a connection line.
In this embodiment of the present application, the third number is equal to the number of the test points on the second chip to be tested.
And step S14, testing the second chip to be tested through the testing device.
In this application embodiment, chip test system can test a plurality of chips that await measuring, after accomplishing one of them chip (corresponding the first chip that awaits measuring) test that awaits measuring, need take out the chip that awaits measuring to remove the connecting wire between chip and the electrically conductive piece that awaits measuring. When a new chip to be tested (corresponding to a second chip to be tested) is tested, firstly, according to the number of the test points on the new chip to be tested, the protective layers on the conductive parts with the corresponding number are removed, the corresponding conductive areas are exposed, each exposed conductive area is electrically connected with the test point on the new chip to be tested one by adopting a connecting wire, and the new chip to be tested is tested through test equipment.
In some embodiments, when a plurality of chips to be tested are tested, the sealing strips are sequentially removed from one end of each conductive member close to the chip to be tested along the second direction.
In other embodiments, the sealing strips in each conductive member may be randomly removed in any order when testing a plurality of chips to be tested.
In some embodiments, prior to removing the portion of the protective layer, the method further comprises:
and fixing the chip to be tested in the chip bearing area of the circuit board.
Here, the chip to be tested may be fixed on the chip carrying region of the circuit board by a thermosol or a jig.
The chip testing method provided by the embodiment of the present application is similar to the chip testing system in the above embodiment, and for technical features not disclosed in the embodiment of the present application in detail, please refer to the above embodiment for understanding, and details are not described herein again.
According to the chip testing method provided by the embodiment of the application, when a chip to be tested is tested, a part of the protective layer arranged on the surface of each conductive piece is removed, a part of the conductive area of each conductive piece is exposed, and each testing point on the chip to be tested is electrically connected with the corresponding conductive area exposed by the conductive piece, so that the testing process of the chip to be tested is realized. Because the protective layer comprises a plurality of sub-protective layers, each sub-protective layer comprises a plurality of sealing strips, each sealing strip can at least expose one conductive area of each conductive piece, and each conductive area can realize the electric connection with one chip to be measured, thus, the measurement of a plurality of chips to be measured can be realized.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in a non-target manner. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. Also, the various elements shown or discussed are coupled or directly coupled to each other.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
The features disclosed in the several method or apparatus embodiments provided in the present application may be combined arbitrarily, without conflict, to arrive at new method embodiments or apparatus embodiments.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (11)
1. A circuit board for chip testing, the circuit board comprising:
a first number of conductive elements arranged along a first direction, each of the conductive elements including at least two conductive regions arranged in a second direction intersecting the first direction; the conductive pieces are arranged in the electric connection area of the circuit board, and each conductive piece is used for being electrically connected with one test point of the chip to be tested in the test operation; wherein the first number is at least a positive integer greater than or equal to 2;
a protective layer adhered to the surface of each conductive member; the protective layer comprises at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers a corresponding conductive area of each conductive piece in the first number of conductive pieces; the orthographic projection area of the protective layer on the circuit board completely covers the orthographic projection area of the first number of conductive pieces on the circuit board;
a connection port disposed at the electrical connection region, the connection port for connecting test equipment in the test operation.
2. The circuit board according to claim 1, wherein in the second direction, adjacent edges of every two adjacent sub-protective layers directly contact or overlap each other;
each sub-protection layer comprises at least one sealing strip arranged in the first direction;
each sealing strip covers a corresponding one of the conductive areas of at least one of the conductive members.
3. The circuit board of claim 2, wherein the conductive member material comprises an oxidizable conductive material; the material of the sealing strip at least comprises polyvinyl chloride and rubber.
4. The circuit board of claim 1, wherein the conductive member and the connection port are electrically connected through an internal circuit of the circuit board;
the circuit board further comprises a chip bearing area; the chip bearing area is used for bearing and fixing the chip to be tested.
5. The circuit board of claim 1, wherein the conductive member comprises: a first conductive contact; the connection port includes any one of: the second conductive contact piece, the plug and the jack;
the first conductive contact piece and the second conductive contact piece are made of the same or different materials.
6. A chip test system, comprising: a circuit board and test equipment as provided in any one of the preceding claims 1 to 5;
the circuit board is used for connecting the chip to be tested and the test equipment.
7. The chip testing method is characterized by being applied to a chip testing system, wherein the chip testing system comprises a circuit board and testing equipment electrically connected with the circuit board; the circuit board at least comprises a first number of conductive pieces arranged along a first direction and a protective layer adhered to the surface of each conductive piece; each conductive member comprises at least two conductive areas arranged in a second direction intersecting the first direction; the protective layer comprises at least two sub-protective layers arranged in the second direction, and each sub-protective layer covers a corresponding conductive area of each conductive piece in the first number of conductive pieces; the method comprises the following steps:
removing part of the sub-protection layer on the surfaces of the conductive pieces so that each conductive piece in a second number of conductive pieces exposes a corresponding one of the conductive regions, wherein the second number is smaller than or equal to the first number;
respectively and electrically connecting each test point on the first chip to be tested with the corresponding exposed conductive area of the conductive piece by using a connecting wire;
and testing the first chip to be tested through the testing equipment.
8. The method of claim 7, further comprising:
after the plurality of test points on the chip to be tested are respectively and electrically connected with the exposed conductive areas of the corresponding conductive parts by adopting the connecting lines, a protective cover is arranged on the circuit board;
wherein, the orthographic projection area of the protective cover on the circuit board completely covers the orthographic projection area of the first number of conductive pieces on the circuit board and the orthographic projection area of the connecting wires on the circuit board.
9. The method of claim 8, wherein an orthographic projection area of the protective cover on the circuit board completely covers an orthographic projection area of the chip to be tested on the circuit board, and an edge of the protective cover is in direct contact with the circuit board.
10. The method of claim 9, further comprising:
taking out the first chip to be tested;
removing part of the sub-protection layer on the surfaces of the conductive pieces so that each conductive piece in a third number of conductive pieces exposes a corresponding one of the conductive areas, wherein the third number is smaller than or equal to the first number;
respectively and electrically connecting each test point on the second chip to be tested with the corresponding exposed conductive area of the conductive piece by using a connecting wire;
and testing the second chip to be tested through the testing equipment.
11. The method of claim 10, wherein each of the sub-protective layers comprises at least one sealing stripe arranged in the first direction; each sealing strip covers a corresponding one of the conductive areas of at least one of the conductive pieces;
when testing a plurality of chips to be tested, the sealing strips are sequentially removed from one end, close to the chip to be tested, of each conducting piece along the second direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110613745.5A CN113466657B (en) | 2021-06-02 | 2021-06-02 | Circuit board for chip testing, chip testing system and method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110613745.5A CN113466657B (en) | 2021-06-02 | 2021-06-02 | Circuit board for chip testing, chip testing system and method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113466657A CN113466657A (en) | 2021-10-01 |
| CN113466657B true CN113466657B (en) | 2022-05-27 |
Family
ID=77872142
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110613745.5A Active CN113466657B (en) | 2021-06-02 | 2021-06-02 | Circuit board for chip testing, chip testing system and method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113466657B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040078358A (en) * | 2003-03-04 | 2004-09-10 | 주식회사 하이닉스반도체 | Test vehicle ball grid array package |
| CN1921098A (en) * | 2005-12-15 | 2007-02-28 | 钰创科技股份有限公司 | Packaged semiconductor grain |
| CN101359653A (en) * | 2007-07-31 | 2009-02-04 | 昆山达鑫电子有限公司 | Memory module encapsulation construction and encapsulation method thereof |
| CN101459155A (en) * | 2007-12-12 | 2009-06-17 | 三星电子株式会社 | Circuit board having bypass pad |
| CN105873373A (en) * | 2015-01-21 | 2016-08-17 | 华为技术有限公司 | Circuit board processing method and circuit board and |
| CN111370382A (en) * | 2018-12-25 | 2020-07-03 | 恩智浦美国有限公司 | Hybrid lead frame for semiconductor die package with improved creepage distance |
| CN112366143A (en) * | 2020-10-09 | 2021-02-12 | 长江存储科技有限责任公司 | Unsealing method |
-
2021
- 2021-06-02 CN CN202110613745.5A patent/CN113466657B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20040078358A (en) * | 2003-03-04 | 2004-09-10 | 주식회사 하이닉스반도체 | Test vehicle ball grid array package |
| CN1921098A (en) * | 2005-12-15 | 2007-02-28 | 钰创科技股份有限公司 | Packaged semiconductor grain |
| CN101359653A (en) * | 2007-07-31 | 2009-02-04 | 昆山达鑫电子有限公司 | Memory module encapsulation construction and encapsulation method thereof |
| CN101459155A (en) * | 2007-12-12 | 2009-06-17 | 三星电子株式会社 | Circuit board having bypass pad |
| CN105873373A (en) * | 2015-01-21 | 2016-08-17 | 华为技术有限公司 | Circuit board processing method and circuit board and |
| CN111370382A (en) * | 2018-12-25 | 2020-07-03 | 恩智浦美国有限公司 | Hybrid lead frame for semiconductor die package with improved creepage distance |
| CN112366143A (en) * | 2020-10-09 | 2021-02-12 | 长江存储科技有限责任公司 | Unsealing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113466657A (en) | 2021-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103488333B (en) | Touch panel and manufacturing method of touch display panel | |
| EP3361838B1 (en) | Chip-on-film package, display panel, and display device | |
| US4617605A (en) | Carrier element for an IC module | |
| JPS5972746A (en) | Method and device for protecting film mounting type integra-ted circuit | |
| CN100555604C (en) | The method of display device module and this module of manufacturing | |
| CN113466657B (en) | Circuit board for chip testing, chip testing system and method | |
| CN114035385A (en) | Array substrate, manufacturing method of array substrate and display device | |
| CN113721093A (en) | Display panel mother board, detection method and system of display panel mother board | |
| CN111309173B (en) | Touch electrode, touch display panel and touch display device | |
| CN113658974B (en) | Light-emitting substrate, preparation method thereof, testing method thereof and display device | |
| JPH07147378A (en) | Semiconductor module and ic package used for it | |
| CN114550583B (en) | Display module, touch display module and electronic equipment | |
| US20230275166A1 (en) | Solar cell and electronic device having the same | |
| CN113539087A (en) | First display panel, second display panel, manufacturing method of second display panel and display device | |
| CN1136699A (en) | Improved flexible strip cable | |
| CN217404899U (en) | Fingerprint identification device and electronic equipment | |
| CN110244087B (en) | Display screen and test equipment | |
| CN103426867B (en) | Conformal barrier enclosure module | |
| JP7350703B2 (en) | Method for manufacturing a semiconductor device and semiconductor device | |
| KR20080064250A (en) | Test board of multilayer type for high-precision inspection | |
| CN210776736U (en) | Narrow encapsulation fingerprint module and fingerprint identification mobile terminal | |
| WO2008015213A1 (en) | Distributed esd protection | |
| CN117769125A (en) | Flexible circuit board and manufacturing method thereof | |
| US7488180B2 (en) | Testing device | |
| CN115915814A (en) | Display module and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |