CN114035385A - Array substrate, manufacturing method of array substrate and display device - Google Patents
Array substrate, manufacturing method of array substrate and display device Download PDFInfo
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- CN114035385A CN114035385A CN202111420934.7A CN202111420934A CN114035385A CN 114035385 A CN114035385 A CN 114035385A CN 202111420934 A CN202111420934 A CN 202111420934A CN 114035385 A CN114035385 A CN 114035385A
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- 239000000758 substrate Substances 0.000 title claims abstract description 111
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000012360 testing method Methods 0.000 claims abstract description 120
- 238000000926 separation method Methods 0.000 claims abstract description 6
- 238000005520 cutting process Methods 0.000 claims description 53
- 239000002184 metal Substances 0.000 claims description 38
- 238000002955 isolation Methods 0.000 claims description 24
- 238000005192 partition Methods 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 239000000853 adhesive Substances 0.000 claims description 4
- 230000001070 adhesive effect Effects 0.000 claims description 4
- 238000004891 communication Methods 0.000 claims description 3
- 239000011159 matrix material Substances 0.000 claims description 3
- 239000002390 adhesive tape Substances 0.000 abstract description 13
- 230000000903 blocking effect Effects 0.000 description 7
- 238000013461 design Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000003292 glue Substances 0.000 description 3
- 238000003698 laser cutting Methods 0.000 description 3
- 230000007704 transition Effects 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000001029 thermal curing Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000000576 coating method Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136272—Auxiliary lines
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
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- Crystallography & Structural Chemistry (AREA)
- General Physics & Mathematics (AREA)
- Optics & Photonics (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application discloses an array substrate, a manufacturing method of the array substrate and a display device, wherein the array substrate comprises a display area and a non-display area, the non-display area is arranged around the display area, the array substrate comprises a substrate and a plurality of test wires formed on the substrate, and at least one test wire comprises a first exposed end exposed on the side face of the array substrate; at least one test wire is provided with a separation groove in the direction extending from the first exposed end to the display area, and a second exposed end and a third exposed end which are not communicated with each other are formed on two sides of the separation groove. The test wiring in the binding side of the array substrate is cut again, so that the exposed end of one side close to the display area is disconnected with the exposed end of the side edge of the array substrate, and the short circuit of the test wiring caused by the exposed contact of the conductive adhesive tape and the side edge of the array substrate is avoided.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to an array substrate, a manufacturing method of the array substrate, and a display device.
Background
The manufacturing process of the array substrate includes a cutting process, in the cutting process, a large display motherboard is mainly cut into a plurality of array substrates, in order to ensure the normal operation of the subsequent process, certain detection is required after each step of key manufacturing process, and usually, the driving wiring on the array substrate, such as a scanning line, a data line and other signal lines, needs to be detected to determine whether the manufacturing process is bad, such as broken line and other problems.
In order to test the yield, generally, test wires are formed on the array substrate, and the exposed test terminals of the test wires are connected with external signals to detect the test wires inside the array substrate, but after a large display mother board is cut, the test wires have end portions exposed in the air from the side edges of the liquid crystal array substrate, and are easily corroded by water vapor in the environment, so that in the subsequent process, the test wires are in contact with an attached conductive adhesive tape to cause short circuit, and even more, the array substrate is integrally scrapped.
Disclosure of Invention
The application aims to provide an array substrate, a manufacturing method of the array substrate and a display device, and aims to prevent the problem of short circuit caused by contact of the exposed end of a test wire of the cut display array substrate and a conductive adhesive tape.
The application discloses array substrate, including display area and non-display area, the non-display area centers on the display area sets up, array substrate is walked the line including binding side and many tests: the binding side is arranged in the non-display area; the at least one test wire comprises a first exposed end exposed on the side surface of the array substrate; at least one test wire is provided with a separation groove in the direction extending from the first exposed end to the display area, and the test wire forms a second exposed end and a third exposed end which are not communicated with each other on two sides of the separation groove.
Optionally, the isolation groove is a blind groove, the bottom surface of the isolation groove is the surface of the substrate, the bottom surface of the isolation groove and the bottom surface of the test trace are on the same horizontal plane, and the second exposed end and the third exposed end are respectively located on two inner side walls of the isolation groove.
Optionally, each test line corresponds to each isolation groove, the isolation grooves are communicated with each other, the width of each isolation groove is S, and S is greater than or equal to 10um and less than or equal to 100 um.
Optionally, a test terminal is arranged corresponding to each test trace, the test terminal is electrically connected to the test trace, and the test terminal divides the test trace into a first line segment and a second line segment; the first line segment extends from the display area to the non-display area to the test terminal, and the second line segment extends from the test terminal to the second exposed end; the second line segment comprises a hollow part, a first sub line segment and a second sub line segment, and the hollow part is arranged between the first sub line segment and the second sub line segment.
Optionally, the width of the second line segment is equal to the width of the test terminal, the test terminal includes a first metal pad, a second metal pad and a transparent conductive layer, a space is provided between the first metal pad and the second metal pad, and the transparent conductive layer covers the first metal pad, the second metal pad and the space between the first metal pad and the second metal pad; the first metal gasket and the second metal gasket are both provided with via holes arranged in a matrix.
Optionally, the hollow portions are rectangular, and the number of the hollow portions is two and is not communicated with each other.
Optionally, the hollow portion is rectangular, and a plurality of protrusions arranged at intervals are formed on one side of the first sub-line segment and one side of the second sub-line segment close to the hollow portion.
The application also discloses a manufacturing method of the array substrate, the array substrate is formed by cutting, and the manufacturing method comprises the following steps:
cutting along a preset first cutting route, and forming a first exposed end corresponding to the test wiring of the array substrate;
arranging an alignment mark in the binding side of the array substrate;
cutting along the alignment mark to form a second exposed end and a third exposed end of the test wire;
wherein the second exposed end and the third exposed end are not communicated with each other
The application also discloses a display device, display device includes as above arbitrary array substrate and conductive adhesive tape, conductive adhesive tape covers first exposed end, separate in the groove second exposed end and third exposed end each other UNICOM, the third exposed end with first exposed end intercommunication.
Optionally, the display device further includes a thermal curing adhesive, and the thermal curing adhesive is filled in the partition groove.
For the scheme that the exposed end that uses frame to cut array substrate to produce carries out the protection, this application is cutting the exposed end that forms in array substrate's side to whole array substrate for the first time, cut the test line in the side of binding of array substrate once more, form two exposed ends that have gapped, two exposed ends are cut off by a separating groove in other words, even electrically conductive sticky tape has realized the electricity with the exposed end of array substrate's side and has contacted, but because the test line of the side of binding after the cutting of second time is walked circuit, can't form the return circuit, so can not lead to the test to walk the line and cause the short circuit, influence the demonstration.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application, are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is obvious that the drawings in the following description are only some embodiments of the application, and that for a person skilled in the art, other drawings can be derived from them without inventive effort. In the drawings:
fig. 1 is a schematic view of an array substrate according to a first embodiment of the present application;
fig. 2 is a schematic bonding side view of an array substrate according to a second embodiment of the present application;
fig. 3 is a schematic bonding-side view of an array substrate according to a third embodiment of the present application;
fig. 4 is a schematic view of an array substrate according to a fourth embodiment of the present application;
fig. 5 is a schematic view of a test terminal on an array substrate according to a fourth embodiment of the present application;
fig. 6 is a schematic view of a test terminal on an array substrate according to a fifth embodiment of the present application;
fig. 7 is a schematic view illustrating a method for manufacturing an array substrate according to a sixth embodiment of the present application;
fig. 8 is a schematic view of a display device of a seventh embodiment of the present application;
fig. 9 is a schematic view of a display motherboard according to an eighth embodiment of the present application.
100, an array substrate; 101. a substrate; 110. a display area; 120. a non-display area; 130. binding side; 140. testing the wiring; 141. a first exposed end; 142. a second exposed end; 143. a third exposed end; 144. a first line segment; 145. a second line segment; 146. a first sub-line segment; 147. a second sub-line segment; 148. a hollow-out section; 149. a protrusion; 150. a blocking groove; 160. a test terminal; 161. a first metal pad; 162. a second metal pad; 163. a transparent conductive layer; 164. a via hole; 200. a display device; 210. a conductive tape; 300. a display mother board; 310. an initial array substrate; 311. cutting a line; 312. the common line is tested.
Detailed Description
It is to be understood that the terminology, the specific structural and functional details disclosed herein are for the purpose of describing particular embodiments only, and are representative, but that the present application may be embodied in many alternate forms and should not be construed as limited to only the embodiments set forth herein.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating relative importance or as implicitly indicating the number of technical features indicated. Thus, unless otherwise specified, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "plurality" means two or more. The terms "comprises" and "comprising," and any variations thereof, are intended to cover a non-exclusive inclusion, such that one or more other features, integers, steps, operations, elements, components, and/or combinations thereof may be present or added.
Further, terms of orientation or positional relationship indicated by "center", "lateral", "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, are described based on the orientation or relative positional relationship shown in the drawings, are simply for convenience of description of the present application, and do not indicate that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present application.
Furthermore, unless expressly stated or limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly and may include, for example, fixed connections, removable connections, and integral connections; can be mechanically or electrically connected; either directly or indirectly through intervening media, or through both elements. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
The present application is described in detail below with reference to the figures and alternative embodiments.
Example 1:
fig. 1 is a schematic diagram of an array substrate according to a first embodiment of the present application, and as a first embodiment of the present application, as shown in fig. 1, an array substrate 100 is disclosed, where the array substrate 100 includes a display area 110 and a non-display area 120, the non-display area 120 is disposed around the display area 110, the array substrate 100 includes a substrate 101 and a plurality of test traces 140 formed on the substrate 101, the test traces 140 are metal wires, and at least one of the test traces 140 includes a first exposed end 141 exposed on a side surface of the array substrate 100; at least one of the test traces 140 is provided with a blocking groove 150 in a direction extending from the first exposed end 141 to the display area 110, and the test trace 140 forms a second exposed end 142 and a third exposed end 143 at two sides of the blocking groove 150, which are not electrically connected to each other.
The test wire 140 is divided into at least two sections to form three exposed ends, the second exposed end 142 and the third exposed end 143 are disconnected by the partition groove 150 and are not conducted with each other, so that in the preparation of the later-stage display panel, even if the conductive adhesive tape is in contact with the first exposed end 141 to realize the electric connection, the conductive adhesive tape can only be in the position of the third exposed end 143 and cannot be in electric connection with the second exposed end 142 at the other end of the partition groove 150, and therefore the short circuit condition of the test wire 140 and the conductive adhesive tape cannot be caused, and the display cannot be influenced.
Certainly, not only one test trace 140 is cut, but also only one test trace 140 includes the first exposed end 141 exposed on the side surface of the array substrate, and 2, 3, 5 test traces 140 or each test trace 140 disposed on the substrate is laser cut from the first exposed end 141 to the direction in which the display area 110 extends to form a partition groove 150.
Example 2:
fig. 2 is a schematic diagram of a bonding side of an array substrate according to a second embodiment of the present application, which is mainly illustrated by a portion of a modified area of the present embodiment, and as a second embodiment of the present application, the first embodiment is further defined and refined, as shown in fig. 2, the isolation groove 150 is a blind groove, the bottom surface of the isolation groove 150 is the surface of the substrate 101, the bottom surface of the blocking slot 150 is on the same level as the bottom surface of the test trace 140, only the film layer above the substrate 101 of the array substrate is cut during the second cutting, the substrate 101 is not cut, and during the cutting, a high-precision cutting device can be used to cut a single isolation slot 150 for each test trace 140, the second exposed end and the third exposed end are respectively positioned on two inner side walls of the partition groove, and the second exposed end and the third exposed end are oppositely arranged.
Certainly, in order to facilitate cutting, a large isolation groove 150 can be formed by cutting corresponding to the test traces 140 during cutting, which is equivalent to that the isolation grooves 150 corresponding to each test trace 140 are communicated with each other, the value range of the width S of the isolation groove 150 is 10um to 100um, and the width of the cutting equipment is within the value range of S, so that the large isolation groove can be formed by cutting at one time; the width of the isolation groove is the length of the isolation groove in the extending direction of the test trace, the range of the distance d from the isolation groove 150 to the side, away from the display area, of the binding side 130 of the array substrate is 0.3mm-3mm, the range of the distance h from the isolation groove 150 to the first exposed end 141 formed by cutting is 1mm-10mm, and both h and d can be set according to the size of the specific array substrate under the condition that a gap exists between the second exposed end 142 and the conductive adhesive tape.
Considering that when cutting, due to the inertia effect, the metal residue of the test wire 140 moves along with the cutting direction, and in order to avoid the residue moving to the position between two adjacent test wires 140 to cause the communication between the two test wires 140, generally, the distance between the adjacent test wires 140 is set to be 50um to 1000 um.
Example 3:
fig. 3 is a schematic diagram of a binding side of an array substrate according to a third embodiment of the present application, which mainly illustrates a partial structure of a modified portion of the present embodiment, and is different from the second embodiment, as shown in fig. 3, the blocking groove 150 is a through groove, not only the test trace 140 and a film layer thereon are cut during cutting, but also the substrate is cut, the second exposed end 142 and the third exposed end 143 are respectively located on two parallel side walls of the through groove, the formed through groove can be used for positioning module assembly, and the shape of the blocking groove can also be selected according to the actual application, for example, the blocking groove is a circular through groove, and can be used for placing an indicator light or serving as an adapter port, and the like.
Example 4:
fig. 4 is a schematic view of an array substrate according to a fourth embodiment of the present application; fig. 5 is a schematic view of a test terminal on an array substrate according to a fourth embodiment of the present application, which is a modification and limitation made to the test traces in any of the above embodiments, as shown in fig. 4 to 5, a test terminal 160 is disposed corresponding to each test trace 140, and the test terminal 160 is electrically connected to the test trace 140.
The test terminal 160 includes a first metal pad 161, a second metal pad 162, and a transparent conductive layer 163, a space is provided between the first metal pad 161 and the second metal pad 162, and the transparent conductive layer 163 covers the first metal pad 161, the second metal pad, and the space between the first metal pad 161 and the second metal pad 162; the first metal pad 161 and the second metal pad 162 are provided with via holes 164 arranged in a matrix.
The test terminal 160 divides the test trace 140 into a first line segment 144 and a second line segment 145, and the width of the second line segment 145 is equal to the width of the test terminal 160
The first line segment 144 extends from the display region 110 to the non-display region 120 to the test terminal 160, the second line segment 145 extends from the test terminal 160 to the second exposed end 142, the first metal pad 161 is electrically connected to the first line segment 145, and the second metal pad 162 is electrically connected to the second line segment 145; because the test traces 140 are generally wider, in order to reduce the resistance requirement and increase the groove/hollow design, the hollow design can also reduce the metal residue of laser cutting, and prevent short circuit between different test traces, specifically, the second line segment 145 includes a hollow portion 148, a first sub-line segment 146 and a second sub-line segment 147, the hollow portion is disposed between the first sub-line segment 146 and the second sub-line segment 147, the hollow portion 168 is rectangular, the hollow portion 148 is provided with two parts and is not communicated with each other, the test traces at the cutting lines are divided into at least two lines (at least two lines), and the test terminals adopt transparent electrode layer switching units, so that the corrosion risk caused by external water vapor can be effectively avoided.
Example 5:
fig. 6 is a schematic view of a test terminal on an array substrate according to a fifth embodiment of the present application; different from the fourth embodiment, the hollow portion 148 is rectangular, a plurality of protrusions 149 arranged at intervals are formed on the first sub-line segment 146 and the second sub-line segment 147 towards the hollow portion 148, and an inverted main-character-shaped groove is finally formed, wherein the left and right split wires adopt symmetrical protrusions 149, and the protrusions 149 can perform point discharge to prevent external static electricity from damaging the internal driving wires, so that the function of electrostatic protection is realized.
Example 6:
fig. 7 is a schematic view illustrating a method for manufacturing an array substrate according to a sixth embodiment of the present application; the manufacturing method of the array substrate is used for cutting and forming the array substrate of any one of the above embodiments, and specifically, the manufacturing method includes:
s1: cutting along a preset first cutting route, and forming a first exposed end corresponding to the test wiring of the array substrate;
s2: arranging an alignment mark in the binding side of the array substrate;
s3: cutting along the alignment mark to form a second exposed end and a third exposed end of the test wire;
wherein the second exposed end and the third exposed end are not in communication with each other.
In this embodiment, the array substrate is cut twice, and is cut along a preset first cutting route, so that a cutting plane is formed, a first exposed end is formed at a position corresponding to the test trace on the cutting plane, the first exposed end is in contact with the conductive adhesive tape to realize electrical connection, so that in order to disconnect the electrical connection between the conductive adhesive tape and the test trace, the first exposed end needs to be separated, cutting is performed again on the test trace, two second exposed ends and a third exposed end which are not in conduction with each other are formed by cutting, the conductive adhesive tape can transmit an electrical signal to the third exposed end through the first exposed end, but the third exposed end cannot transmit the electrical signal to the second exposed end any more, which is equivalent to disconnecting the electrical connection between the test trace and the conductive adhesive tape in the display panel.
Specifically, this embodiment generally adopts preset counterpoint mark to carry out the laser cutting location, adjusts laser energy, laser frequency and cutting speed, realizes the complete cutting of test line. Preferably, a cutting terminal design as shown in fig. 5 is adopted, and a light-tight metal layer is adopted at the cutting position, so that whether the cutting effect is feasible or not can be directly judged by using transmitted light; every test is walked all and is adopted the fretwork design to the interval of different test routes is more than 10um at least, prevents that radium-shine cutting's electrically conductive foreign matter from leading to the unusual short circuit between the different test routes.
Example 7:
fig. 8 is a schematic view of a display device according to a seventh embodiment of the present application, and as shown in fig. 8, the present application further discloses a display device 200, where the display device 200 includes the array substrate 100 and the conductive tape 210 according to any of the above embodiments, the conductive tape 210 covers the first exposed end 141, the second exposed end 142 and the third exposed end 143 in the partition groove 150 are not communicated with each other, and the third exposed end 143 is communicated with the first exposed end 141.
Cutting off the test wire at the binding side of the array substrate 100 again by using a laser cutting method, wherein the electrical signal of the conductive tape 210 can only be transmitted to the third exposed end 143 through the first exposed end 141 and cannot be transmitted to the second exposed end 142, which is equivalent to disconnecting the electrical connection between the test wire 140 and the conductive tape 210 in the display panel; further, in combination with the frame sealing glue coating process, the test wiring area is covered with an insulating material such as UV glue or thermosetting glue 220 to protect the second exposed end and the third exposed end at the cut position, and further to prevent the second exposed end 142 from being electrically connected with the conductive tape 210.
Example 8:
fig. 9 is a schematic diagram of a display mother board according to an eighth embodiment of the present application, as shown in fig. 9, which also discloses a display mother board 300, the display mother substrate 300 includes a plurality of uncut initial array substrates 310, each initial array substrate 130 has a test trace 140 disposed therein, adjacent initial array substrates are connected by the test trace, a first cutting line is preset between adjacent initial array substrates 130, each initial array substrate has a second cutting line, the junction of the first cutting line and the test trace is a first exposed end of the test trace, the second cutting line cuts in the binding side to form a second exposed end and a third exposed end, and the initial array substrate is cut by the preset first cutting line and the second cutting line to form the array substrate according to any one of the above embodiments.
The large display mother board 300 further includes a plurality of test common lines 312, and the corresponding test traces 140 are respectively connected to the plurality of test common lines in a one-to-one correspondence; a plurality of cutting lines are preset according to the distribution of the initial array substrate 310, the array substrate can be cut from a large motherboard by cutting along the plurality of cutting lines 311, and the test traces 140 are exposed on the side edges of the array substrate at the corresponding positions of the cutting lines; of course, only one cutting line 311 is disposed between two adjacent array substrates, and the array substrates are correspondingly provided with more test transition lines, so as to transmit the test signal to the next array substrate through the test transition lines, and the test transition lines (not shown in the figure) may not be connected to the circuit inside the current array substrate, but only connected to the test traces 140.
It should be noted that the inventive concept of the present application can form many embodiments, but the present application has a limited space and cannot be listed one by one, so that, on the premise of no conflict, any combination between the above-described embodiments or technical features can form a new embodiment, and after the embodiments or technical features are combined, the original technical effect will be enhanced.
The foregoing is a more detailed description of the present application in connection with specific alternative embodiments, and the specific implementations of the present application are not to be considered limited to these descriptions. For those skilled in the art to which the present application pertains, several simple deductions or substitutions may be made without departing from the concept of the present application, and all should be considered as belonging to the protection scope of the present application.
Claims (10)
1. An array substrate comprising a display area and a non-display area, the non-display area being disposed around the display area, the array substrate comprising:
a substrate; and
a plurality of test wires formed on the substrate, at least one of the test wires including a first exposed end exposed at a side surface of the array substrate;
the display panel is characterized in that a separation groove is formed in the direction, extending from the first exposed end to the display area, of at least one test wire, and a second exposed end and a third exposed end which are not communicated with each other are formed on two sides of the separation groove by the test wire.
2. The array substrate according to claim 1, wherein the isolation groove is a blind groove, the bottom surface of the isolation groove is a surface of the substrate, the bottom surface of the isolation groove and the bottom surface of the test trace are on the same horizontal plane, and the second exposed end and the third exposed end are respectively located on two inner sidewalls of the isolation groove.
3. The array substrate of claim 2, wherein the isolation grooves corresponding to each test trace are connected to each other, and the width of the isolation grooves is S, wherein S is greater than or equal to 10um and less than or equal to 100 um.
4. The array substrate of claim 1, wherein a test terminal is disposed corresponding to each test trace, the test terminal is electrically connected to the test trace, and the test terminal divides the test trace into a first line segment and a second line segment;
the first line segment extends from the display area to the non-display area to the test terminal, and the second line segment extends from the test terminal to the second exposed end;
the second line segment comprises a hollow part, a first sub line segment and a second sub line segment, and the hollow part is arranged between the first sub line segment and the second sub line segment.
5. The array substrate of claim 4, wherein the width of the second line segment is equal to the width of the test terminal;
the test terminal comprises a first metal pad, a second metal pad and a transparent conducting layer, wherein a gap is arranged between the first metal pad and the second metal pad, and the transparent conducting layer covers the first metal pad, the second metal pad and the gap between the first metal pad and the second metal pad; the first metal gasket and the second metal gasket are both provided with via holes arranged in a matrix.
6. The array substrate of claim 4, wherein the two hollowed-out portions are rectangular and are not connected to each other.
7. The array substrate of claim 4, wherein the hollowed-out portion is rectangular, and a plurality of protrusions are formed on one side of the first sub-line segment and one side of the second sub-line segment, which are close to the hollowed-out portion, and the protrusions are spaced from each other.
8. A method for manufacturing an array substrate, wherein the array substrate according to any one of claims 1 to 7 is formed by cutting, and the method comprises:
cutting along a preset first cutting route, and forming a first exposed end corresponding to the test wiring of the array substrate;
arranging an alignment mark in the binding side of the array substrate;
cutting along the alignment mark to form a second exposed end and a third exposed end of the test wire;
wherein the second exposed end and the third exposed end are not in communication with each other.
9. A display device, comprising the array substrate according to any one of claims 1 to 7 and a conductive tape, wherein the conductive tape covers the first exposed end, the second exposed end and a third exposed end in the partition groove are not communicated with each other, and the third exposed end is communicated with the first exposed end.
10. The display device according to claim 9, further comprising a heat-curable adhesive, wherein the heat-curable adhesive is filled in the partition groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111420934.7A CN114035385A (en) | 2021-11-26 | 2021-11-26 | Array substrate, manufacturing method of array substrate and display device |
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| CN114973996A (en) * | 2022-05-30 | 2022-08-30 | 京东方科技集团股份有限公司 | Display module and display device |
| CN115268152A (en) * | 2022-06-21 | 2022-11-01 | 福州京东方光电科技有限公司 | Display panel and electronic equipment |
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