CN113451155A - 加工半导体晶片的方法、半导体晶片、夹和半导体器件 - Google Patents

加工半导体晶片的方法、半导体晶片、夹和半导体器件 Download PDF

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Publication number
CN113451155A
CN113451155A CN202110318330.5A CN202110318330A CN113451155A CN 113451155 A CN113451155 A CN 113451155A CN 202110318330 A CN202110318330 A CN 202110318330A CN 113451155 A CN113451155 A CN 113451155A
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semiconductor
major surface
clip
glass structure
semiconductor wafer
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C·范柯林斯基
D·佩多内
M·皮钦
R·鲁普
戴秋莉
黄佳艺
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Infineon Technologies Austria AG
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Infineon Technologies Austria AG
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    • H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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Abstract

提供了一种用于加工半导体晶片的方法。一种半导体晶片包括第一主表面和第二主表面。在半导体晶片内部产生缺陷，以限定出平行于第一主表面的脱离平面。加工第一主表面而限定出多个电子半导体部件。提供了一种玻璃结构，所述玻璃结构包括多个开口。所述玻璃结构附接到经加工的第一主表面，所述多个开口中的每个分别使多个电子半导体部件的相应区域未被覆盖。聚合物层被施加到第二主表面，并且通过将聚合物层冷却到其玻璃化转变温度以下，沿着脱离平面将半导体晶片分裂成半导体切片和剩留的半导体晶片。所述半导体切片包括所述多个电子半导体部件。

Description

加工半导体晶片的方法、半导体晶片、夹和半导体器件
技术领域
本公开总体上涉及一种用于加工半导体晶片的方法。本发明还涉及一种半导体晶片和一种半导体器件。本公开还涉及一种用于电连接布置在半导体晶片上的焊盘的夹。
背景技术
为了改善半导体器件的特性，通常减小器件中的半导体材料的最终厚度。特别是对于垂直功率器件，最终厚度会影响电特性。
可以通过蚀刻、研磨、锯切等来使半导体晶片变薄。这些去除工艺可能是耗时的或资源密集的。变薄的另一种方法可以是分裂晶片。
薄晶片的处理是复杂的。脆性半导体材料一旦变薄就容易断裂。可以将待变薄的半导体晶片和已经变薄的半导体晶片安装在载体上以进行安全处理。
在将变薄的半导体晶片布置在载体上的情况下，它不可能电接触晶片的两侧。这样就不可能在晶片级上测量两侧都具有电接触部的垂直器件的电特性。
半导体器件的侧向尺寸也趋于减小。侧向尺寸越小，使得必须电连接的焊盘越小。另一方面，连接功率器件的电连接器可能需要足够大的横截面来允许高电流流动。
发明内容
一个示例涉及一种用于加工半导体晶片的方法。所述方法提供具有第一主表面和与第一主表面相反的第二主表面的半导体晶片。在半导体晶片内部产生缺陷。所述缺陷限定出平行于第一主表面的脱离平面。根据本方法，对第一主表面进行加工以限定出多个电子半导体部件。所述方法还提供玻璃结构。所述玻璃结构具有多个开口。所述玻璃结构被附接到经加工的第一主表面。所述多个开口中的每个分别使多个电子半导体部件的相应区域未被覆盖。将聚合物层施加到第二主表面上。所述方法通过将聚合物层冷却到其玻璃化转变温度以下而将半导体晶片分裂成半导体切片和剩留的半导体晶片。所述半导体切片在第一主表面与脱离平面之间延伸。所述半导体切片包括所述多个电子半导体部件。
一个示例涉及一种半导体晶片。所述半导体晶片具有第一主表面和与第一主表面相反的第二主表面。由缺陷限定的脱离平面位于半导体晶片内部。脱离平面平行于第一主表面。多个电子半导体部件形成在第一主表面处以及第一主表面与脱离平面之间。玻璃结构附接到第一主表面。玻璃结构包括多个开口。所述多个开口中的每个分别使多个电子半导体部件的相应区域未被覆盖。
一个示例涉及一种用于电连接布置在玻璃结构中的开口的底部上的焊盘的夹。所述夹包括形成夹的第一部分的铆钉或被弯曲以形成第一部分和第二部分的单件金属片，所述铆钉铆接到夹的第二部分。所述第二部分被构造成延伸到端子。所述第一部分具有为开口的宽度的大约一半或更大的宽度。所述第一部分被构造成能够直通延伸到开口的底部。
一个示例涉及一种半导体器件。所述半导体器件包括具有第一主表面和与第一主表面相反的第二主表面的半导体芯片。第一主表面包括焊盘和玻璃结构。所述玻璃结构包括开口。所述开口的边沿包围焊盘。包围所述开口的所述玻璃结构的厚度与所述开口的宽度之间的纵横比等于一到三或更大。半导体器件包括之上安装半导体芯片的载体。半导体芯片的第二主表面面对所述载体。粘合剂位于所述开口的底部上。夹电连接焊盘。夹包括形成夹的第一部分的铆钉或者被弯曲以形成第一部分和第二部分的单件，所述铆钉铆接到夹的第二部分。所述第二部分被构造成延伸到载体上的端子。所述第一部分具有为开口的宽度的大约一半或更大的宽度。所述第一部分被构造成直通延伸到开口的底部。所述夹的第一部分借助于粘合剂电连接到焊盘。
附图说明
附图示出了示例，并且与说明书一起用于解释本公开的原理。本公开的其它示例和许多预期的优点将容易理解，这是因为通过参考下面的详细描述，它们将变得更好地理解。附图的元件不一定相对于彼此成比例。相同或相似的附图标记表示相同或类似部分。
图1A-1H是示出了根据一个示例的用于加工半导体晶片的一种示例性方法的概念图。
图2是根据一个示例的用于加工半导体晶片的一种示例性方法的流程图。
图3是根据一个示例的半导体晶片的概念性的自上而下的视图。
图4A和4B是根据两个不同的示例的沿着图3中的线A-A’的概念性横截面图。
图5是根据一个示例的半导体器件的概念性横截面图。
图6A是根据一个示例的包括铆钉的夹的概念性透视图。
图6B是根据一个示例的包括铆钉的夹的概念性横截面图。
图7A是根据一个示例的弯曲的夹的概念性透视图。
图7B是根据一个示例的弯曲的夹的概念性透视图。
图7C是根据一个示例的附接到一个示例性半导体器件的弯曲的夹的概念性横截面图。
具体实施方式
在下文中，参考附图描述了多个示例，其中，在全文中，通常使用相似或相同的附图标记来指代相似或相同的元件。在下面的描述中，出于解释的目的，阐述了许多具体细节，以便提供对示例的一个或多个方面的透彻理解。然而，对于本领域技术人员而言显见的是，这些示例的一个或多个方面可以用较少程度的这些具体细节来实施。因此，下面的描述不应被视为限制性的，并且保护范围由所附权利要求书限定。
所概括的各个方面可以以各种形式实施。下面的描述通过图示的方式示出了可以实践各方面的各种组合和配置。应当理解，所描述的方面和/或示例仅仅是示例，在不脱离本公开的范围的情况下，可以利用其它方面和/或示例，并且可以进行结构和功能上的修改。另外，虽然可能仅针对多个实施方式中的一个来公开一个示例的特定特征或方面，但是可以将这种特征或方面与其它实施方式的一个或多个其它特征或方面组合，因为它对于任何给定的或特定的应用可能是期望的和有利的。此外，就具体实施方式或权利要求中使用的术语“包含”、“具有”、“带有”或其其它变体而言，这些术语旨在以类似于术语“包括”的方式是开放式包括。另外，术语“示例性”仅仅意味着作为示例，而不是最好的或最佳的。
本文描述的示例可以涉及半导体晶片。半导体晶片可以包括任何种类的半导体材料。半导体晶片可以包括例如Si、SiC、SiGe、GaAs、GaN的特定的半导体材料或任何其它半导体材料。半导体晶片可以具有圆形形式。圆形半导体晶片的直径可以是大约110mm、150mm、200mm、300mm或450mm。圆形半导体晶片的直径可以具有任何其它值。半导体晶片可以具有矩形形式。半导体晶片可以具有正方形形式。半导体晶片可以由SiC制成且直径为150mm。半导体晶片的厚度可以在大约200μm至大约700μm之间。半导体晶片的厚度可以是大约350μm或大约500μm。
所描述的示例的各方面可以包括在半导体晶片内产生缺陷。缺陷可以借助于至少一个辐射源产生。辐射源可以是激光器。辐射源可以是飞秒激光器。半导体晶片内产生的缺陷可以确定平行于半导体晶片的表面的脱离平面。脱离层或缺陷层可以管控或引导裂纹扩展。施加到半导体晶片上的应力可能会引起裂纹扩展。将晶片暴露于辐射源的射线下可以在第一步骤中在半导体晶片内产生一种类型的穿孔，在第二步骤中沿着该穿孔发生裂纹扩展。形成缺陷层并开始裂纹扩展可以允许从半导体晶片上分裂出薄切片。换句话说：缺陷层可以例如通过激光工艺引入，以便以期望的深度弱化衬底，并且随后的工艺用于沿着该缺陷层分裂衬底。这可以通过施加热(冷/热梯度)力或机械(例如超声波)力来实现。分裂切片的厚度可以小于200μm或者小于100μm或者小于80μm或者小于60μm或者小于40μm或者小于20μm。在多个示例中，切片的厚度可以包括在大约30至50μm之间。
本文描述的示例可以包括在半导体晶片的表面上加工的电子半导体部件。电子半导体部件可以是至少部分地被加工的半导体器件。电子半导体部件可以在半导体晶片中和半导体晶片上被加工或被部分加工。部分加工可能表明半导体器件未完全完成。仍可能需要进一步的工艺、例如形成掺杂区、接触区、金属化或切割，以获得可操作的半导体器件。半导体器件可以是至少双端子器件，例如二极管。半导体器件也可以是三端子器件，例如场效应晶体管(FET：Field-Effect Transistor)、绝缘栅双极晶体管(IGBT：Insulated GateBipolar Transistor)、结场效应晶体管(JFET：Junction Field Effect Transistor)和晶闸管等。半导体器件还可以包括多于三个的端子。半导体器件可以是垂直器件。形成在半导体晶片上的电子部件可以通过切口线分开。
本文公开的示例可以包括玻璃结构。玻璃结构的厚度可以包括在大约100μm至700μm之间或在大约400μm至600μm之间。条的厚度可以是大约500μm。条的厚度可以包括在大约150μm至190μm之间。玻璃结构可以包括任何合适的玻璃材料，例如纯石英或任何类型的浮法玻璃。玻璃结构可以具有多个开口。多个开口的或开口中的一个的侧向尺寸可以适配半导体器件或半导体部件的侧向尺寸。多个开口的或开口中的一个的侧向尺寸可以适配于半导体部件或半导体器件的表面上的接触焊盘的侧向尺寸。开口的侧向宽度可以小于2mm、或者小于1.5mm或者小于1mm。开口的侧向宽度可以是大约1mm。开口的侧向宽度可以是大约1.2mm。开口的面积可以小于3mm2或小于2.5mm2或小于2mm2或小于1.5mm2。开口的面积可以是1.1x1.2mm2。开口可以是矩形的。玻璃结构可以是玻璃格栅。玻璃格栅可以是规则的玻璃格栅。玻璃格栅的开口可以由条隔开。条的侧向宽度可以包括在大约100μm至200μm之间。条的侧向宽度可以是大约155μm。条可以在开口周围形成边沿。条的距离可以适配于半导体晶片上的切口线的距离。条的厚度可以包括在大约300μm至700μm之间或在大约400μm至600μm之间。条的厚度可以是大约500μm。包围开口的玻璃结构、即条的厚度与开口的宽度之间的高宽比可以是大约1：3或大约1：2.5或1：2或更大，随着玻璃结构的厚度大于开口的宽度，高宽比可以达到1：1或甚至更大。条的厚度可以是大约500μm，而开口的宽度可以在大约1mm至1.2mm之间。
本文描述的玻璃结构可以通过可以是湿蚀刻工艺的蚀刻工艺形成。蚀刻工艺可以包括使用光刻技术在玻璃晶片的两侧上形成掩模。一旦掩模形成在玻璃晶片的表面上，玻璃晶片就可以从两个表面从每侧蚀刻到玻璃晶片的大约一半的深度，以获得开口。本文描述的玻璃结构可以通过激光诱导的深蚀刻(LIDE)工艺形成。在LIDE工艺中，开口以两步工艺形成。首先，玻璃表面被激光脉冲照射，从而产生横跨整个玻璃厚度的线形改性。随后，执行湿蚀刻以扩大激光脉冲诱导的微穿孔。
上述的玻璃结构可以附接到半导体晶片的经加工的第一主表面。玻璃结构可以永久地或换言之不可逆地附接到半导体晶片。玻璃结构可以使用聚合物粘合剂来附接。玻璃结构可以使用环氧树脂来附接。玻璃结构可以使用陶瓷粘合剂来附接。玻璃结构可以使用玻璃焊料来附接。玻璃结构可以使用阳极结合、玻璃浆料结合或熔融结合来附接。可以使用提供到半导体晶片的永久连接的任何其它方法来附接玻璃结构。永久连接可以适应宽的温度范围。永久连接可以承受高达300℃或甚至更高的温度以及低至–170℃或甚至更低的温度。
玻璃结构可以相对于半导体晶片布置而使得玻璃结构中的多个开口分别使多个电子半导体部件的每个区域未被覆盖。玻璃结构可以相对于半导体晶片布置而使得玻璃结构的条覆盖半导体晶片的切口线。玻璃结构可以针对每个半导体部件包括两个或更多个开口。每个半导体部件两个开口可以允许半导体部件具有未覆盖的控制焊盘和功率焊盘。控制焊盘可以提供到场效应晶体管的栅极或到双极晶体管的基极的电连接。功率焊盘可以提供到场效应晶体管的源极或漏极或到双极晶体管的发射极或集电极的电连接。开口的尺寸可以选择成小于最终半导体芯片的尺寸。
本文描述的示例可以包括将聚合物层施加到半导体晶片的第二主表面。聚合物层可以适于在冷却时向半导体晶片引入应力。示例可以包括在施加聚合物层之前将牺牲层施加到半导体晶片的第二主表面。本文描述的示例可以包括在具有或不具有中间牺牲层的情况下将聚合物层施加到半导体晶片的第一主表面。本文描述的示例可以包括将聚合物层冷却到其玻璃化转变温度以下。冷却可以包括迅速冷却。冷却聚合物层可以向半导体晶片引入应力并使得沿着预定义的脱离层将半导体切片从半导体晶片分裂出。
本文公开的示例可以包括沿着切口线将永久附接有玻璃结构的半导体切片切割成半导体芯片。分割或切割可以像通常方式那样通过划线-破裂、激光切割、锯切或任何其它方法来实现。在沿着切口线布置玻璃结构的条的情况下，可以同时切割玻璃结构。玻璃结构的条可以足够大，以在每个半导体芯片上留下围绕开口的边沿。边沿可以为薄半导体芯片提供稳定性。边沿可以提供高压保护。
本文描述的示例可以包括用于电连接布置在玻璃结构中的开口的底部上的焊盘的夹。夹可以提供足够大的横截面，以传导由半导体器件所处理的高电流。待传导的高电流可高于5A、高于6A或高于7A或更高。所需的电流可大约为6.9A。所需的横截面面积可大于800μm2、900μm2或1000μm2或更大。
本文所述的夹可以包括铜。本文描述的夹可以是任何其它导电材料的。夹可以包括延伸到玻璃结构的开口的底部的第一部分。第一部分可以由铆钉形成。铆钉可以具有圆形的横截面。铆钉的直径可以大于200μm、大于300μm、大于500μm或更大。铆钉的直径可以是大约500μm至700μm。铆钉可以具有开口的宽度的大约一半或更大的直径。铆钉可以被构造成直通延伸到开口的底部。铆钉可以铆接到夹的第二部分。第二部分可以延伸到端子。第二部分可以由金属片形成。第二部分可以具有矩形的横截面。第二部分可以具有与铆钉的横截面面积相对应的横截面面积。
本文描述的夹可以包括与第二部分一体形成的第一部分。第一部分和第二部分可以由一片金属片形成，该金属片可以是铜片。夹可以被弯曲以使得第一部分和第二部分彼此大致成直角。夹可以具有矩形的横截面。第一部分可以具有方形的横截面。第一部分的宽度可以是大约200μm、大于300μm、大于500μm或更大。第一部分的宽度可以是大约500μm至700μm。第一部分可以具有开口的宽度的大约一半或更大的宽度。第一部分可以被构造成直通延伸到开口的底部。第二部分可以延伸到端子。第二部分可以具有矩形的横截面。第二部分可以具有与第一部分的横截面面积相对应的横截面面积。第二部分可以具有变化的横截面。
本文公开的示例可以包括具有夹的半导体器件。夹的第一部分可以延伸到开口中。所述开口可以在底部处包括导电粘合剂。粘合剂可以将夹附接到底部。粘合剂可以在布置于开口的底部处的焊盘与夹之间提供电连接。粘合剂可以是焊料。粘合剂可以是导电膏。
应当理解，上面给出的所有细节都可以应用于下面参考附图讨论的示例，并且下面给出的任何示例尺寸或材料都应被理解为仅仅是不限制本公开的示例。
图1A-1H是示出根据一个示例的用于加工半导体晶片的一个示例方法的概念图。
图1A示出了半导体晶片10的横截面。根据本示例的半导体晶片10可以是SiC(碳化硅)晶片。晶片10包括第一主表面12和与第一主表面12相反的第二主表面14。根据本示例的SiC晶片可以是具有150mm的直径的6英寸晶片。晶片可以具有在第一主表面12与第二主表面14之间的大约500μm的厚度tw。
图1B示出了半导体晶片10和布置在第一主表面12上方的辐射源16。根据本示例的辐射源16将晶片10暴露于激光射线18下。激光射线18可以被配置成能够在半导体晶片10内部以明确定义的深度产生缺陷。明确定义的深度可考虑随后的分裂损失。激光射线18可以被聚焦以在明确定义的深度处产生缺陷。在相同深度产生的缺陷可以限定脱离平面20。脱离平面20通常平行于第一主表面12。第一主表面12与脱离平面20之间的距离tS可以包括在大约50μm至100μm之间。第一主表面12与脱离平面20之间的距离tS可以为大约50μm。
图1C示出了在晶片10的第一主表面12处进行以形成半导体部件22的加工。该加工可以包括形成半导体部件22所需的任何前端工艺。这可以包括沉积、蚀刻、植入、生长、掺杂、扩散等等。虽然图1C仅示出了4个部件，但是应当理解，晶片10可以包括多得多的部件22。半导体部件22的一部分可以延伸到第一主表面12上方。半导体部件22的一部分可以在半导体本体中在第一主表面12与脱离平面20之间延伸。半导体部件22可以由图1C中未示出的切口线分开。半导体部件22可以包括在第一主表面12上的接触焊盘。
图1D示出了玻璃结构24的示意性横截面。玻璃结构24可以是玻璃格栅。玻璃结构24可包括在其间具有开口28的玻璃条26。在本示例中，玻璃结构24的厚度tg可以是大约500μm。在本示例中，开口28的宽度可以在大约1mm至1.5mm之间。
图1E示出了玻璃结构24通过粘合剂30不可逆地附接到晶片10。玻璃结构24可以与经加工的晶片10对正，以使半导体部件22不被覆盖。换句话说，开口28可以在半导体部件22的至少一部分上方。开口28可以使半导体部件22的接触焊盘不被覆盖。条26可以布置在用于分开半导体部件22的切口线的顶部上并且沿着该切口线布置。每个半导体部件可以有多于一个的开口28。例如，在半导体部件22在晶片10的第一主表面上包括两个接触焊盘的情况下，每个接触焊盘可以具有单独的开口28。
图1F示出了用于将经加工的半导体切片从晶片分裂出的准备状态。聚合物层32被施加到晶片10的第二主表面14上。聚合物层可以具有比半导体晶片高约两个数量级的热系数。在一个示例中，可以将另外的聚合物层(未示出)施加到第一主表面12。然后可以冷却包括晶片10、玻璃结构24和聚合物层的组件。冷却可以降低到聚合物层的玻璃化转变温度以下的温度。冷却可能会达到0℃以下的温度。冷却可能会低于–10℃、低于–100℃、低于–150℃、低于–170℃或甚至更低。冷却例如可以借助于液氮来实现。玻璃化转变改变了聚合物层的物理性质，并对晶片施加应力。使用玻璃化转变允许实现相对较高的弹性模量，从而可以产生足够大的应力。该应力导致裂纹在脱离层中扩展，并且随后使得切片34从晶片上分裂开。玻璃结构24在分裂开期间稳定切片34。在分裂期间，玻璃结构24上的可选的附加聚合物层可以进一步起着稳定作用。在分裂期间，在玻璃结构24上的可选的附加聚合物层可以进一步加强裂纹扩展。切片在第一主表面12与脱离层20之间延伸。半导体切片34包括晶片10的经加工的半导体部分。
图1G示出了从剩留的半导体晶片36分裂开半导体切片34。聚合物层32可以与剩留的半导体晶片36脱离。这可以例如通过蚀刻来实现。剩留的半导体晶片可能仍然足够厚，例如具有350μm的起始晶片厚度和50μm的切片厚度，从而可以再次用剩留的晶片36作为半导体晶片10重新开始如参考1A-1G所解释的方法。因此，用同一晶片，可以产生多个经加工的半导体切片。锯切损失可以最小化。可以以任何其它形式研磨、蚀刻或加工半导体切片34的背侧38，以释放源自分裂工艺的任何残留损伤。永久附接的玻璃栅格24使薄的半导体切片34稳定。玻璃结构24的厚度tg可以是半导体切片34的厚度tS的至少四倍。玻璃结构24的厚度tg可以是半导体切片34的厚度tS的十倍。厚度tg可以是500μm，而厚度tS是50μm。
图1H示出了与图1G相比旋转了180°的包括玻璃结构24和半导体切片34的组件。图1H示出了用于完成半导体部件22的进一步的背侧加工步骤。背侧加工可包括植入工艺以形成掺杂的示例区域40。背侧加工可包括任何退火步骤。背侧加工可以包括形成金属化结构42、例如接触焊盘、连接线等等。玻璃结构24可以在分裂之后薄化。在此阶段，即在将切片从晶片上分裂开之后，也可以在半导体切片34的前侧12上、即在开口28内部形成金属化结构44。金属化结构44也可以在较早的阶段形成。金属化结构44可以在前侧加工期间形成。当前侧12和背侧38均设有接触焊盘42、44时，可以对半导体部件22进行电测试。因此，可以在晶片级进行电测量。玻璃结构24在测试期间使晶片稳定，但是使接触焊盘44可接近。不需要附加的载体。在测试之后，半导体切片34和玻璃结构24一起可以被分成单独的半导体裸片。单个化可以通过沿着切口线46进行锯切来实现。可以使用任何其它切割方法。
图2是根据一个示例的用于加工半导体晶片的一个示例方法的流程图。在S1，提供半导体晶片。在S2，借助于激光器、优选地是具有小于500fs的脉冲的飞秒激光器来产生缺陷。缺陷在半导体晶片内部产生。缺陷位于限定出平行于半导体晶片的表面的脱离平面的一个平面上。在S3，加工晶片的第一主表面以限定多个电子半导体部件。在S4，提供玻璃结构。玻璃结构包括从玻璃结构的第一表面延伸到玻璃结构的与第一表面相反的第二表面的多个开口。该玻璃结构可以针对每个半导体部件包括一个开口或针对每个半导体部件包括多于一个的开口。在S5，将玻璃结构永久附接到半导体晶片的经加工的第一主表面。附接实施成能承受大约300℃-170℃的温度。在S6，将聚合物层施加到晶片的与第一主表面相反的第二主表面。该聚合物可以具有一玻璃化转变温度。在S7，将半导体晶片分裂成包括半导体晶片的经加工的第一表面的半导体切片和剩留的半导体晶片。通过将组件冷却到玻璃化转变温度以下以实现冷分裂来实现分裂。
图3是半导体晶片10或附接有玻璃结构24的半导体切片34的概念性的自上而下的视图。在分裂之后，自上而下的视图不会变化。它显示了由界定开口28的规则的玻璃结构24形成的栅格。在开口的底部是未被覆盖的半导体部件22。一个半导体部件22的整个未被覆盖的表面可以形成接触焊盘。在一个半导体部件22的未被覆盖的表面上，可以形成多于一个的接触焊盘(未示出)。在形成栅格24的条26的中间，有切口线46。
图4A是根据一个示例的沿着图3中的线A-A’的概念性横截面图。在半导体切片34上，示出了玻璃结构24的两个条26。在两个条26之间，示出了接触焊盘44。条26示出两个凹面26a、26b。当如上所述使用光刻掩模从两个表面开始将开口28蚀刻到玻璃结构中时，会出现这些表面。湿蚀刻会底切掩膜，并产生凹面。两个凹面部分限制了开口28的纵横比宽度/深度。如果开口宽度足够大于开口的深度，则它们是可以容忍的。由此产生的开口可以通过向初始开口添加两倍的蚀刻深度来计算。
图4B是根据一个不同的示例的沿着图3中的线A-A’的概念性横截面图。在半导体切片34上，示出了玻璃结构24的两个条26。在两个条26之间，示出了接触焊盘44。条26显示出直的垂直表面。在本示例中，已经使用上述的LIDE工艺蚀刻了开口28。可以实现较小的开口28的纵横比宽度/深度，即，对于相同高度(等于开口的深度)的玻璃结构，与使用图4A所示的湿蚀刻工艺相比，开口可实现较小的宽度。
图5是根据一个示例的半导体器件48的概念性横截面图。半导体器件48包括通过切割半导体切片34而获得的裸片。裸片可以包括一个电子部件22。在所示的示例中，电子部件22可以是二极管。接触焊盘44可以在开口28的底部处布置在电子部件22的顶部上，并且金属化结构42可以布置在背侧处。该横截面图在接触焊盘44的左侧和右侧示出了玻璃结构24的条26。从图3的视图可以理解，玻璃结构24形成了完全包围布置在开口28的底部处的接触焊盘44的边沿。半导体器件48还包括可以是引线框架的载体50。载体50包括裸片焊盘50a和端子50b。
裸片的金属化结构42例如通过焊料或导电膏电和机械地连接裸片焊盘50a。示意性地示出的夹52具有第一部分52a和第二部分52b。第一部分52a可以具有大于玻璃结构24的厚度的长度。第一部分52a的第一端部54借助于开口28的底部处的粘合剂56电连接到接触焊盘44。粘合剂可以是焊料或导电膏。第二部分52b可以被构造成延伸到端子50b。第二部分52b的结构可以与所使用的载体有关。例如，载体可以具有在裸片焊盘之外的另一水平上的端子。
图6A是根据一个示例的包括铆钉的夹58的概念性透视图。夹58可以包括第一部分58a和第二部分58b。第一部分58a可由铆接到第二部分58b的铆钉形成。夹58可以由铜制成。铆钉58a的直径可以是可缩放的，以符合待接触的接触焊盘。例如，接触焊盘可以是源接触部。铆钉58a的直径可以是可缩放的，以符合通过夹的电流。第二部分58b可以由金属片冲压而成。第二部分58b可具有与通过夹的电流有关的可缩放的上表面积。第二部分58b可以具有与导通电阻要求有关的可缩放的上表面积。导通电阻是MOSFET晶体管的源极与漏极之间的电阻值。第二部分58b可以弯曲以适配于载体端子。第二部分58b可以包括铆钉58a穿过的开口。
图6B是连接到一个示例性的半导体器件的焊盘44的夹58的概念性横截面图。半导体器件包括带有包围开口28的玻璃结构24的半导体部件22。铆钉58a直通进入开口28。铆钉58a未弯曲。为了固定铆钉58a，开口28可以部分地填充粘合剂56。粘合剂56可以是导电膏。粘合剂56可以是焊料。铆钉58a可以延伸到粘合剂中。当附接到焊盘44时，可能不需要弯曲夹或对夹施加任何力。直径d可以是大约500至700μm。焊盘44的表面与第二部分58b的上表面之间的距离可以是大约1.25mm至1.3mm。夹58结合了用于小接触的长的垂直尺寸与宽的夹表面区域。通过将垂直的第一部分58a铆接到大的第二部分58b，可以将夹插入到由高的玻璃结构或高的边沿包围的小的接合焊盘开口28中。如果开口28的深度/宽度纵横比太大，则可能无法通过接合导线接触焊盘44。夹58可以容易地适应电流、导通电阻和封装体设计要求。
图7A是根据一个示例的弯曲的夹60的概念性透视图。夹60可以包括第一部分60a和第二部分60b。第一部分和第二部分可以由金属片一体地形成。金属片可以是铜片。第一部分60a的横截面的长度d1和宽度d2可适配于待接触的焊盘的表面。长度d1和宽度d2可以是大约500至700μm。横截面d1×d2可以对应于焊盘的表面p1×p2。第一部分60a的横截面可以与第二部分60b的横截面相同。第一部分60a可以将长的垂直尺寸与小的源接触部相结合。
图7B是根据一个示例的弯曲的夹62的概念性透视图。夹62与夹60的不同之处在于，第一部分62a的横截面可以与第二部分62b的横截面不相同。第二部分62b可以包括具有与第一部分62a的横截面相同的横截面的部分62b.1。部分62b.1可以连接到端子。第二部分62b可以包括可以大于第一部分62a且大于部分62b.1的部分62b.2。部分62b.2可以是可缩放的表面积。可缩放的表面积可以例如通过冲压或蚀刻实现。该面积不受另一种方法限制。
图7C是连接到一个示例性的半导体器件的焊盘44的夹60或夹62的概念性横截面图。半导体器件包括带有包围开口28的玻璃结构24的半导体部件22。第一部分62a(或60a)直通进入开口28。为了固定第一部分60a、62a，开口28可以部分地填充粘合剂56。粘合剂56可以是导电膏。粘合剂56可以是焊料。第一部分60a、62a可以延伸到粘合剂中。当附接到焊盘44时，可能不需要弯曲夹60、62或对夹60、62施加任何力。夹60、62将用于小接触的长的垂直尺寸与宽的夹表面区域相结合。可以将夹插入到由高的玻璃结构或高的边沿包围的小的接合焊盘开口28中。夹60、62可以容易地适配于电流、导通电阻和封装体设计要求。
示例
在下面，使用特定示例进一步描述用于加工半导体晶片的方法以及半导体晶片、半导体器件和夹。
示例1是一种用于加工半导体晶片的方法，所述方法包括：提供包括第一主表面和与第一主表面相反的第二主表面的半导体晶片；在半导体晶片内部产生缺陷，所述缺陷限定出平行于第一主表面的脱离平面；加工第一主表面以限定出多个电子半导体部件；提供玻璃结构，所述玻璃结构包括多个开口；将所述玻璃结构附接到经加工的第一主表面，所述多个开口中的每个分别使多个电子半导体部件的相应区域未被覆盖；将聚合物层施加到第二主表面；通过将聚合物层冷却到其玻璃化转变温度以下，将半导体晶片分裂成半导体切片和剩留的半导体晶片，所述半导体切片在第一主表面与脱离表面之间延伸并包括多个电子半导体部件。
示例2是示例1的方法，其中，所述方法还包括在从半导体晶片分裂出半导体切片之前，将另外的聚合物层施加到第一主表面。
示例3是示例1的方法，其中，半导体切片的厚度为大约100μm或小于100μm、优选为大约50μm或小于50μm。
示例4是示例1的方法，其中，玻璃结构的厚度至少是半导体切片的厚度的四倍。
示例5是示例1的方法，其中，多个电子部件通过切口线分开，所述切口线被玻璃结构覆盖。
示例6是示例5的方法，其中，所述方法还包括将带有附接的玻璃结构的半导体切片沿着切口线分割成半导体芯片。
示例7是示例1的方法，其中，所述方法还包括将夹电连接到焊盘，所述焊盘布置在第一主表面上未被玻璃结构覆盖的相应区域中。
示例8是示例7的方法，所述夹包括具有比连接到所述焊盘的玻璃结构的厚度大的长度的第一部分；以及被构造成延伸到端子的第二部分。
示例9是示例8的方法，所述夹包括形成铆接到第二部分的第一部分的铆钉以及被弯曲以形成第一部分和第二部分的单件中的至少一个。
示例10是示例7的方法，其中，将夹连接到焊盘包括将粘合剂填充到玻璃结构的相应开口中。
示例11是示例1的方法，其中，所述方法还包括用剩留的半导体晶片作为半导体晶片重新开始所述方法。
示例12是一种半导体晶片，包括：第一主表面和与第一主表面相反的第二主表面；半导体晶片内部的平行于第一主表面的脱离平面，所述脱离平面由缺陷限定；形成在第一主表面处和第一主表面与脱离平面之间的多个电子半导体部件；附接到第一主表面的玻璃结构，所述玻璃结构包括多个开口，所述多个开口中的每个分别使多个电子半导体部件的相应区域未被覆盖。
示例13是一种用于电连接布置在玻璃结构中的开口的底部上的焊盘的夹，所述夹包括形成夹的第一部分的铆钉以及被弯曲以形成第一部分和第二部分的单件金属片中的至少一个，所述铆钉铆接到夹的第二部分，其中，第二部分被构造成延伸到端子，第一部分具有为开口的宽度的大约一半或更大的宽度并且被构造成直通延伸到开口的底部。
示例14是一种半导体器件，包括：具有第一主表面和与第一主表面相反的第二主表面的半导体芯片，所述第一主表面包括焊盘和玻璃结构，所述玻璃结构包括开口，所述开口的边沿包围所述焊盘，其中，包围所述开口的玻璃结构的厚度与所述开口的宽度之间的纵横比为一到三或更大；载体，半导体芯片以面对所述载体的第二主表面安装在所述载体上；所述开口的底部上的粘合剂；电连接所述焊盘的夹，所述夹包括形成所述夹的第一部分的铆钉以及被弯曲以形成第一部分和第二部分的单件中的至少一个，所述铆钉铆接到所述夹的第二部分，其中，所述第二部分被构造成延伸到载体上的端子，并且所述第一部分被构造成直通延伸到所述开口的底部，所述第一部分具有为开口的宽度的大约一半或更大的宽度，并借助于粘合剂电连接到所述焊盘。
示例15是示例14的半导体器件，其中，半导体芯片是垂直功率部件。
虽然已经结合一个或多个实施方式说明和描述了本公开，但是在不脱离所附权利要求的精神和范围的情况下，可以对所说明的示例进行改变和/或修改。特别是关于由上述构件或结构(组件、装置、电路、系统等)执行的各种功能，除非另外指出，否则用于描述这些构件的术语(包括对“措施”的引述)意欲对应于执行所描述的构件的指定功能的任何构件或结构(例如，在功能上等同的)，即使在结构上不等同于本文所示的本公开的示例性实施方式中执行该功能所公开的结构。

Claims (15)

1.一种用于加工半导体晶片的方法，所述方法包括：
提供包括第一主表面和与所述第一主表面相反的第二主表面的半导体晶片；
在半导体晶片内部产生缺陷，所述缺陷限定出平行于所述第一主表面的脱离平面；
加工所述第一主表面，以限定出多个电子半导体部件；
提供玻璃结构，所述玻璃结构包括多个开口；
将玻璃结构附接到经加工的第一主表面，所述多个开口中的每个分别使所述多个电子半导体部件的相应区域未被覆盖；
将聚合物层施加到第二主表面；
通过将聚合物层冷却到其玻璃化转变温度以下，将半导体晶片分裂成半导体切片和剩留的半导体晶片，所述半导体切片在第一主表面与脱离平面之间延伸并且包括所述多个电子半导体部件。
2.根据权利要求1所述的方法，其中，所述方法还包括：在将所述半导体切片从所述半导体晶片分裂之前，将另外的聚合物层施加到所述第一主表面。
3.根据前述权利要求中任一项所述的方法，其中，所述半导体切片的厚度为大约或小于100μm、优选为大约或小于50μm。
4.根据前述权利要求中任一项所述的方法，其中，所述玻璃结构的厚度是所述半导体切片的厚度的至少四倍。
5.根据前述权利要求中任一项所述的方法，其中，所述多个电子部件通过切口线分离，所述切口线被所述玻璃结构覆盖。
6.根据权利要求5所述的方法，其中，所述方法还包括：将带有所述附接的玻璃结构的所述半导体切片沿着所述切口线划分割成半导体芯片。
7.根据前述权利要求中任一项所述的方法，其中，所述方法还包括：将夹电连接到焊盘，所述焊盘布置在所述第一主表面上未被所述玻璃结构覆盖的相应区域中。
8.根据权利要求7所述的方法，其中，所述夹包括：
长度大于连接到焊盘的玻璃结构的厚度的第一部分；以及
被构造成延伸到端子的第二部分。
9.根据权利要求8所述的方法，其中，所述夹包括以下中的至少一个：
-形成铆接到第二部分的第一部分的铆钉；
-被弯曲以形成第一部分和第二部分的单件。
10.根据权利要求7至9中任一项所述的方法，其中，将所述夹连接到所述焊盘包括将粘合剂填充到所述玻璃结构的相应开口中。
11.根据前述权利要求中任一项所述的方法，其中，所述方法还包括：用剩留的半导体晶片作为半导体晶片重新开始所述方法。
12.一种半导体晶片，包括：
第一主表面和与第一主表面相反的第二主表面；
半导体晶片内部的平行于第一主表面的脱离平面，所述脱离平面由缺陷限定；
形成在第一主表面处且在第一主表面与脱离平面之间的多个电子半导体部件；
附接到第一主表面的玻璃结构，所述玻璃结构包括多个开口，所述多个开口中的每个分别使所述多个电子半导体部件的相应区域未被覆盖。
13.一种用于电连接布置在玻璃结构中的开口的底部上的焊盘的夹，所述夹包括以下中的至少一个：
-形成夹的第一部分的铆钉，所述铆钉铆接到所述夹的第二部分；
-被弯曲以形成第一部分和第二部分的单件金属片，
其中，所述第二部分被构造成延伸到端子，所述第一部分具有为开口的宽度的大约一半或更大的宽度，并且被构造成直通延伸到所述开口的底部。
14.一种半导体器件，包括：
具有第一主表面和与第一主表面相反的第二主表面的半导体芯片，所述第一主表面包括焊盘和玻璃结构，所述玻璃结构包括开口，所述开口的边沿包围所述焊盘，其中，包围所述开口的所述玻璃结构的厚度与所述开口的宽度之间的纵横比为一到三或更大；
载体，所述半导体芯片以第二主表面面对所述载体的方式安装在所述载体上；
所述开口的底部上的粘合剂；
电连接焊盘的夹，所述夹包括以下中的至少一个：
-形成夹的第一部分的铆钉，所述铆钉铆接到夹的第二部分；
-被弯曲以形成第一部分和第二部分的单件；
其中，所述第二部分被构造成延伸到载体上的端子，并且所述第一部分被构造成直通延伸到所述开口的底部，所述第一部分具有为开口的宽度的大约一半或更大的宽度，并且借助于粘合剂电连接到焊盘。
15.根据权利要求14所述的半导体器件，其中，所述半导体芯片是垂直功率部件。
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