CN113447787B - Power semiconductor device aging on-line diagnosis method - Google Patents

Abstract

The invention discloses an aging online diagnosis method for power semiconductor devices. The method is based on the characteristics of specific electrical parameters corresponding to different junction temperatures under different aging degrees of power semiconductor devices, and establishes its aging diagnosis model about junction temperature; The electrical data of the semiconductor device is combined with the heat-sensitive electrical parameter method and the thermal resistance network method to estimate the junction temperature respectively. By comparing the two estimated junction temperatures obtained, the judgment of the aging type of the power semiconductor device is realized, and then the aging degree is realized. Diagnosis and life estimation; this method improves the safety and economic benefits of power semiconductor devices, and is a new idea in the field of aging pre-diagnosis of power semiconductor devices.

Description

A method for on-line diagnosis of power semiconductor device aging

technical field

The invention relates to the technical field of power electronic equipment health management, in particular to an on-line aging diagnosis method for power semiconductor devices.

Background technique

According to the research report on the reliability of power electronic systems, power semiconductor devices have the highest failure rate in the converter system, accounting for about 34%. Among various failure factors, the failure of power electronic systems induced by temperature factors accounts for as high as 55%. A large number of test statistical data and failure mechanism analysis show that factors such as the swing range of junction temperature, maximum junction temperature, average junction temperature, minimum case temperature and cycle conduction time of power devices determine the maximum temperature they can experience before failure. number of cycles. Therefore, the accurate extraction and detection of the junction temperature of IGBT in power semiconductor devices is the basis for its aging state diagnosis, service life estimation, health state management and reliability state assessment.

The aging of power semiconductor devices can be mainly divided into chip aging and package aging. Most of the existing research on aging analysis technology studies the junction temperature change of the device from the perspective of thermally sensitive parameters, and offline analysis is mapped to the failure degree of the device, which has not yet reached practicality. There is a lack of an online diagnostic method that takes into account both the determination of the aging type and the estimation of the aging degree of power semiconductor devices.

Contents of the invention

In order to solve the problems of the prior art, the purpose of the present invention is to overcome the deficiencies of the prior art and provide an on-line diagnosis method for the aging of power semiconductor devices. Taking IGBT as an example, it is proposed to pass the accelerated aging test without destroying the module package. , test and analyze the aging characteristics of power devices, study the junction temperature change in the failure process of IGBT, including thermal sensitive electrical parameter method and thermal resistance network method, compare the junction temperature detection results of the two methods, and determine the type and degree of IGBT aging In order to obtain a multi-objective control that takes into account both economic benefits and equipment reliability, and then provides a reference for the health management of power semiconductor devices, mainly the pre-diagnosis technology of aging factor failures.

In order to achieve the above invention creation purpose, the present invention adopts the following technical solutions:

An on-line diagnosis method for the aging of power semiconductor devices, which uses a junction temperature estimation method to judge the degree of conduction power offset, thereby judging the degree of aging; it includes two situations:

(1) Based on the electrothermal characteristics of power semiconductor devices, according to the characteristics of specific electrical parameters corresponding to different junction temperatures under different aging degrees of power semiconductor devices, compare the size of the two junction temperature parameters obtained by the heat-sensitive electrical parameter method and the thermal resistance network method, and judge The type of aging of power semiconductor devices, that is, chip aging or package aging;

(2) On the basis of the determination of the aging type, compare the deviation degree of the conduction power data of the power semiconductor device in the actual working condition and the conduction power data of the normal power semiconductor device, and realize the diagnosis of the aging degree of the power semiconductor device.

Preferably the power semiconductor device is an IGBT.

Preferably, the method for monitoring the junction temperature of a power semiconductor device includes:

(1) The thermally sensitive electrical parameter method is used to estimate the junction temperature. The conduction power P ₀ is selected as the power at the moment t ₀ at the end of the conduction state, that is, before the start of the turn-off process, then P ₀ =v _ce (t ₀ ) ·ic ( _{t 0} ) is a thermally sensitive electrical parameter, and establishes the three-dimensional mapping relationship of conduction power-current-junction temperature; according to the conduction current I _c = _ic (t ₀ ) and conduction Pass power P ₀ to obtain the first estimated junction temperature T _j1 ;

(2) The method of estimating the junction temperature by the thermal resistance network method extracts the thermal resistance parameters of unpackaged and aging power semiconductor devices, and constructs an electrothermal model, that is, the thermal resistance network Z _th = (T _j -T _c )/P = ΔT/ΔP. Case temperature T _c =T _c (t ₀ ) and thermal power data p(t ₀ ) are substituted to obtain a second estimated junction temperature T _j2 .

Preferably, the determination of the type of aging is implemented as follows:

Two junction temperature parameters are used: the first estimated junction temperature T _j1 obtained by the thermally sensitive electrical parameter junction temperature estimation method based on conduction power, and the second estimated junction temperature T _j2 obtained by the thermal resistance network junction temperature estimation method;

If T _j1 <T _j2 , the aging type of the power semiconductor device is chip aging. When the power semiconductor device has chip aging but no package aging, the first estimated junction temperature T _j1 obtained by the thermally sensitive electrical parameter junction temperature estimation method based on the conduction power established by the normal model after chip aging is less than the power semiconductor at this time The actual junction temperature of the device, while the aging of the chip does not affect the inherent characteristics of the package, that is, the thermal impedance parameters of the package remain unchanged, and the second estimated junction temperature T _j2 obtained based on the thermal resistance network junction temperature estimation method is the actual junction temperature of the power semiconductor device at this time. junction temperature;

If T _j1 >T _j2 , the aging type of the power semiconductor device is packaging aging. When the package aging of the power semiconductor device occurs without chip aging, the package aging does not affect the inherent characteristics of the chip, and the first estimated junction temperature T _j1 is obtained based on the thermally sensitive electrical parameter junction temperature estimation method of the conduction power established by the normal model For the actual junction temperature of the power semiconductor device at this time, the second estimated junction temperature T _j2 obtained based on the normal thermal resistance network junction temperature estimation method is smaller than the actual junction temperature of the power semiconductor device at this time.

Preferably, the estimation of the aging degree is realized as follows:

Keep the shell temperature _Tc of the power semiconductor device constant, and the conduction power P1 corresponding to the conduction current _Ic at the moment _t0 at the end of the conduction state in the switching cycle, that is, before the start of the turn _- off process in the temperature calibration experiment; actual operating conditions The same case temperature T _c and the same conduction current I _c correspond to another conduction power P ₂ ;

P ₂ -P ₁ , aging occurs, and the aging degree of the power semiconductor device is characterized by the deviation of conduction power ΔP=P ₂ -P ₁ .

Preferably, the establishment of the junction temperature estimation model based on the heat-sensitive electrical parameter method of conduction power and the thermal resistance network method includes the following four steps:

Step 1: Temperature calibration experiment, extraction of normal IGBT inherent parameters, select a specific IGBT to test on the temperature calibration platform, adopt the control variable method, and measure the set value of the IGBT in a single switching cycle under a certain current gradient and junction temperature gradient respectively. Electrode current _{ic and collector-emitter voltage v ce parameter} signals;

Step 2: Offline data processing, obtaining the conduction power of each experimental sample, and establishing a three-dimensional mapping relationship table of conduction power-current-junction temperature;

Step 3: Extract the thermal resistance network parameters of the IGBT according to the tested IGBT data sheet;

Step 4: Build the electrothermal model of the IGBT according to the extracted thermal resistance network parameters.

Preferably, the realization of the junction temperature estimation based on the heat-sensitive electrical parameter method of conduction power and the thermal resistance network method includes the following two steps:

Step 1: Data sampling, sensing the case temperature T _c , collector-emitter voltage v _ce , and collector current ic of the power semiconductor device at the moment _{t 0} at the end of the conduction state within a switching cycle, that is, before the start of the turn-off process, Then obtain the conduction current I _c , the corresponding conduction power P ₁ and thermal power data p(t ₀ )=v _ce (t ₀ )·ic ( _{t 0} );

Step 2: Obtaining the junction temperature, substituting the conduction current _Ic and the corresponding conduction power P1 into the _first estimated junction temperature _Tj1 obtained from the three-dimensional mapping relationship table of conduction power-current-junction temperature established in claim 5; The second estimated junction temperature T _j2 is obtained by substituting the case temperature T _c and the thermal power data p(t ₀ ) into the electrothermal model established in claim 5 .

Preferably, when the conduction current _Ic and the corresponding conduction power P1 are substituted into the _first estimated junction temperature T _j1 obtained from the three-dimensional mapping relationship table of conduction power-current-junction temperature, the thermal power based on conduction power is used. Sensitive electrical parameter junction temperature estimation method; when substituting the case temperature T _c and thermal power data p(t ₀ ) into the second estimated junction temperature T _j2 obtained by the electrothermal model established in claim 5, the junction temperature estimation based on the thermal resistance network is used method.

Preferably, the thermally sensitive electrical parameter junction temperature estimation method based on conduction power P ₀ is replaced by other thermally sensitive electrical parameters according to actual conditions, such as conduction voltage drop v _ce and turn-off delay time t _{d_off} .

Compared with the prior art, the present invention has the following obvious outstanding substantive features and significant advantages:

1. The online diagnosis method for power semiconductor device aging of the present invention uses the key aging factor—junction temperature for aging diagnosis;

2. The present invention monitors the junction temperature based on the thermally sensitive electrical parameter junction temperature estimation method of conduction power and the thermal resistance network junction temperature estimation method, and realizes the determination of the aging type of the power semiconductor device by comparing the two estimated junction temperatures. Then realize the diagnosis of aging degree and life estimation, improve the safety and economic benefits of power semiconductor devices, and provide a new idea for the future online diagnosis research of power semiconductor device aging;

3. The method of the present invention is simple and easy to implement, low in cost, and suitable for popularization and use.

Description of drawings

FIG. 1 is a schematic diagram of an on-line diagnosis method for power semiconductor device aging according to the present invention.

Fig. 2 is a flow chart of the present invention for determining the type of aging and diagnosing the degree of aging.

FIG. 3 is a schematic diagram of establishing a junction temperature estimation model of the present invention.

Fig. 4 is a schematic diagram of the temperature calibration test platform of the present invention.

Fig. 5 is a schematic diagram of the temperature calibration test system of the present invention.

Fig. 6 is a schematic diagram of the waveforms of the collector-emitter voltage v _ce and the collector current _ic in one switching cycle of the present invention.

FIG. 7 is a three-dimensional relationship diagram of conduction power-current-junction temperature in the present invention.

detailed description

Below in conjunction with specific implementation example, above-mentioned scheme is described further, and preferred embodiment of the present invention is described in detail as follows:

Embodiment one:

In this embodiment, referring to FIG. 1 , an on-line diagnosis method for the aging of power semiconductor devices uses a junction temperature estimation method to judge the degree of conduction power offset, thereby judging the degree of aging; it includes two situations:

(1) Based on the electrothermal characteristics of power semiconductor devices, according to the characteristics of specific electrical parameters corresponding to different junction temperatures under different aging degrees of power semiconductor devices, compare the size of the two junction temperature parameters obtained by the heat-sensitive electrical parameter method and the thermal resistance network method, and judge The type of aging of power semiconductor devices, that is, chip aging or package aging;

(2) On the basis of the determination of the aging type, compare the deviation degree of the conduction power data of the power semiconductor device in the actual working condition and the conduction power data of the normal power semiconductor device, and realize the diagnosis of the aging degree of the power semiconductor device.

Among them, the power semiconductor device junction temperature monitoring method includes:

(1) The thermally sensitive electrical parameter method is used to estimate the junction temperature. The conduction power P ₀ is selected as the power at the moment t ₀ at the end of the conduction state, that is, before the start of the turn-off process, then P ₀ =v _ce (t ₀ ) ·ic ( _{t 0} ) is a thermally sensitive electrical parameter, and establishes the three-dimensional mapping relationship of conduction power-current-junction temperature; according to the conduction current I _c = _ic (t ₀ ) and conduction Pass power P ₀ to obtain the first estimated junction temperature T _j1 ;

(2) The method of estimating the junction temperature by the thermal resistance network method extracts the thermal resistance parameters of unpackaged and aging power semiconductor devices, and constructs an electrothermal model, that is, the thermal resistance network Z _th = (T _j -T _c )/P = ΔT/ΔP. Case temperature T _c =T _c (t ₀ ) and thermal power data p(t ₀ ) are substituted to obtain a second estimated junction temperature T _j2 .

As shown in Figure 2, the determination of the aging type of the power semiconductor device is implemented as follows:

Two junction temperature parameters are used: the first estimated junction temperature T _j1 obtained by the thermally sensitive electrical parameter junction temperature estimation method based on conduction power, and the second estimated junction temperature T _j2 obtained by the thermal resistance network junction temperature estimation method;

If T _j1 <T _j2 , the aging type of the power semiconductor device is chip aging. When the power semiconductor device has chip aging but no package aging, the first estimated junction temperature T _j1 obtained by the thermally sensitive electrical parameter junction temperature estimation method based on the conduction power established by the normal model after chip aging is less than the power semiconductor at this time The actual junction temperature of the device, while the aging of the chip does not affect the inherent characteristics of the package, that is, the thermal impedance parameters of the package remain unchanged, and the second estimated junction temperature T _j2 obtained based on the thermal resistance network junction temperature estimation method is the actual junction temperature of the power semiconductor device at this time. junction temperature;

If T _j1 >T _j2 , the aging type of the power semiconductor device is packaging aging. When the package aging of the power semiconductor device occurs without chip aging, the package aging does not affect the inherent characteristics of the chip, and the first estimated junction temperature T _j1 is obtained based on the thermally sensitive electrical parameter junction temperature estimation method of the conduction power established by the normal model For the actual junction temperature of the power semiconductor device at this time, the second estimated junction temperature T _j2 obtained based on the normal thermal resistance network junction temperature estimation method is smaller than the actual junction temperature of the power semiconductor device at this time.

The estimation of the degree of aging is achieved as follows:

Keep the shell temperature _Tc of the power semiconductor device constant, and the conduction power P1 corresponding to the conduction current _Ic at the moment _t0 at the end of the conduction state in the switching cycle, that is, before the start of the turn _- off process in the temperature calibration experiment; actual operating conditions The same case temperature T _c and the same conduction current I _c correspond to another conduction power P ₂ ;

P ₂ -P ₁ , aging occurs, and the aging degree of the power semiconductor device is characterized by the deviation of conduction power ΔP=P ₂ -P ₁ .

As shown in Figure 3, the establishment of the junction temperature estimation model based on the thermally sensitive electrical parameter method of the conduction power and the thermal resistance network method mainly includes the following four steps:

Step 1: Temperature calibration experiment, extraction of normal IGBT inherent parameters, select a specific IGBT to test on the temperature calibration platform, adopt the control variable method, and measure the set value of the IGBT in a single switching cycle under a certain current gradient and junction temperature gradient respectively. Electrode current _{ic and collector-emitter voltage v ce parameter} signals;

Step 2: Offline data processing, obtaining the conduction power of each experimental sample, and establishing a three-dimensional mapping relationship table of conduction power-current-junction temperature;

Step 3: Extract the thermal resistance network parameters of the IGBT according to the tested IGBT data sheet;

Step 4: Build the electrothermal model of the IGBT according to the extracted thermal resistance network parameters.

Among them, step 1 and step 2 are implemented on the temperature calibration platform shown in Figure 4, and the schematic diagram shown in Figure 5 uses a single-phase inverter circuit for double-pulse testing, and selects Infineon's IGBT module (model: FF50R12RT4) for testing. During the experiment, start the heating plates on both sides of the module to be tested. After the temperature controller shows that the temperature is stable and maintains for 15 minutes, it can be considered that the temperature of the chip in the module is the same as that in the box. By changing the pulse width of the first pulse The width of the collector current at the turn-off time is adjustable to 10A, 15A, 20A, 25A, 30A, 35A, 40A, and the collector-emitter voltage v _ce and collector current in a single switching cycle of the IGBT are tested at 30, 60, 90, and 120°C respectively ic , record test data, the waveforms of collector-emitter voltage v _ce and collector current _ic in _a single switching cycle are shown in Figure 6; conduct data analysis offline, establish a mapping relationship table of conduction power-current-junction temperature, and conduct Data fitting, filling blank data, and drawing a three-dimensional relationship diagram of conduction power-current-junction temperature.

As shown in FIG. 7 , the three-dimensional relationship diagram of conduction power-current-junction temperature is used to verify the correctness of an online diagnosis method for aging of power semiconductor devices proposed in this patent by using aging tests. It can be seen that under the same working conditions, the first estimated junction temperature T _j1 obtained by the thermally sensitive electrical parameter junction temperature estimation method based on conduction power and the second estimated junction temperature obtained by the junction temperature estimation method based on thermal resistance network under different aging degrees T _j2 has a certain deviation. The results show that the junction temperature of IGBT is affected by the degree of aging. For the research on the aging state of IGBT, the thermal resistance network method and the thermal sensitive electrical parameter method can be used to establish a joint model to finally determine the aging state of IGBT.

In this embodiment, according to the electrical data of the power semiconductor device in the actual working condition, the junction temperature is estimated separately by combining the heat-sensitive electrical parameter method and the thermal resistance network method, and the judgment of the aging type of the power semiconductor device is realized by comparing the two estimated junction temperatures , and then realize the diagnosis of aging degree and life estimation.

Embodiment two:

In this embodiment, it is basically the same as in Embodiment 1, the difference is that:

The thermally sensitive electrical parameter junction temperature estimation method based on conduction power in the described online diagnosis method for aging of power semiconductor devices can be replaced by other thermally sensitive electrical parameters according to the actual situation, such as: conduction voltage drop v _ce , off Off delay time t _{d_off} . Reduce system sampling and computing costs, more economical and real-time.

The online diagnostic method for power semiconductor device aging in the above-mentioned embodiment, this method is based on the characteristics of specific electrical parameters corresponding to different junction temperatures under different aging degrees of power semiconductor devices, and establishes its aging diagnosis model about junction temperature; according to the actual operating conditions of power semiconductor devices Electrical data, combined with heat-sensitive electrical parameter method and thermal resistance network method to estimate the junction temperature separately, through the comparison of the two estimated junction temperatures, the judgment of the aging type of the power semiconductor device is realized, and then the diagnosis of the aging degree and the life estimation are realized; the The method improves the safety and economic benefits of power semiconductor devices, and is a new idea in the field of aging pre-diagnosis of power semiconductor devices.

The embodiment of the present invention has been described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned embodiment, and various changes can also be made according to the purpose of the invention of the present invention. The changes, modifications, substitutions, combinations or simplifications should all be equivalent replacement methods, as long as they meet the purpose of the invention, as long as they do not deviate from the technical principle and inventive concept of the invention, they all belong to the protection scope of the invention.

Claims (4)

1. A power semiconductor device aging on-line diagnosis method is characterized in that, adopts junction temperature estimation method, judges conduction power excursion degree, thereby judges degree of aging; Include two kinds of situations: (1) Based on the electrothermal characteristics of power semiconductor devices, according to the characteristics of specific electrical parameters corresponding to different junction temperatures under different aging degrees of power semiconductor devices, compare the size of the two junction temperature parameters obtained by the heat-sensitive electrical parameter method and the thermal resistance network method, and judge The aging type of power semiconductor devices, that is, chip aging or packaging aging; the determination of the aging type is implemented as follows: Two junction temperature parameters are used: the first estimated junction temperature T _j1 obtained by the thermally sensitive electrical parameter junction temperature estimation method based on conduction power, and the second estimated junction temperature T _j2 obtained by the thermal resistance network junction temperature estimation method; If T _j1 <T _j2 , the aging type of power semiconductor devices is chip aging; If T _j1 >T _j2 , the aging type of power semiconductor devices is package aging; (2) On the basis of the determination of the aging type, compare the deviation degree of the conduction power data of the power semiconductor device in the actual working condition and the conduction power data of the normal power semiconductor device, and realize the diagnosis of the aging degree of the power semiconductor device; The diagnosis of the aging degree is realized as follows: Keep the shell temperature _Tc of the power semiconductor device constant, and the conduction power P1 corresponding to the conduction current _Ic at the moment _t0 at the end of the conduction state in the switching cycle, that is, before the start of the turn _- off process in the temperature calibration experiment; actual operating conditions The same case temperature T _c and the same conduction current I _c correspond to another conduction power P ₂ ; The aging degree of the power semiconductor device is characterized by the deviation of conduction power ΔP=P ₂ −P ₁ . 2. power semiconductor device aging online diagnosis method as claimed in claim 1, is characterized in that, described power semiconductor device junction temperature estimation method comprises: (1) The thermally sensitive electrical parameter method is used to estimate the junction temperature. The conduction power P ₀ is selected as the power at the moment t ₀ at the end of the conduction state, that is, before the start of the turn-off process, then P ₀ =v _ce (t ₀ ) ·ic ( _{t 0} ) is a thermally sensitive electrical parameter, and establishes the three-dimensional mapping relationship of conduction power-current-junction temperature; according to the conduction current I _c = _ic (t ₀ ) and conduction Through power P ₀ , get the first estimated junction temperature T _j1 ; collector-emitter voltage v _ce , collector current _ic ; (2) The method of estimating the junction temperature by the thermal resistance network method extracts the thermal resistance parameters of unpackaged and aging power semiconductor devices, and constructs an electrothermal model, that is, the thermal resistance network Z _th = (T _j2 -T _c )/P, where T _c is the shell temperature, P is the thermal power, substituting the case temperature T _c and the thermal power P to obtain the second estimated junction temperature T _j2 . 3. power semiconductor device aging on-line diagnosis method as claimed in claim 2, is characterized in that, the junction temperature estimation model establishment based on the thermosensitive electrical parameter method of conduction power and thermal resistance network method comprises following four steps: Step 1: Temperature calibration experiment, extraction of normal IGBT inherent parameters, select a specific IGBT to test on the temperature calibration platform, adopt the control variable method, and measure the set value of the IGBT in a single switching cycle under a certain current gradient and junction temperature gradient respectively. Electrode current _{ic and collector-emitter voltage v ce parameter} signals; Step 2: Offline data processing, obtaining the conduction power of each experimental sample, and establishing a three-dimensional mapping relationship table of conduction power-current-junction temperature; Step 3: Extract the thermal resistance network parameters of the IGBT according to the tested IGBT data sheet; Step 4: Build the electrothermal model of the IGBT according to the extracted thermal resistance network parameters. 4. as described in any one of claim 1-3 aging on-line diagnosis method of power semiconductor device, it is characterized in that, the junction temperature estimation realization based on the heat-sensitive electric parameter method of conduction power and thermal resistance network method comprises following two step: Step 1: Data sampling, collecting the case temperature T _c , collector-emitter voltage v _ce , and collector current ic of the power semiconductor device at the moment _{t 0} at the end of the conduction state within a switching cycle, that is, before the start of the turn-off process, and then Obtain conduction current I _c , corresponding conduction power P ₀ and thermal power P; Step 2: Obtain the junction temperature, and substitute the conduction current I _c and the corresponding conduction power P ₀ into the three-dimensional mapping relationship table of conduction power-current-junction temperature to obtain the first estimated junction temperature T _j1 ; the case temperature T _c and The thermal power P is substituted into the electrothermal model to obtain the second estimated junction temperature T _j2 .

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