CN113437974A

CN113437974A - Single-slope analog-to-digital converter calibration method and system

Info

Publication number: CN113437974A
Application number: CN202110796454.4A
Authority: CN
Inventors: 吴梦施; 何佳; 刘俊
Original assignee: Hangzhou Hikmicro Sensing Technology Co Ltd
Current assignee: Hangzhou Hikmicro Sensing Technology Co Ltd
Priority date: 2021-07-14
Filing date: 2021-07-14
Publication date: 2021-09-24
Anticipated expiration: 2041-07-14
Also published as: CN113437974B

Abstract

The embodiment of the application provides a calibration method and a calibration system for a single-slope analog-to-digital converter, which are used for acquiring the lower limit number and the median number of the preset digital output range of a single-slope ADC to be corrected and acquiring the lower limit voltage and the median voltage of the preset voltage analog conversion range of the single-slope ADC to be corrected, wherein the lower limit number is not zero; inputting the lower limit voltage into the single slope ADC to be corrected, and adjusting the offset calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be corrected to be a lower limit number, and obtain the offset calibration value at the moment as a target offset calibration value; and inputting the median voltage into the single slope ADC to be corrected, carrying out offset calibration on the single slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be corrected to be the median number and obtain the gain calibration value at the moment as the target gain calibration value. Calibration of the single-slope ADC is achieved.

Description

Single-slope analog-to-digital converter calibration method and system

Technical Field

The present application relates to the field of analog signal processing technologies, and in particular, to a calibration method and system for a single slope analog-to-digital converter.

Background

In the field of integrated circuits, a single-ramp ADC (Analog-to-Digital Converter) is widely used for on-chip Digital signal processing, such as various detectors and sensors, due to its advantages of simple structure and low cost. The operating principle of a single ramp ADC is shown in fig. 1. The ramp generator outputs a ramp signal of a specific slope at a certain time, the ramp signal is compared with the analog input signal, the comparator outputs a high level when the ramp signal is smaller than the analog input signal, and the comparator outputs a low level when the ramp signal is larger than the analog input signal, thereby generating a pulse signal of which the high level width is in direct proportion to the amplitude of the analog input voltage. At the same time, the clock pulse is used to measure the width of the pulse signal and the measurement result is given in the form of digital code, thereby completing the conversion of analog signal to digital signal.

In the conversion process from analog signals to digital signals, the slope of the ramp signal and the starting time of the ramp generator and the counter directly influence the output pulse width of the comparator and the clock pulse counting, and further influence the analog-to-digital conversion result. In order to make the analog-to-digital conversion characteristics of the single-slope ADC meet the design requirements and improve the accuracy of the single-slope ADC, the single-slope ADC must be calibrated.

Disclosure of Invention

An object of the embodiments of the present application is to provide a calibration method and system for a single-slope analog-to-digital converter, so as to calibrate a single-slope ADC. The specific technical scheme is as follows:

in a first aspect, an embodiment of the present application provides a method for calibrating a single-slope analog-to-digital converter, where the method includes:

acquiring a lower limit number and a median number of a preset digital output range of a to-be-corrected single slope analog-to-digital converter (ADC), and acquiring a lower limit voltage and a median voltage of a preset voltage analog conversion range of the to-be-corrected single slope ADC, wherein the lower limit number is not zero;

inputting the lower limit voltage into the single slope ADC to be corrected, and adjusting the offset calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be corrected to be the lower limit number, and obtain the offset calibration value at the moment as a target offset calibration value;

inputting the median voltage into the single slope ADC to be corrected, carrying out offset calibration on the single slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be corrected to be the median number, and obtain the gain calibration value at the moment as the target gain calibration value.

In a possible embodiment, the inputting the lower limit voltage into the single-slope ADC to be corrected, and adjusting the offset calibration value of the single-slope ADC to be corrected so that the number output by the single-slope ADC to be corrected is the lower limit number, and the offset calibration value at this time is the target offset calibration value includes:

setting the current digit to be adjusted of the offset calibration value to be adjusted to be 1, wherein each digit of the initial offset calibration value to be adjusted is 0, and the initial digit to be adjusted is the highest digit of the offset calibration value to be adjusted;

inputting the lower limit voltage into the to-be-corrected single slope ADC, performing gain calibration on the to-be-corrected single slope ADC based on a preset gain calibration value, and performing offset calibration on the to-be-corrected single slope ADC based on a current to-be-adjusted offset calibration value to obtain a numerical value output by the to-be-corrected single slope ADC;

if the currently output numerical value is not less than the lower limit number, keeping the current digit to be adjusted in the offset calibration value to be adjusted to be 1;

if the currently output numerical value is smaller than the lower limit number, setting the current digit to be adjusted in the offset calibration value to be adjusted to be 0;

selecting the next digit in the offset calibration value to be adjusted as the digit to be adjusted, and returning to the execution step: and setting the current digit to be adjusted of the offset calibration value to be adjusted to be 1 until the current digit to be adjusted is the last digit of the offset calibration value to be adjusted, and obtaining the offset calibration value to be adjusted at the moment as a target offset calibration value.

In a possible embodiment, the inputting the median voltage into the single-slope ADC to be corrected, performing offset calibration on the single-slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single-slope ADC to be corrected so that the number output by the single-slope ADC to be corrected is the median number, and the gain calibration value at this time is obtained as a target gain calibration value includes:

setting the current digit to be adjusted of the gain calibration value to be adjusted to be 1, wherein each digit of the initial gain calibration value to be adjusted is 0, and the initial digit to be adjusted is the highest digit of the gain calibration value to be adjusted;

inputting the median voltage into the single slope ADC to be corrected, performing offset calibration on the single slope ADC to be corrected based on the target offset calibration value, and performing gain calibration on the single slope ADC to be corrected based on the current gain calibration value to be adjusted to obtain a numerical value output by the single slope ADC to be corrected;

if the currently output numerical value is not less than the median number, keeping the current digit to be adjusted in the gain calibration value to be adjusted to be 1;

if the currently output numerical value is smaller than the median number, setting the current digit to be adjusted in the gain calibration value to be adjusted to be 0;

selecting the next digit in the gain calibration value to be adjusted as the digit to be adjusted, and returning to the execution step: and setting the current digit to be adjusted of the gain calibration value to be adjusted to be 1 until the current digit to be adjusted is the last digit of the gain calibration value to be adjusted, and obtaining the gain calibration value to be adjusted at the moment as a target gain calibration value.

The embodiment of the present application further provides a calibration system for a single slope analog-to-digital converter, where the system includes:

the device comprises a voltage generator, a single slope ADC, a numerical comparator 1, a register, a time sequence and a digital control logic circuit;

the time sequence and digital control logic circuit is used for controlling the time sequence of each part;

the register is used for storing the offset calibration value to be adjusted and the gain calibration value to be adjusted;

the voltage generator is used for generating a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC and inputting the lower limit voltage into the single-ramp ADC;

the single-slope ADC is used for performing offset calibration based on the offset calibration value to be adjusted in the register under the condition that the lower limit voltage is input, and outputting a digital signal under the current offset calibration value to be adjusted;

the numerical value comparator 1 is configured to compare the digital signal under the current offset calibration value to be adjusted with the lower limit number of the preset digital output range of the single-slope ADC, and adjust the offset calibration value to be adjusted in the register according to the comparison result, so that the digital signal under the current offset calibration value to be adjusted output by the single-slope ADC is the lower limit number, and the offset calibration value to be adjusted at this time is obtained as the target offset calibration value;

the voltage generator is further configured to generate a median voltage of a preset voltage analog conversion range of the single-ramp ADC, and input the median voltage into the single-ramp ADC;

the single-slope ADC is further used for performing offset calibration based on the target offset calibration value under the condition that the median voltage is input, performing gain calibration based on the gain calibration value to be adjusted in the register, and outputting a digital signal under the current gain calibration value to be adjusted;

the numerical value comparator 1 is further configured to compare the digital signal under the current gain calibration value to be adjusted with the median number of the preset digital output range of the single-slope ADC, and adjust the gain calibration value to be adjusted in the register according to the comparison result, so that the digital signal under the current gain calibration value to be adjusted output by the single-slope ADC is the median number, and the gain calibration value to be adjusted at this time is obtained as the target gain calibration value.

In one possible embodiment, the voltage generator is a digital-to-analog converter DAC;

the DAC is specifically configured to generate a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC when a preset first digital is input, and input the lower limit voltage into the single-ramp ADC; and when a preset second digit is input, generating a median voltage of a preset voltage analog conversion range of the single-ramp ADC, and inputting the median voltage into the single-ramp ADC.

In one possible implementation, the registers include a successive approximation register 1 and a successive approximation register 2;

the successive approximation register 1 is used for storing the offset calibration value to be adjusted and setting the current digit to be adjusted of the offset calibration value to be adjusted to 1, wherein each digit of the initial offset calibration value to be adjusted is 0, and the initial digit to be adjusted is the highest digit of the offset calibration value to be adjusted;

the numerical comparator 1 is specifically configured to compare the digital signal under the current offset calibration value to be adjusted with a lower limit number of a preset digital output range of the single-slope ADC, and send first information to the successive approximation register 1 when the digital signal under the current offset calibration value to be adjusted is not less than the lower limit number; under the condition that the digital signal under the current offset calibration value to be adjusted is smaller than the lower limit number, second information is sent to the successive approximation register 1;

the successive approximation register 1 is further configured to keep a digit to be adjusted in the offset calibration value to be adjusted as 1 when the first information is received; when second information is received, setting the digit to be adjusted in the offset calibration value to be adjusted to be 0; selecting the next digit in the offset calibration value to be adjusted as the digit to be adjusted, setting the digit to be adjusted of the offset calibration value to be adjusted as 1, and outputting the digit to be adjusted to a successive approximation register 1 until the digit to be adjusted is the last digit of the offset calibration value to be adjusted, and obtaining the offset calibration value to be adjusted at the moment as the target offset calibration value;

the successive approximation register 2 is used for storing a bias gain standard value to be adjusted and setting the current digit to be adjusted of the gain calibration value to be adjusted to be 1, wherein each digit of the initial gain calibration value to be adjusted is 0, and the initial digit to be adjusted is the highest digit of the gain calibration value to be adjusted;

the numerical comparator 1 is specifically configured to compare the digital signal under the current gain calibration value to be adjusted with the median number of the preset digital output range of the single-slope ADC, and send third information to the successive approximation register 2 when the digital signal under the current gain calibration value to be adjusted is not less than the median number; under the condition that the digital signal under the current gain calibration value to be adjusted is smaller than the median number, fourth information is sent to the successive approximation register 2;

the successive approximation register 2 is further configured to keep the number of bits to be adjusted in the gain calibration value to be adjusted as 1 when the third information is received; when the fourth information is received, setting the digit to be adjusted in the gain calibration value to be adjusted to be 0; selecting the next digit in the gain calibration value to be adjusted as the digit to be adjusted, setting the digit to be adjusted of the gain calibration value to be adjusted as 1, and outputting the digit to be adjusted to the successive approximation register 1 until the digit to be adjusted is the last digit of the gain calibration value to be adjusted, and obtaining the gain calibration value to be adjusted at the moment as the target gain calibration value.

In a possible embodiment, the system further comprises a numerical comparator 2 and a counter 2;

the counter 2 is used for starting to count when the single-slope ADC receives input voltage;

the numerical comparator 2 is configured to trigger the single-ramp ADC to convert the input voltage signal into a digital signal when the count of the counter 2 is the offset calibration value to be adjusted.

In one possible embodiment, the single ramp ADC includes a counter 1;

the value comparator 2 is specifically configured to trigger the counter 1 to reset and count when the count of the counter 2 is the target offset calibration value, where the single-slope ADC outputs a digital signal corresponding to the voltage signal when the count of the counter 1 is a preset count value.

In one possible embodiment, the register further comprises a parameter register; the parameter register is configured to store initial configuration parameters of each portion, where the initial configuration parameters include a lower limit number and a median number of a preset digital output range of the single-ramp ADC, a first parameter, and a second parameter, the first parameter is a preset first number or a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC, and the second parameter is a preset second number or a median voltage of the preset voltage analog conversion range of the single-ramp ADC.

In a possible implementation, the parameter register is further configured to store the target offset calibration value and the target gain calibration value.

The embodiment of the application has the following beneficial effects:

the calibration method and the calibration system for the single-slope analog-to-digital converter, provided by the embodiment of the application, are used for acquiring the lower limit number and the median number of the preset digital output range of the single-slope ADC to be corrected, and acquiring the lower limit voltage and the median voltage of the preset voltage analog conversion range of the single-slope ADC to be corrected, wherein the lower limit number is not zero; inputting the lower limit voltage into the single slope ADC to be corrected, and adjusting the offset calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be corrected to be a lower limit number, and obtain the offset calibration value at the moment as a target offset calibration value; and inputting the median voltage into the single slope ADC to be corrected, carrying out offset calibration on the single slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be corrected to be the median number and obtain the gain calibration value at the moment as the target gain calibration value. The calibration of the single-slope ADC is realized, an on-chip calibration scheme of the single-slope ADC is provided, the structure is simple, the cost is low, the operation is convenient, and the calibration of the offset and the gain of the single-slope ADC within a specified number of times is realized through the successive approximation register 1 and the successive approximation register 2; the automatic level of this application embodiment is higher, need not to carry out calibration operation to single slope ADC before dispatching from the factory, only needs just can realize single slope ADC's real-time calibration through configuration parameter register, has improved the efficiency of calibration greatly. Of course, not all advantages described above need to be achieved at the same time in the practice of any one product or method of the present application.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of the operation of a single-ramp ADC in the related art;

FIG. 2 is a diagram illustrating a single ramp ADC calibration method according to the related art;

FIG. 3 is a first schematic diagram of a calibration system for a single-slope analog-to-digital converter according to an embodiment of the present application;

FIG. 4 is a diagram illustrating the analog-to-digital conversion characteristics of a single-ramp ADC according to an embodiment of the present application;

FIG. 5 is a second schematic diagram of a calibration system for a single-slope analog-to-digital converter according to an embodiment of the present application;

FIG. 6 is a third schematic diagram of a calibration system for a single-slope analog-to-digital converter according to an embodiment of the present application;

FIG. 7a is a schematic diagram of a first portion of a single-slope analog-to-digital converter calibration system according to an embodiment of the present application;

FIG. 7b is a diagram of a second portion of a single-slope analog-to-digital converter calibration system according to an embodiment of the present application;

FIG. 8 is a timing diagram of a single slope ADC calibration according to an embodiment of the present application;

fig. 9 is a schematic diagram of a calibration method of a single-slope analog-to-digital converter according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

In the related art, there are three calibration modes of the ADC, which are manual debugging, software debugging and hardware debugging, respectively. The manual debugging has the problems of low precision, high cost, low production efficiency and the like, and the development of the manual debugging in the industry is seriously limited. Software debugging depends on an automatic test platform, the debugging precision is improved to a certain extent, and the test time is shortened, but the process cannot ensure that all ADC systems are completely consistent, and the ADC chips can only be calibrated one by a manufacturer before leaving factories. And the hardware debugging can realize the automation of the test and the parallel test, thereby greatly improving the production efficiency.

As shown in fig. 2, the hardware debugging method of the ADC may compare the digital signal value converted by the ADC with a target value, and adjust the gain coefficient of the ADC according to the comparison result, so as to achieve the purpose of calibrating the ADC. Although the method has a simple structure and is easy to realize, only gain calibration is performed during ADC calibration, offset calibration is ignored, and the accuracy of a calibration result is poor; secondly, the number of iterations of the gain adjustment is not fixed, and if the preset gain coefficient value deviates from the final target value more, the required calibration time will be increased greatly.

In view of this, the present application provides a calibration system for a single-slope analog-to-digital converter, referring to fig. 3, the system includes:

the voltage generator is configured to generate a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC, and input the lower limit voltage to the single-ramp ADC;

the single-slope ADC is configured to perform offset calibration based on the offset calibration value to be adjusted in the register when the lower limit voltage is input, and output a digital signal under the offset calibration value to be currently adjusted;

the numerical comparator 1 is configured to compare the digital signal under the current offset calibration value to be adjusted with the lower limit number of the preset digital output range of the single-slope ADC, and adjust the offset calibration value to be adjusted in the register according to the comparison result, so that the digital signal under the current offset calibration value to be adjusted output by the single-slope ADC is the lower limit number, and the offset calibration value to be adjusted at this time is obtained as a target offset calibration value;

the single-slope ADC is further configured to, when the median voltage is input, perform offset calibration based on the target offset calibration value, perform gain calibration based on the gain calibration value to be adjusted in the register, and output a digital signal under the current gain calibration value to be adjusted;

the numerical comparator 1 is further configured to compare the digital signal under the current gain calibration value to be adjusted with the median number of the preset digital output range of the single-slope ADC, and adjust the gain calibration value to be adjusted in the register according to the comparison result, so that the digital signal under the current gain calibration value to be adjusted output by the single-slope ADC is the median number, and the gain calibration value to be adjusted at this time is obtained as the target gain calibration value.

The time sequence and digital control logic circuit is a control circuit for coordinating the time sequence of each part and the on-off of the channel signal in the single slope analog-to-digital converter calibration system, and is used for controlling the execution time sequence of each part and the power-on and power-off of each part.

The preset voltage analog conversion range of the single slope ADC is a range of an input voltage which can be converted into a digital signal when the single slope ADC is designed, and the preset digital output range of the single slope ADC is a range of a digital signal which can be converted when the single slope ADC is designed, for example, when the single slope ADC is designed, V is designed_min-V_maxIs transported byConverting voltage into digital D_min-D_maxIf the preset voltage analog conversion range is V_min-V_maxThe preset digital output range is D_min-D_maxLower limit voltage of V_minMedian voltage of V_mid＝(V_min+V_max) A lower limit number of D_minMedian number being D_mid＝(D_min+D_max)/2。

The analog-to-digital conversion characteristics of the single ramp ADC are shown in fig. 4. The input/output characteristic curve of the single-ramp ADC is represented by Dout ═ Gain · Vin + Offset (the nonlinear error of the ADC is not considered here), Vin is the analog input voltage of the single-ramp ADC, and the range is V_min-V_maxI.e. the output voltage range of the ramp generator; dout is the digital output of a single ramp ADC with a range of D_min-D_maxIn one example, the number string can be 00 … 01-11 … 11, wherein the length of the number string can be set in a self-defined manner according to the actual situation; gain is the Gain of the single slope ADC and is regulated and controlled by a Gain calibration value; offset is the Offset of the single slope ADC, regulated by an Offset calibration value.

And calibrating the single-slope ADC, namely calibrating the gain calibration value and the offset calibration value of the ADC by the single slope, so that the ADC has the conversion characteristic. V_minThe lower limit of the ramp generator output voltage is independent of the gain, so the initial point (V) can be chosen_min,D_min) Calibration of single ramp ADC offsets is performed for reference. The gain calibration value of the single-slope ADC can be set to any value, and the analog voltage V is input_minAdjusting the offset calibration value to make the output of the single-slope ADC be D_minAnd obtaining the offset calibration value at the moment as a target offset calibration value. After the target offset calibration value is determined, the midpoint (V) is used_mid,D_mid) Calibration of the single ramp ADC gain is performed for reference. Input analog voltage V_midAdjusting the gain calibration value to make the output of the single-slope ADC be D_midAnd obtaining the gain calibration value at the moment as a target gain calibration value. Thus, the calibration of the single-slope ADC is completed, and the parameters used for the calibration are the target gain calibration value and the target offset calibration value. In one example, the digital output range is 00 … 01-11 … 11And the reason is that the accurate gain calibration value and offset calibration value can be obtained only by the jump of the output value of the single-slope ADC in the positive and negative directions of the target value during data comparison instead of 00 … 00-11 … 11.

In the embodiment of the application, the calibration of the single-slope ADC is realized, besides the gain calibration, the target offset calibration value is also determined, the offset calibration is realized, and the accuracy of the single-slope ADC for outputting the digital signal can be further improved.

In a possible embodiment, the voltage generator is a DAC (Digital to analog converter); the DAC is specifically configured to generate a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC when a preset first digital is input, and input the lower limit voltage to the single-ramp ADC; and when a preset second digit is input, generating a median voltage of a preset voltage analog conversion range of the single-ramp ADC, and inputting the median voltage into the single-ramp ADC.

First number D_{offset_ref}To make DAC output lower limit voltage V_minThe digital input of (2); second number D_{gain_ref}To make DAC output a median voltage V_midThe first digit and the second digit are determined according to the actual digital-to-analog conversion parameters of the DAC, so that the lower limit voltage and the median voltage can be accurately input. In the embodiment of the application, the DAC can be used for accurately generating the lower limit voltage and the median voltage.

In one possible implementation, referring to fig. 5, the registers include a successive approximation register 1 and a successive approximation register 2;

the successive approximation register 1 is configured to store an offset calibration value to be adjusted, and set a current digit to be adjusted of the offset calibration value to be adjusted to 1, where each digit of the initial offset calibration value to be adjusted is 0, and the initial digit to be adjusted is a highest digit of the offset calibration value to be adjusted;

the numerical comparator 1 is specifically configured to compare the digital signal under the current offset calibration value to be adjusted with the lower limit number of the preset digital output range of the single-slope ADC, and send first information to the successive approximation register 1 when the digital signal under the current offset calibration value to be adjusted is not less than the lower limit number; under the condition that the digital signal under the current offset calibration value to be adjusted is smaller than the lower limit number, second information is sent to the successive approximation register 1;

the successive approximation register 1 is further configured to keep the number of bits to be adjusted in the offset calibration value to be adjusted as 1 when the first information is received; when second information is received, setting the digit to be adjusted in the offset calibration value to be adjusted to be 0; selecting the next digit in the offset calibration value to be adjusted as the digit to be adjusted, setting the digit to be adjusted of the offset calibration value to be adjusted as 1, and outputting the digit to be adjusted to a successive approximation register 1 until the digit to be adjusted is the last digit of the offset calibration value to be adjusted, and obtaining the offset calibration value to be adjusted at the moment as the target offset calibration value;

the successive approximation register 2 is configured to store a bias gain standard value to be adjusted, and set a current digit to be adjusted of a gain calibration value to be adjusted to 1, where each digit of an initial gain calibration value to be adjusted is 0, and the initial digit to be adjusted is a highest digit of the gain calibration value to be adjusted;

Firstly, performing offset calibration, inputting a lower limit voltage into a single-slope ADC, and performing gain correction on the lower limit voltage by using any gain calibration value; setting the highest digit of the offset calibration value to be adjusted to 1 by a successive approximation register 1, generating an offset calibration value to be adjusted of 100 … 00, carrying out offset correction on the lower limit voltage by using the current offset calibration value to be adjusted, and obtaining a digital signal Dout output by the single-slope ADC<Q:0>(ii) a Will digital signal Dout<Q:0>With a lower limit number D_minMaking a comparison if Dout<Q:0>≥D_minThen the offset calibration value REG1[ M:0] is to be adjusted]Is correct for the highest digit of 1, and then REG1[ M:0]The next highest position 1, the current offset calibration value to be adjusted, i.e. 110 … 00; if Dout<Q:0><D_minThen REG1[ M:0]The most significant bit is a1 error, the most significant bit is set to zero, and REG1[ M:0] is then added]The next highest position 1, the current offset calibration value to be adjusted, i.e. 010 … 00, is generated. The comparison is sequentially cycled until REG1[ M:0]]All the digits of the calibration result are determined, the ADC offset calibration of the single slope is finished, and the last offset calibration value to be adjusted is used as a target offset calibration value.

After the offset calibration is finished, gain calibration is carried out, the median voltage is input into a single slope ADC, and offset correction is carried out on the median voltage by using a target offset calibration value; setting the highest digit of the gain calibration value to be adjusted to 1 by the successive approximation register 2 to generate a gain calibration value to be adjusted of 100 … 00, and carrying out gain correction on the median voltage by using the current gain calibration value to be adjusted to obtain a digital signal Dout output by the single-slope ADC<Q:0>The digital data Dout<Q:0>And median number D_midMaking a comparison if Dout<Q:0>≥D_midThen the gain calibration value REG2[ N:0] to be adjusted]The highest digit is 1 correct, and then REG2[ N:0]]The next highest position 1, the current gain calibration value to be adjusted, i.e. 110 … 00; if Dout<Q:0><D_midThen REG2[ N: 0)]The most significant bit is a1 error, the most significant bit is set to zero, and REG2[ M:0] is then added]To the next highest position 1, to generate the current gain calibration to be adjustedThe value 010 … 00. So as to cycle sequentially until REG2[ N:0]]All the bits of (1) are determined, which represents that the monoclinic ADC gain calibration is finished, and the last gain calibration value to be adjusted is used as a target gain calibration value.

In a possible embodiment, referring to fig. 6, the system further comprises a numerical comparator 2 and a counter 2;

the counter 2 is configured to start counting when the single-slope ADC receives an input voltage;

the numerical comparator 2 is configured to trigger the single-slope ADC to convert the input voltage signal into a digital signal when the count of the counter 2 is the offset calibration value to be adjusted.

The successive approximation register 2 sends the current offset calibration value to be adjusted to the numerical comparator 2, the numerical comparator 2 compares the count of the counter 2 with the offset calibration value to be adjusted, and when the count of the counter 2 is the current offset calibration value to be adjusted, the numerical comparator 2 triggers the single-slope ADC to convert the input voltage signal into a digital signal, so that the offset calibration is realized.

In one possible embodiment, the single-ramp ADC includes a counter 1;

the numerical comparator 2 is specifically configured to trigger the counter 1 to reset and count when the count of the counter 2 is the target offset calibration value, wherein when the count of the counter 1 is a preset count numerical value, the single slope ADC outputs a digital signal corresponding to the voltage signal at that time.

The single-slope ADC comprises a counter 1, and when the count of the counter 2 is the current offset calibration value to be adjusted, the numerical comparator 2 triggers the counter 1 inside the single-slope ADC to reset and count clock pulses. When the count of the counter 1 is a preset count value, the single-slope ADC outputs a digital signal corresponding to the input voltage at that time. In one example, the preset count value is the initial value of the counter 1, that is, the single slope ADC outputs the digital signal corresponding to the input voltage at the moment when the counter 1 starts counting.

In a possible implementation, the register further includes a parameter register; the parameter register is configured to store initial configuration parameters of each part, where the initial configuration parameters include a lower limit number and a middle value number of a preset digital output range of the single-ramp ADC, a first parameter, and a second parameter, the first parameter is a preset first number or a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC, and the second parameter is a preset second number or a middle value voltage of the preset voltage analog conversion range of the single-ramp ADC. The parameter register stores initial configuration parameters to facilitate acquisition of the initial configuration parameters.

In a possible implementation manner, the parameter register is further configured to store the target offset calibration value and the target gain calibration value. The parameter register stores the target offset calibration value and the target gain calibration value so as to facilitate the acquisition of the subsequent target offset calibration value and the target gain calibration value after the single-slope ADC calibration is completed.

As shown in fig. 7a and 7b, the calibration system for a single-slope analog-to-digital converter according to the embodiment of the present application may further include: parameter register, DAC, single slope ADC, numerical value comparator 1, numerical value comparator 2, successive approximation register 1, successive approximation register 2, counter 2, time sequence and digital control logic circuit. Among them, a1 in fig. 7a is connected with a1 in fig. 7B, B1 in fig. 7a is connected with B1 in fig. 7B, and C1 in fig. 7a is connected with C1 in fig. 7B.

The parameter register is used to store initial configuration parameters of each part, and in one example, the initial configuration parameters may be input into the parameter register in series by SCK (CMOS clock) in cooperation with SDA (SerialData, a data signal line of I2C bus). The DAC is used to convert the digital signal into a voltage signal. The single-slope ADC is a target to be calibrated, the gain and the offset of the single-slope ADC are determined by a gain calibration value and an offset calibration value, the gain calibration value is input from a port Idac < N:0>, the larger the gain calibration value is, the larger the slope of a slope signal output by the slope generator is, namely the larger the gain of the single-slope ADC is; the offset calibration value is used to generate a reset signal of the counter 1 in the single-slope ADC, which is input from the port Rst _ counter, and the larger the offset calibration value is, the later the count start time of the counter 1 is, i.e., the larger the offset of the ADC is. The value comparator 1 and the value comparator 2 are mainly used for comparing the values of two input digital signals so as to determine the subsequent operation. The numerical comparator 1 is configured to compare the digital signal after the single-slope ADC conversion with the offset target value and the gain target value, so as to determine a configuration word of the offset calibration value and the gain calibration value; the numerical comparator 2 is used to compare the offset calibration value with the magnitude of the output signal of the counter 2, thereby generating a reset signal of the counter 1. Successive approximation register 1 and successive approximation register 2 are modules for generating a single-slope ADC gain calibration value and an offset calibration value based on the dichotomy principle. The timing and digital control logic circuit is a control circuit for coordinating the timing of each module and the on/off of the path signal in the scheme, and in one example, the timing diagram of the circuit in the calibration of the single slope analog-to-digital converter can be as shown in fig. 8.

The following is a detailed description of single ramp analog-to-digital converter calibration:

after the single slope analog-to-digital converter calibration system is powered on, whether the parameter register has the full amount of initial configuration parameters is judged, if yes, the parameters are directly acquired, and if not, the parameter register needs to be configured. In one example, there are five types of parameters to be configured, namely, an offset reference value Doffset _ ref (corresponding to a first number), a gain reference value Dgain _ ref (corresponding to a second number), an offset target value Doffset (corresponding to a lower limit number), a gain target value Dgain (corresponding to a middle number), and an initial gain calibration value of the ADC. The offset reference value Doffset _ ref is a digital input that makes the DAC output an offset reference voltage Voffset _ ref (equivalent to a lower limit voltage); the gain reference value Dgain _ ref is a digital input that causes the DAC output to be a gain reference voltage Vgain _ ref (equivalent to the median voltage). In one example, the offset target value Doffset is the lower limit 00..01 of the ADC digital output range; the gain target value Dgain is the median 10 … 00 of the ADC digital output range. When performing offset calibration, an initial value, that is, an initial gain calibration value, needs to be preset for the gain calibration value of the ADC, where the initial gain calibration value may be any value, and in one example, for uniformity, the initial gain calibration value may be 10 … 00.

And entering a single-slope ADC calibration mode, and clearing the successive approximation register 1 and the successive approximation register 2.

Offset calibration is performed first: s _ offset, S2, S3, S5, S7, S9 off, S _ gain, S1, S4, S6, S8 on. The DAC inputs an offset reference value Doffset _ ref and outputs an offset reference voltage Voffset _ ref, which is the lower limit of the analog conversion range; then, the single slope ADC converts the offset reference voltage Voffset _ ref. The ramp generator outputs a ramp signal determined by the initial gain calibration value at a certain time after the S _ offset is turned off, the ramp signal is compared with the input offset reference voltage Voffset _ ref, a pulse signal proportional to the offset reference voltage Voffset _ ref is generated, and the pulse is measured by the clock pulse; meanwhile, the highest position 1 of REG1[ M:0] of the register 1 is gradually approached, a first offset calibration value 100 … 00 is generated and output to the numerical comparator 2 through a port D1< M:0>, when the counter 2 counts to the offset calibration value, the counter 1 inside the ADC is reset and counts clock pulses, and digital data Dout < Q:0> after the offset reference voltage Voffset _ ref is converted is output; then, the digital data Dout < Q:0> enters the numerical comparator 1, is compared with the offset target value Doffset, if Dout < Q:0> is ≧ Doffset, REG1[ M:0] is correct at the highest position 1, then the second offset calibration value, i.e. 110 … 00, of REG1[ M:0] is generated at the next highest position 1, REG1[ M:0] is incorrect at the highest position 1, REG 350 ] is zero, then REG1[ M:0] is generated at the next highest position 1, a second offset calibration value, i.e. 010 … 00, and this is cyclically compared in sequence until all bits of REG1[ M:0] are determined, Eoc _ en1 outputs a negative pulse, representing that ADC offset calibration is finished, and the last offset calibration value is stored as the finally determined offset calibration value in the successive approximation register 1 at 1[ M:0 ].

And after the offset calibration is finished, gain calibration is carried out: s _ gain, S2, S3, S6, S7, S8 off, S _ offset, S1, S4, S5, S9 on. The DAC inputs a gain reference value Dgain _ ref and outputs a gain reference voltage Vgain _ ref, namely the median of the analog conversion range; then, the single slope ADC converts the gain reference voltage Voffset _ ref. After S _ gain is closed, gradually approaching the highest position 1 of REG2[ N:0] of a register 2, generating first gain calibration data 100 … 00, and outputting the first gain calibration data to a ramp generator in the ADC through an interface D2< N:0 >; then, the ramp generator outputs a ramp signal determined by the gain calibration value, and compares the ramp signal with the input gain reference voltage Vgain _ ref to generate a pulse signal proportional to the gain reference voltage Vgain _ ref, and the pulse is measured by a clock pulse; meanwhile, the counter 1 counts the clock pulse under the control of the offset calibration value determined in the previous step, and outputs the digital data Dout < Q:0> after the conversion of the gain reference voltage Vgain _ ref; the digital data Dout < Q:0> and the gain target value Dgain enter into a numerical comparator 1 for comparison, if Dout < Q:0> is ≧ Dgain, REG2[ N:0] is correct at the highest position 1, then the second gain calibration value is generated by the next highest position 1 of REG2[ N:0], namely 110 … 00, if Dout < Q:0> < Dgain, REG2[ N:0] is incorrect at the highest position 1, the position is zero, then the next highest position 1 of REG2[ M:0] is generated by the next highest position 1, namely 010 … 00, and the above steps are successively circulated until all the bits of REG2[ N:0] are determined, Eoc _ en2 outputs a negative pulse representing the end of ADC gain calibration, and the last gain REG is stored as the finally determined gain calibration value to successively approach 2[ N:0] of a register 2.

The single-ramp ADC calibration is finished, the switches S _ offset, S _ gain, S2, S3, S5, S6, S9 are opened, S1, S4, S7, S8 are closed, and the ADC conversion mode is entered. At this time, the single-slope ADC performs analog-to-digital conversion on the input analog signal Vin under the control of the offset calibration value and the gain calibration value determined in the last two steps, and outputs the converted digital signal through the Dout < Q:0> port.

In the embodiment of the application, a calibration system for a single-slope ADC is provided, the calibration of the single-slope ADC is realized, an on-chip calibration scheme for the single-slope ADC is provided, the structure is simple, the cost is low, the operation is convenient, and the calibration of the offset and the gain of the single-slope ADC within a specified number of times is realized through a successive approximation register 1 and a successive approximation register 2; the automatic level of this application embodiment is higher, need not to carry out calibration operation to single slope ADC before dispatching from the factory, only needs just can realize single slope ADC's real-time calibration through configuration parameter register, has improved the efficiency of calibration greatly.

The embodiment of the present application further provides a calibration method for a single slope analog-to-digital converter, referring to fig. 9, the method includes:

s101, acquiring a lower limit number and a median number of a preset digital output range of a to-be-corrected single slope analog-to-digital converter (ADC), and acquiring a lower limit voltage and a median voltage of a preset voltage analog conversion range of the to-be-corrected single slope ADC, wherein the lower limit number is not zero;

s102, inputting the lower limit voltage into the single slope ADC to be corrected, and adjusting the offset calibration value of the single slope ADC to be corrected so as to enable the number output by the single slope ADC to be the lower limit number and obtain the offset calibration value at the moment as a target offset calibration value;

and S103, inputting the median voltage into the single slope ADC to be corrected, carrying out offset calibration on the single slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single slope ADC to be corrected so that the number output by the single slope ADC to be corrected is the median number, thereby obtaining the gain calibration value at the moment as the target gain calibration value.

In one possible embodiment, the inputting the lower limit voltage into the single-slope ADC to be corrected and adjusting the offset calibration value of the single-slope ADC to be corrected such that the number output by the single-slope ADC to be corrected becomes the lower limit number, and the offset calibration value at this time is obtained as the target offset calibration value includes:

inputting the lower limit voltage into the single slope ADC to be corrected, performing gain calibration on the single slope ADC to be corrected based on a preset gain calibration value, and performing offset calibration on the single slope ADC to be corrected based on a current offset calibration value to be adjusted to obtain a numerical value output by the single slope ADC to be corrected;

In one possible embodiment, the inputting the median voltage into the single-slope ADC to be corrected, performing offset calibration on the single-slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single-slope ADC to be corrected such that the number output by the single-slope ADC to be corrected is the median number, and the gain calibration value at this time is obtained as the target gain calibration value includes:

An embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored in the computer-readable storage medium, and when the computer program is executed by a processor, the computer program implements any one of the above calibration methods for a single-slope analog-to-digital converter.

In yet another embodiment provided by the present application, there is also provided a computer program product containing instructions that, when run on a computer, cause the computer to perform any of the single ramp analog-to-digital converter calibration methods of the above embodiments.

In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the application to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optic, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.

It should be noted that, in this document, the technical features in the various alternatives can be combined to form the scheme as long as the technical features are not contradictory, and the scheme is within the scope of the disclosure of the present application. Relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for embodiments of the method, the computer program product and the storage medium, since they are substantially similar to the system embodiments, the description is relatively simple, and in relation to the description, reference may be made to some of the description of the system embodiments.

The above description is only for the preferred embodiment of the present application and is not intended to limit the scope of the present application. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A method of single-slope analog-to-digital converter calibration, the method comprising:

2. The method according to claim 1, wherein the inputting the lower limit voltage into the single-slope ADC to be corrected, and adjusting the offset calibration value of the single-slope ADC to be corrected so that the number output by the single-slope ADC to be corrected is the lower limit number, and obtaining the offset calibration value at this time as the target offset calibration value comprises:

3. The method according to claim 1, wherein the inputting the median voltage into the single-slope ADC to be corrected, performing offset calibration on the single-slope ADC to be corrected based on the target offset calibration value, and adjusting the gain calibration value of the single-slope ADC to be corrected so that the number output by the single-slope ADC to be corrected is the median number, and the gain calibration value at this time is a target gain calibration value, comprises:

4. A single-slope analog-to-digital converter calibration system, the system comprising:

5. The system of claim 4, wherein the voltage generator is a digital-to-analog converter (DAC);

6. The system according to claim 4 or 5, wherein the registers comprise a successive approximation register 1 and a successive approximation register 2;

7. The system of claim 6, further comprising a numerical comparator 2 and a counter 2;

8. The system of claim 7, wherein the single ramp ADC comprises a counter 1;

9. The system of claim 6, wherein the registers further comprise a parameter register; the parameter register is configured to store initial configuration parameters of each portion, where the initial configuration parameters include a lower limit number and a median number of a preset digital output range of the single-ramp ADC, a first parameter, and a second parameter, the first parameter is a preset first number or a lower limit voltage of a preset voltage analog conversion range of the single-ramp ADC, and the second parameter is a preset second number or a median voltage of the preset voltage analog conversion range of the single-ramp ADC.

10. The system of claim 9, wherein the parameter register is further configured to store the target offset calibration value and the target gain calibration value.