CN101777913A - Method for calibration of the gain error and input offset in ADC - Google Patents

Abstract

The invention provides a method for calibration of the gain error and input offset in ADC. The steps are: increasing reference voltage VDAC to calibrate the gain error, and measure the input offset Doffset using the calibrated reference voltage VREF+VDAC, then calibrate the input offset on this base. The invention reduces the gain error and the input offset to a very small number through the calibration of the ADC and thus meeting the application needs for highly precise purposes.

Description

The method of the gain error of calibrating analog-to-digital converter and input imbalance

Technical field

The present invention relates to the gain error of a kind of calibrating analog-to-digital converter in the circuit design field and the method for input imbalance.

Background technology

Ideally, the analog to digital converter ADC of M position (M-bit) should be zero the input corresponding to zero output, and the transducer of (can regard the gain=1 that gains as) is exported in full width of cloth input corresponding to the full width of cloth.But can there be input imbalance and gain error in the side circuit.The input imbalance that is to say that the zero input of ADC can't be V in input only corresponding to zero output _OffsetSituation under just have zero output, this just has been equivalent to import a fixing imbalance V _OffsetAnd gain error be meant the input of the full width of cloth corresponding be not full width of cloth output, full width of cloth input may cause output to be overflowed or can't reach maximum output, seem just as there being gain error (gain error), make analog signal be exaggerated gain+gain error (G+GE) and doubly just be quantized later, as shown in Figure 1.Generally speaking, not high to input imbalance and the gain error requirement of ADC, but in the high-precision applications occasion, need the imbalance of ADC and gain error very little.For example, LTC2204[1] imbalance have only ± 1mV, externally import precise reference voltage source V _REFThe time, gain error is 0.2%.The high-precision applications occasion needs the gain error of ADC and imports imbalance very little, because the input imbalance of unregulated ADC and gain error are limited by the technology mismatch parameter mainly and can't reduce, at this moment just need carry out extra calibration.

Summary of the invention

The method of the gain error of a kind of calibrating analog-to-digital converter provided by the invention and input imbalance makes that circuit still can meet design requirement under the prerequisite of technology mismatch.

In order to achieve the above object, the invention provides a kind of gain error of calibrating analog-to-digital converter and the method for input imbalance, comprise following steps:

The gain error GE of step 1, estimation maximum possible _MaxGain error GE with the minimum permission _Allowed

Calibration times N={ log that step 2, calculating need ₂(GE _Max/ GE _Allowed), wherein, { m} represents to be not less than the smallest positive integral of m;

Step 3, set up reference voltage V _DAC, this reference voltage V _DACBe the N position, full amplitude output is ± V _REF* GE _Max, minimum resolution (1LSB) is V _REF* GE _Max/ 2 ^N-1

Step 4, make reference voltage output bit _DAC=2 ^N-1, time=1;

Step 5, make input value V _In=+V _Full/ 2, (V _FullBe maximum input amplitude), obtain outputting measurement value D _Out=D1 is if noise ratio more greatly can be average in the hope of what repeatedly export;

Step 6, make input value V _In=-V _Full/ 2, obtain outputting measurement value D _Out=D2 is if noise ratio more greatly can be average in the hope of what repeatedly export;

Step 7, make step-length bit _Step=2 ^N-1-time

Step 8, judgement D1-D2 〉=2 ^M-1Whether (M is the figure place of analog to digital converter) sets up, if then make bit _DAC=bit _DAC+ bit _Step, if not, then make bit _DAC=bit _DAC-bit _StepThis also becomes the reference voltage of analog to digital converter into V _REF+ V _DAC=V _REF* (1+GE _Max/ 2), perhaps V _REF+ V _DAC=V _REF* (1-GE _Max/ 2);

Step 9, judge whether time 〉=N-1 sets up, if, carry out step 11, if not, carry out step 10;

Step 10, make time=time+1, carry out step 5;

Step 11, make input value V _In=+V _Full/ 2, obtain outputting measurement value D _Out=D1;

Step 12, make input value V _In=-V _Full/ 2, obtain outputting measurement value D _Out=D2;

Step 13, judgement D1-D2 〉=2 ^M-1Whether set up, if, finish the gain error calibration, carry out step 14, if not, then make bit _DAC=bit _DAC-1, finish the gain error calibration, carry out step 14;

V after step 14, the calibration of use gain error _REF+ V _DACAs reference voltage, make the input value V of analog to digital converter _In=0, obtain outputting measurement value D _Out=D;

Step 15, make D _Offset=D-2 ^M-1

Because output is natural binary code, so the corresponding code value of zero input of analog to digital converter is 2 ^M-1, with D-2 ^M-1As input imbalance D _OffsetValue;

Step 16, make D _Out=D _Out-D _Offset

From the output valve of analog to digital converter, cut D _Offset, be the output valve after the calibration input is lacked of proper care.

The present invention can make the gain error of analog to digital converter and import imbalance very little by calibration, satisfies the application need of high accuracy occasion.

Description of drawings

Fig. 1 is the schematic diagram of analog to digital converter in the background technology;

Fig. 2 is the flow chart of the gain error and the method that input is lacked of proper care of a kind of calibrating analog-to-digital converter provided by the invention;

Fig. 3 is the value of the preceding gain error of calibration in the embodiment of the invention;

Fig. 4 is the value of calibration back gain error in the embodiment of the invention;

Fig. 5 is the value that input is lacked of proper care before the calibration in the embodiment of the invention;

Fig. 6 is the value of calibration back input imbalance in the embodiment of the invention.

Embodiment

Following according to Fig. 2～Fig. 6, specify preferred embodiment of the present invention:

As shown in Figure 2, be a kind of gain error of calibrating analog-to-digital converter and the method for input imbalance, comprise following steps:

The gain error GE of step 1, estimation maximum possible _MaxGain error GE with the minimum permission _Allowed

Calibration times N={ log that step 2, calculating need ₂(GE _Max/ GE _Allowed), wherein, { m} represents to be not less than the smallest positive integral of m;

Step 3, set up reference voltage V _DAC, this reference voltage V _DACBe the N position, full amplitude output is ± V _REF* GE _Max, minimum resolution (1LSB) is V _REF* GE _Max/ 2 ^N-1

Step 4, make reference voltage output bit _DAC=2 ^N-1, time=1;

Step 5, make input value V _In=+V _Full/ 2, (V _FullBe maximum input amplitude), obtain outputting measurement value D _Out=D1 is if noise ratio more greatly can be average in the hope of what repeatedly export;

Step 6, make input value V _In=-V _Full/ 2, obtain outputting measurement value D _Out=D2 is if noise ratio more greatly can be average in the hope of what repeatedly export;

Step 7, make step-length bit _Step=2 ^N-1-time

Step 8, judgement D1-D2 〉=2 ^M-1Whether (M is the figure place of analog to digital converter) sets up, if then make bit _DAC=bit _DAC+ bit _Step, if not, then make bit _DAC=bit _DAC-bit _StepThis also becomes the reference voltage of analog to digital converter into V _REF+ V _DAC=V _REF* (1+GE _Max/ 2), perhaps V _REF+ V _DAC=V _REF* (1-GE _Max/ 2);

Step 9, judge whether time 〉=N-1 sets up, if, carry out step 11, if not, carry out step 10;

Step 10, make time=time+1, carry out step 5;

Step 11, make input value V _In=+V _Full/ 2, obtain outputting measurement value D _Out=D1;

Step 12, make input value V _In=-V _Full/ 2, obtain outputting measurement value D _Out=D2;

Step 13, judgement D1-D2 〉=2 ^M-1Whether set up, if, finish the gain error calibration, carry out step 14, if not, then make bit _DAC=bit _DAC-1, finish the gain error calibration, carry out step 14;

V after step 14, the calibration of use gain error _REF+ V _DACAs reference voltage, make the input value V of analog to digital converter _In=0, obtain outputting measurement value D _Out=D;

Step 15, make D _Offset=D-2 ^M-1

Because output is natural binary code, so the corresponding code value of zero input of analog to digital converter is 2 ^M-1, with D-2 ^M-1As input imbalance D _OffsetValue;

Step 16, make D _Out=D _Out-D _Offset

From the output valve of analog to digital converter, cut D _Offset, be the output valve after the calibration input is lacked of proper care.

In the step 16, only be to carry out subtraction at numeric field, so the analog to digital converter that analog quantitys such as amplifier imbalance are introduced input imbalance still exists, if this imbalance can cause that some circuit " overflows " in the analog to digital converter, calibration steps then of the present invention can not recover out.With the production line analog-digital converter is example, if ideally the output area of first order level circuit (Stage1) just equals the input range of second level level circuit (Stage2), the imbalance of the amplifier of Stage1 may cause the input range of its actual output area greater than Stage2 so, and some input information will " be lost ".But generally, circuit design can leave suitable surplus to non-ideal factors such as amplifier imbalances, and just the output area of Stage1 can be less than the input range of Stage2, so this method is still effective.Certainly, analog quantitys such as amplifier input imbalance can be along with variations in temperature, so, need to calibrate off and on.

Because consider various non-ideal factors in the circuit, (reference voltage is V before the gain error calibration in zero input of analog to digital converter _REF+ 0) and after the gain error calibration (reference voltage is V _REF+ V _DAC) output code value may not be identical, so D _OffsetInput imbalance in the time of should being real work under the reference voltage.

To 5000 analog to digital converters as an example, the effect of the calibrating installation that the diplomatic copy utility model provides.As shown in Figure 3, the gain error of these analog to digital converters before calibration is 2% (3 σ), and as shown in Figure 5, the input imbalance before the calibration is 10mV (3 σ).Target is that gain error is less than 0.1% after the calibration, and input imbalance is less than 1mV.The maximum possible gain error is made as ± 3%, i.e. the full width of cloth output of DAC is made as ± 3%*V _REF, can calculate bit _DAC=6.

After calibrating, as shown in Figure 4, the gain error of these analog to digital converters is controlled in 0.1%; As shown in Figure 6, the input imbalance can reach theoretic null value.

Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited to the appended claims.

Claims (1)

1. the method for the gain error of a calibrating analog-to-digital converter and input imbalance is characterized in that the method includes the steps of:

The gain error GE of step estimation maximum possible _MaxGain error GE with the minimum permission _Allowed

Calibration times N={ log that step 2, calculating need ₂(GE _Max/ GE _Allowed), wherein, { m} represents to be not less than the smallest positive integral of m;

Step 3, set up reference voltage V _DAC, this reference voltage V _DACBe the N position, full amplitude output is ± V _REF* GE _Max, minimum resolution (1LSB) is V _REF* GE _Max/ 2 ^N-1

Step 4, make reference voltage output bit _DAC=2 ^N-1, time=1;

Step 5, make input value V _In=+V _Full/ 2, (V _FullBe maximum input amplitude), obtain outputting measurement value D _Out=D1 is if noise ratio more greatly can be average in the hope of what repeatedly export;

Step 6, make input value V _In=-V _Full/ 2, obtain outputting measurement value D _Out=D2 is if noise ratio more greatly can be average in the hope of what repeatedly export;

Step 7, make step-length bit _Step=2 ^N-1-time

Step 8, judgement D1-D2 〉=2 ^M-1Whether (M is the figure place of analog to digital converter) sets up, if then make bit _DAC=bit _DAC+ bit _Step, if not, then make bit _DAC=bit _DAC-bit _StepThis also becomes the reference voltage of analog to digital converter into V _REF+ V _DAC=V _REF* (1+GE _Max/ 2), perhaps V _REF+ V _DAC=V _REF* (1-GE _Max/ 2);

Step 9, judge whether time 〉=N-1 sets up, if, carry out step 11, if not, carry out step 10;

Step 10, make time=time+1, carry out step 5;

Step 1 makes input value V _In=+V _Full/ 2, obtain outputting measurement value D _Out=D1;

Step 12, make input value V _In=-V _Full/ 2, obtain outputting measurement value D _Out=D2;

Step 13, judgement D1-D2 〉=2 ^M-1Whether set up, if, finish the gain error calibration, carry out step 14, if not, then make bit _DAC=bit _DAC-1, finish the gain error calibration, carry out step 14;

V after step 14, the calibration of use gain error _REF+ V _DACAs reference voltage, make the input value V of analog to digital converter _In=0, obtain outputting measurement value D _Out=D;

Step 15, make D _Offset=D-2 ^M-1

Because output is natural binary code, so the corresponding code value of zero input of analog to digital converter is 2 ^M-1, with D-2 ^M-1As input imbalance D _OffsetValue;

Step 16, make D _Out=D _Out-D _Offset

From the output valve of analog to digital converter, cut D _Offset, be the output valve after the calibration input is lacked of proper care.

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