CN113608111B - System for accurately detecting input signal amplitude - Google Patents
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- CN113608111B CN113608111B CN202110650686.9A CN202110650686A CN113608111B CN 113608111 B CN113608111 B CN 113608111B CN 202110650686 A CN202110650686 A CN 202110650686A CN 113608111 B CN113608111 B CN 113608111B
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Abstract
The invention discloses a system for accurately detecting the amplitude of an input signal, which comprises: two-way selector, comparator, digital logic circuit and register, D/A converter, reference signal source; the input signal is coupled with the first input ends of the two-way selector, and the output end of the reference signal source is coupled with the second input ends of the two-way selector; the output ends of the two-way selector are coupled with the first input end of the comparator; the second input end of the comparator is coupled with the output end of the digital-to-analog converter; the input ends of the digital logic circuit and the register are coupled with the output end of the comparator, and the output ends of the digital logic circuit and the register are coupled with the input end of the digital-to-analog converter; and the output end of the comparator outputs an indication signal for judging whether the amplitude of the input signal exceeds a set threshold value. The invention can accurately detect the amplitude of the high-frequency input signal.
Description
Technical Field
The present invention relates to the field of communication systems, and in particular, to a system for accurately detecting the amplitude of an input signal.
Background
Detection of the amplitude of an input signal is a common requirement in communication systems. Amplitude detection, which is accurate and has a sufficiently large applicability, can provide very useful information for communication systems. In wireless communication and wired communication, an input signal is generally a high-frequency signal, and an amplitude/peak detection circuit is required to convert the input signal into a direct current voltage/current, compare the direct current voltage/current with a direct current reference voltage/current, and determine whether the input amplitude is greater than or less than a set threshold value.
In the conventional input signal amplitude detection scheme shown in fig. 1, an input signal is superimposed with a dc offset voltage 3, amplified by an amplifier 4, superimposed with a dc offset voltage 5, converted into a dc voltage by a peak detection circuit 6, and superimposed with a dc offset voltage 7 to obtain a voltage 18, which is input to a comparator 8, and a reference voltage 19 is input to the other end of the comparator 8, where the reference voltage 19 is a settable dc voltage and serves as a set input amplitude detection threshold.
The difference between the voltages at the two inputs of the comparator in fig. 1 is:
V18-V19＝((Vin+VOS3)A20+VOS5)A6+VOS7-V19 (1)
wherein, VinRepresenting the input signal amplitude; v18Represents the voltage at 18 in fig. 1; v19Represents the dc reference voltage at 19; a. the20Represents the gain of the amplifier (4); vOS3Represents the dc offset voltage 3; vOS5Represents the dc offset voltage 5; a. the6Indicating the gain of the peak detection circuit 6；VOS7Indicating the dc offset voltage 7 of the comparator 8. V18-V19A decision of greater than 0 or less than 0 determines the comparator output 13, i.e. the decision that the input amplitude is greater or less than a certain threshold. Thus:
the above formula represents: for input amplitude VinThe size decision is subjected to VOS3、VOS5、VOS7Influence of error, simultaneously with A6And A20It is related. V of each chip due to process variation of chip manufactureOS3、VOS5、VOS7、A6、A20There will be deviations and also be affected by temperature variations. Thus, the set DC voltage V19Cannot ensure Vin_thIs a precise fixed value.
Therefore, the conventional high frequency input amplitude detection method has the following disadvantages: 1. the detection precision is poor; 2. the detection range is smaller; 3. temperature changes affect the detection accuracy; 4. the chip is required to be trimmed according to the test after production, so that the cost and the complexity are greatly increased.
Disclosure of Invention
The present invention has been made in view of the above problems, so as to provide a system for accurately detecting the amplitude of an input signal.
In one embodiment of the present invention, a system for accurately detecting the amplitude of an input signal is provided, comprising: the device comprises two selectors 2, a comparator 8, a digital logic circuit and register 9, a digital-to-analog converter 10 and a reference signal source 11;
the input signal is coupled to the first input end of the two-way selector 2, and the output end of the reference signal source 11 is coupled to the second input end of the two-way selector 2;
the output end of the two-way selector 2 is coupled with the first input end of the comparator 8;
a second input end of the comparator 8 is coupled to the output end of the digital-to-analog converter 10;
the input end of the digital logic circuit and register 9 is coupled to the output end of the comparator 8, and the output end of the digital logic circuit and register 9 is coupled to the input end of the digital-to-analog converter 10;
the output end of the comparator 8 outputs an indication signal for judging whether the amplitude of the input signal exceeds a set threshold value.
Further, a controllable gain amplifier 4 is also included; the controllable gain amplifier 4 is coupled between the output of the two-way selector 2 and a first input of a comparator 8.
Further, a peak detection circuit 6 is included; the peak detection circuit 6 is coupled between the output of the controllable gain amplifier 4 and a first input of a comparator 8.
Further, the system for accurately detecting the amplitude of the input signal operates in a calibration mode or a detection mode.
Further, when the system for accurately detecting the amplitude of the input signal works in the calibration mode, the two-way selector 2 selects the reference signal source 11, the comparator 8, the digital logic circuit, the register 9 and the digital-to-analog converter 10 jointly form an analog-to-digital converter ADC, and after quantization of at least one clock cycle, a signal at the first input end of the comparator 8 is stored in the register.
Further, when the temperature changes, the calibration mode is restarted.
Further, when the system for accurately detecting the amplitude of the input signal works in the detection mode, the two-way selector 2 selects the input signal, the digital-to-analog converter 10 converts the digital signal 14 stored in the register into the analog reference voltage 19, and the comparator 8 compares the first input end signal with the analog reference voltage 19 to output the indication signal.
Further, when the amplitude of the input signal is greater than a set threshold value, the indication signal is at a first level; and when the amplitude of the input signal is smaller than the set threshold value, the indicating signal is at a second level.
Further, the reference signal source 11 includes: a high-speed signal source 11-1 and a precise amplitude limiter 11-2; the output end of the high-speed signal source 11-1 is coupled to the input end of the precision amplitude limiter 11-2, and outputs a high-speed reference signal 11-5 capable of precisely controlling amplitude after amplitude limiting by the precision amplitude limiter 11-2.
Further, the high speed signal source 11-1 includes a Voltage Controlled Oscillator (VCO) or a high speed pseudo random signal generator (PRBS generator).
Further, the precision limiter 11-2 includes: a resistor pair 11-6, a transistor pair 11-7 and a controllable current source 11-8; a first terminal of a first transistor of the transistor pair 11-7 is coupled to a first terminal of a first resistor of the resistor pair 11-6, a second terminal of the first resistor is coupled to a supply voltage, a second terminal of the first transistor is coupled to a first terminal of a controllable current source 11-8, and a second terminal of the controllable current source 11-8 is grounded; a first terminal of a second transistor of the transistor pair 11-7 is coupled to a first terminal of a second resistor of the resistor pair 11-6, a second terminal of the second resistor is coupled to the supply voltage, and a second terminal of the second transistor is coupled to a first terminal of the controllable current source 11-8; the control ends of the first transistor and the second transistor are used as the input ends of the precise amplitude limiter 11-2, and the first end of the first transistor and the first end of the second transistor form the output end of the precise amplitude limiter 11-2.
In another embodiment of the present invention, a communication system is provided comprising the system for accurately detecting the amplitude of an input signal.
The beneficial technical effects of the invention are as follows:
(1) the invention discloses a system for accurately detecting the amplitude of an input signal, which can eliminate various errors of a detection system through an automatic calibration mode, improve the detection precision, simultaneously does not need additional trimming and reduces the cost and the complexity.
(2) When the temperature changes greatly, the automatic calibration mode is restarted, the influence of temperature change is eliminated, and the detection precision is further improved.
(3) The invention discloses a high-precision high-speed reference signal source, which further improves the detection precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.
Fig. 1 is a schematic structural diagram of a conventional input signal amplitude detection scheme;
fig. 2 is a schematic structural diagram of a system for accurately detecting an amplitude of an input signal according to an embodiment of the present invention.
Fig. 3 is a schematic structural diagram of a high-speed reference signal source with controllable amplitude according to an embodiment of the present invention.
Fig. 4 is a schematic structural diagram of an amplitude-controllable precision amplitude limiter according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the invention provides a system for accurately detecting the amplitude of an input signal. When the system starts to work, the automatic calibration mode is entered: generating a high-speed reference signal according to the set amplitude, amplifying the high-speed reference signal, outputting the amplified high-speed reference signal to a peak detection circuit to generate a direct current voltage, quantizing the direct current voltage into digital bits through a comparator and a digital logic circuit, storing the digital bits into a register as a stored reference voltage, further quantizing and storing various errors of the detection system into the stored reference voltage, and ending the calibration mode at the moment. The system enters a normal working/detection mode: the stored reference voltage is converted into an analog direct current voltage through a digital-to-analog converter and serves as a reference voltage of the comparator, at this time, the reference voltage of the comparator contains various errors, and the errors can be counteracted with corresponding errors in a detection path, so that the judgment precision of the comparator is not influenced, namely the detection precision of the input amplitude is not influenced.
The invention is described in further detail below with reference to the figures and the embodiments.
An embodiment of the present invention provides a schematic structural diagram of a system for accurately detecting an amplitude of an input signal, as shown in fig. 2, a system 16 for accurately detecting an amplitude of an input signal provided by an embodiment of the present invention includes: the device comprises a two-way selector 2, a controllable gain amplifier 4, a peak detection circuit 6, a comparator 8, a digital logic circuit and register 9, a digital-to-analog converter 10 and a high-speed reference signal source 11 with controllable amplitude.
Specifically, an input signal is coupled to a first input terminal of the two-way selector 2, and an output terminal of the amplitude-controllable high-speed reference signal source 11 is coupled to a second input terminal of the two-way selector 2, and is configured to input a reference signal 12 to the two-way selector 2;
the output end of the two-way selector 2 is coupled with the input end of the controllable gain amplifier 4 and used for selecting to input an input signal or a reference signal 12 into the controllable gain amplifier 4, and the controllable gain amplifier 4 is provided with an input direct-current offset voltage 3;
the output end of the controllable gain amplifier 4 is coupled to the input end of the peak detection circuit 6, and is used for amplifying the input signal or the reference signal 12 and outputting the amplified signal to the peak detection circuit 6, so as to prevent the signal input to the peak detection circuit 6 from being too small or too large, and the peak detection circuit 6 has an input dc offset voltage 5;
the output end of the peak detection circuit 6 is coupled to the first input end of the comparator 8, and is used for converting the ac signal into a dc signal 18 and outputting the dc signal to the comparator 8, where the comparator 8 has an input dc offset voltage 7;
a second input terminal of the comparator 8 is coupled to the output terminal of the digital-to-analog converter 10, and is configured to compare the dc signal 18 with an analog reference voltage 19 to generate an output signal 13;
the input end of the digital logic circuit and register 9 is coupled to the output end of the comparator 8, and the output end of the digital logic circuit and register 9 is coupled to the input end of the digital-to-analog converter 10; a digital logic circuit and register 9 and a digital to analog converter 10 for converting the output signal 13 to an analog reference voltage 19.
Further, the input signal and the reference signal 12 are differential signals.
In another embodiment of the present invention, the input signal and reference signal 12 are single-ended signals.
In another embodiment of the present invention, the present invention further provides a communication system comprising a signal path transmission module 1, a system 16 for accurately detecting the amplitude of an input signal; the signal path transmission module 1 is used for transmitting an input signal.
The specific working process of the invention is as follows:
when the communication system is initially in operation, the system 16 for accurately detecting the amplitude of the input signal enters a calibration mode: the two-way selector 2 selects the high-speed reference signal 12 to be conducted; according to a set amplitude threshold value, a high-speed reference signal source 11 with controllable amplitude generates a high-speed reference signal 12; the speed of the high-speed reference signal 12 is similar to that of the input signal, and the amplitude of the high-speed reference signal is accurate and controllable; a high-speed reference signal 12 passes through the two-way selector 2, an additional input direct-current offset voltage 3 is added, the high-speed reference signal is amplified through the controllable gain amplifier 4, an additional input direct-current offset voltage 5 is added, the high-speed reference signal is converted into a direct-current voltage through the peak detection circuit 6, the additional input direct-current offset voltage 7 is added, and a direct-current signal 18 is obtained and input to the comparator 8; the comparator 8, the digital logic circuit and register 9 and the digital-to-analog converter 10 jointly form an analog-to-digital converter ADC; after a plurality of clock cycles, a plurality of times of comparator comparison and digital logic operation, the direct current signal 18 can be quantized into a multi-bit digital signal 14 (a string of characters consisting of '0' and '1'), and the digital signal 14 at the moment is stored in a register for later use; at this point, the calibration mode ends. It should be noted that the dc signal 18 of the above process includes the error dc offset voltages 3, 5, and 7, and also includes errors of the two-way selector 2, the controllable gain amplifier 4, the peak detection circuit 6, and the influence error of the temperature during calibration, which are all quantitatively stored in the digital signal and stored in the register.
When the communication system is operating normally, the system 16 for accurately detecting the amplitude of the input signal enters a detection mode: the two-way selector 2 selects the input signals to be conducted, and the high-speed reference signal source 11 can be turned off without working; an input signal passes through a two-way selector 2, an extra input direct current offset voltage 3, a controllable gain amplifier 4, an extra input direct current offset voltage 5, a peak detection circuit 6 and an extra input direct current offset voltage 7 to reach a first input end of a comparator; meanwhile, the digital logic circuit and the register inside the register 9 output the stored digital signal 14 to the digital-to-analog converter 10, and then output as an analog reference voltage 19; the analog reference voltage 19 is actually a direct current signal 18 stored in a calibration mode, and the direct current signal 18 is obtained by passing a high-speed reference signal 12 with a set amplitude through the two-way selector 2, the additional input direct current offset voltage 3, the controllable gain amplifier 4, the additional input direct current offset voltage 5, the peak detection circuit 6 and the additional input direct current offset voltage 7; the dc signal 18 in the calibration mode is compared with the dc signal 18 in the normal operation/detection mode through the comparator 8, and then errors caused by the two-way selector 2, the additional input dc offset voltage 3, the controllable gain amplifier 4, the additional input dc offset voltage 5, the peak detection circuit 6, and the additional input dc offset voltage 7 are subtracted and cancelled. Therefore, the present invention can realize amplitude detection with higher accuracy with less influence of errors caused by manufacturing processes/temperatures, etc.
At this time, the output signal of the comparator 8 is an indication signal for determining whether the amplitude of the input signal exceeds a set threshold. When the amplitude of the input signal is larger than a certain set threshold value, outputting a '0' which represents that the input amplitude is large enough; when the input signal amplitude is smaller than the set threshold value, a "1" is output, which represents that the input amplitude is too small.
Satisfies the formula (3) in the calibration mode:
V18_trim＝((V12_trim×A2+VOS3)A4+VOS5)A6+VOS7 (3)
wherein V18_trimRepresenting the voltage at 18 in fig. 2 in calibration mode; v12_trimRepresents the amplitude of the high speed reference signal at 12; a. the2Represents the gain of the two-way selector 2; vOS3Represents the input dc offset voltage 3 of the controllable gain amplifier 4; a. the4Represents the gain of the controllable gain amplifier 4; vOS5An input dc offset voltage 5 representing a peak detection circuit 6; a. the6Represents the gain of the peak detection circuit 6; vOS7Representing the input dc offset voltage of comparator 8.
The normal operation/detection mode satisfies the formulas (4), (5), (6):
V18_det＝((Vin×A2+VOS3)A4+VOS5)A6+VOS7 (4)
V19_det≈V18_trim＝((V12_trim×A2+VOS3)A4+VOS5)A6+VOS7 (5)
V18_det-V19_det≈(Vin-V12_trim)A2A4A6 (6)
wherein, V18_detVoltage at 18 in normal operating/sensing mode; v19_detVoltage at 19 in normal operating/sensing mode; vinInputting the signal amplitude for the system; v18_det-V19_detIs the difference between the input voltages at the two ends of the comparator 8.
By formula (6):
V18_det-V19_det＞0＜＝>Vin-V12_trim＞0 (7)
V18_det-V19_det＜0<＝>Vin-V12_trim＜0 (8)
equations (7) and (8) show that the output of comparator 8 is equal to either "0" or "1", as measured by the input signal amplitude VinAnd accurate high speed reference signal V12_trimIs determined as long as V12_trimThe waveform of (2) is similar to that of the input signal, and the amplitude is accurate, which means that the amplitude of the input signal can be accurately detected. And formula (7) and(8) is established with A2、A4、A6、VOS3、VOS5、VOS7Is irrelevant; in addition, when the temperature changes, the calibration mode can be restarted, and the influence of the temperature can be eliminated.
Another embodiment of the present invention provides a schematic structural diagram of a high-speed reference signal source 11 with controllable amplitude, as shown in fig. 3, the high-speed reference signal source 11 with controllable amplitude provided in the embodiment of the present invention includes: a high-speed signal source 11-1 and a precise amplitude limiter 11-2.
Specifically, the output end of the high-speed signal source 11-1 is coupled to the input end of the precision amplitude limiter 11-2, the high-speed signal source 11-1 generates a high-amplitude high-speed oscillation signal 11-4, and the high-speed oscillation signal 11-5 capable of precisely controlling the amplitude is output after being limited by the precision amplitude limiter 11-2.
Further, the amplitude of the output signal of the precision amplitude limiter 11-2 can be precisely limited by the amplitude limiting control signal 11-3.
Further, the high speed signal source 11-1 includes a Voltage Controlled Oscillator (VCO) or a high speed pseudo random signal generator (PRBS generator).
Further, the high-speed signal source 11-1 includes a voltage-controlled oscillator and a frequency divider.
Another embodiment of the present invention provides a schematic structural diagram of an amplitude-controllable precision amplitude limiter 11-2, as shown in fig. 4, the amplitude-controllable precision amplitude limiter 11-2 provided in the embodiment of the present invention includes: a resistor pair 11-6, a transistor pair 11-7, and a controllable current source 11-8.
Specifically, a first terminal of a first transistor in the transistor pair 11-7 is coupled to a first terminal of a first resistor in the resistor pair 11-6, a second terminal of the first resistor is coupled to the power supply voltage, a second terminal of the first transistor is coupled to a first terminal of the controllable current source 11-8, and a second terminal of the controllable current source 11-8 is grounded;
a first terminal of a second transistor of the transistor pair 11-7 is coupled to a first terminal of a second resistor of the resistor pair 11-6, a second terminal of the second resistor is coupled to the supply voltage, and a second terminal of the second transistor is coupled to a first terminal of the controllable current source 11-8;
the first end of the first transistor and the first end of the second transistor form the output end of the precision amplitude limiter 11-2; the high-speed oscillation signal 11-4 with large amplitude is input to the control end of the transistor pair 11-7, and the high-speed reference signal 11-5 with accurate amplitude control is generated through the conduction control of the transistor pair 11-7.
When the amplitude of the input high-speed oscillation signal 11-4 is large enough, the transistor pair 11-7 enters an on/off switching working mode; i.e. only one of the two transistors is conducting, the current of the controllable current source 11-8 will flow completely into one of the resistors of the resistor pair 11-6 and then switch back and forth according to the waveform of the input signal. Thus, the amplitude of the output high-speed reference signal 11-5 satisfies equation (9):
V12_trim＝2×I×R (9)
wherein, I is the direct current of the controllable current source 11-8, and R is the resistance value of the resistance pair 11-6.
By designing the I multiplied by R to be in direct proportion to accurate band gap reference voltage, accurate output amplitude control is achieved.
The high-precision high-speed reference signal source 11 provided by the embodiment of the invention further improves the detection precision.
It is also noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a good or system that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such good or system. The term "comprising", without further limitation, means that the element so defined is not excluded from the article or system in which the element is included.
The foregoing description shows and describes several preferred embodiments of the invention, but as aforementioned, it is to be understood that the invention is not limited to the forms disclosed herein, but is not to be construed as excluding other embodiments and is capable of use in various other combinations, modifications, and environments and is capable of changes within the scope of the inventive concept as expressed herein, commensurate with the above teachings, or the skill or knowledge of the relevant art. And that modifications and variations may be effected by those skilled in the art without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A system for accurately detecting the amplitude of an input signal, comprising: the device comprises two selectors 2, a comparator 8, a digital logic circuit and register 9, a digital-to-analog converter 10, a reference signal source 11, a controllable gain amplifier 4 and a peak detection circuit 6;
the input signal is coupled to the first input end of the two-way selector 2, and the output end of the reference signal source 11 is coupled to the second input end of the two-way selector 2;
the output end of the two-way selector 2 is coupled with the input end of the controllable gain amplifier 4;
the output end of the controllable gain amplifier 4 is coupled to the input end of the peak detection circuit 6;
the output end of the peak detection circuit 6 is coupled to the first input end of the comparator 8;
a second input end of the comparator 8 is coupled to the output end of the digital-to-analog converter 10;
the input end of the digital logic circuit and register 9 is coupled to the output end of the comparator 8, and the output end of the digital logic circuit and register 9 is coupled to the input end of the digital-to-analog converter 10;
the output end of the comparator 8 outputs an indication signal for judging whether the amplitude of the input signal exceeds a set threshold value.
2. The system for accurately detecting the amplitude of an input signal as claimed in claim 1, wherein the system for accurately detecting the amplitude of an input signal operates in a calibration mode or a detection mode.
3. The system for accurately detecting the amplitude of an input signal according to claim 2, wherein when the system for accurately detecting the amplitude of an input signal is operating in the calibration mode, the two-way selector 2 selects the reference signal source 11, and the comparator 8, the digital logic circuit and register 9, and the digital-to-analog converter 10 together form an analog-to-digital converter ADC, and after quantization for at least one clock cycle, the signal at the first input terminal of the comparator 8 is stored in a register in the digital logic circuit and register 9.
4. A system for accurately detecting the amplitude of an input signal as claimed in claim 3, wherein the calibration mode is restarted when a temperature change occurs.
5. The system for accurately detecting the amplitude of an input signal according to claim 2, wherein when the system for accurately detecting the amplitude of an input signal is operating in a detection mode, the two-way selector 2 selects the input signal, the digital-to-analog converter 10 converts the digital signal 14 stored in the digital logic circuit and the register of the register 9 into an analog reference voltage 19, and the comparator 8 compares the first input signal with the analog reference voltage 19 to output an indication signal.
6. The system for accurately detecting the amplitude of an input signal according to claim 1, wherein the indication signal is at a first level when the amplitude of the input signal is greater than a set threshold; and when the amplitude of the input signal is smaller than the set threshold value, the indicating signal is at a second level.
7. The system for accurately detecting the amplitude of an input signal according to claim 1, wherein the reference signal source 11 comprises: a high-speed signal source 11-1 and a precise amplitude limiter 11-2; the output end of the high-speed signal source 11-1 is coupled to the input end of the precision amplitude limiter 11-2, and outputs a high-speed reference signal 11-5 capable of precisely controlling amplitude after amplitude limiting by the precision amplitude limiter 11-2.
8. The system for accurately detecting the amplitude of an input signal according to claim 7, wherein the high speed signal source 11-1 comprises a Voltage Controlled Oscillator (VCO) or a high speed pseudo random signal generator (PRBS generator).
9. The system for accurately detecting the amplitude of an input signal according to claim 7, wherein the accurate amplitude limiter 11-2 comprises: a resistor pair 11-6, a transistor pair 11-7 and a controllable current source 11-8; a first terminal of a first transistor of the transistor pair 11-7 is coupled to a first terminal of a first resistor of the resistor pair 11-6, a second terminal of the first resistor is coupled to a supply voltage, a second terminal of the first transistor is coupled to a first terminal of a controllable current source 11-8, and a second terminal of the controllable current source 11-8 is grounded; a first terminal of a second transistor of the transistor pair 11-7 is coupled to a first terminal of a second resistor of the resistor pair 11-6, a second terminal of the second resistor is coupled to the supply voltage, and a second terminal of the second transistor is coupled to a first terminal of the controllable current source 11-8; the control ends of the first transistor and the second transistor are used as the input ends of the precise amplitude limiter 11-2, and the first end of the first transistor and the first end of the second transistor form the output end of the precise amplitude limiter 11-2.
10. A communication system comprising a system for accurately detecting the amplitude of an input signal as claimed in any one of claims 1 to 9.
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| CN107968667A (en) * | 2016-10-20 | 2018-04-27 | 国民技术股份有限公司 | A kind of DC maladjustment eliminates circuit and method |
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| CN108398590A (en) * | 2017-07-07 | 2018-08-14 | 佛山科学技术学院 | A kind of voltage peak detection circuit of numeral output |
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