WO2021120037A1

WO2021120037A1 - Successive approximation register analog-to-digital converter and mismatch voltage detection method

Info

Publication number: WO2021120037A1
Application number: PCT/CN2019/126181
Authority: WO
Inventors: 高方
Original assignee: 华为技术有限公司
Priority date: 2019-12-18
Filing date: 2019-12-18
Publication date: 2021-06-24
Also published as: CN114788179A

Abstract

An SAR ADC and a mismatch voltage detection method. During capacitance mismatch detection, an SAR control circuit is configured to control, according to a first control signal, a CDAC to output a mismatch voltage. A variable capacitor array is configured to provide a detection voltage. A comparator is configured to generate a comparison result according to the mismatch voltage and the detection voltage. A correction control circuit is configured to generate the first control signal and generate a second control signal according to the comparison result. An RDAC is configured to output an analog voltage according to the second control signal and charge the variable capacitor array generate the detection voltage. In the capacitance mismatch detection process, because the capacitance of the variable capacitor array is adjustable, a variable voltage range is provided. When the capacitance of the variable capacitor array is small, a small voltage range can be provided; because the precision is high in the case of the small voltage range, the detection voltage having adequate precision can be provided on the basis of said voltage range, so as to accurately measure the amount of mismatch of low capacitance in the CADC.

Description

A method for successively approximating analog-to-digital converter and mismatch voltage detection

Technical field

The embodiments of the present application relate to the field of electronic circuits, and in particular to a method for successive approximation register analog-to-digital converter (SAR ADC) and mismatch voltage detection.

Background technique

The digital-to-analog converter (DAC) in the SAR ADC is usually composed of a binary weighted capacitor array. The capacitor array includes a multi-bit capacitor, and the capacitance value of each capacitor increases exponentially with the increase in the number of bits. In practical applications, there will be a certain deviation between the capacitance value of each capacitor and the ideal design value, that is, capacitance mismatch. In order to ensure the performance of the SAR ADC, it is necessary to correct the capacitance mismatch.

The commonly used capacitance mismatch correction technology is a digital background correction technology, which can correct the mismatch amount of each capacitance in the DAC bit by bit. Among them, how to accurately measure the mismatch amount of each capacitance is particularly important. Specifically, this technology controls the capacitors in the DAC to switch to generate a mismatch voltage corresponding to the capacitance to be measured, which can reflect the amount of mismatch of the capacitance to be measured, and then inject a detection voltage into the DAC , So that the detection voltage and the mismatch voltage are offset. Since the size of the detection voltage is known, the amount of mismatch of the capacitance to be measured can be determined by the size of the detection voltage.

This technology usually pre-sets a fixed voltage range, within which detection voltages of different sizes can be provided. Because the mismatch voltage corresponding to the highest capacitance is large, the voltage range usually needs to be set large enough However, when the voltage range is too large, its accuracy is lower, which makes it impossible to accurately measure the mismatch of low-level capacitors.

Summary of the invention

The embodiments of the present application provide a method for successively approximating analog-to-digital converters and mismatch voltage detection, which can accurately measure the capacitance mismatch amount of low-level capacitors in the RDAC.

The first aspect of the embodiments of the present application provides a successive approximation analog-to-digital converter, including: a capacitor digital-to-analog converter (CDAC), a SAR control circuit, a variable capacitor array, a comparator, and a correction Control circuit and resistance digital-to-analog converter (Resistance Digital-to-Analog Converter, RDAC).

When performing the capacitance mismatch detection of the CDAC, the SAR control circuit is used to control the CDAC to output a first voltage according to the first control signal, where the first voltage is the mismatch voltage and is related to the capacitance mismatch amount of the CDAC;

The variable capacitor array is used to provide a second voltage, where the second voltage is a detection voltage for detecting the magnitude of the first voltage;

The comparator is used to compare according to the difference between the first voltage and the second voltage to generate a comparison result;

The correction control circuit is used to generate a first control signal and generate a second control signal according to the comparison result;

The RDAC is used to output an analog voltage according to the second control signal and charge the variable capacitor array to generate the second voltage;

Among them, the capacitance value of the variable capacitor array is adjustable.

In the above-mentioned successive approximation analog-to-digital converter, since the capacitance value of the variable capacitor array for providing the second voltage is adjustable, a variable voltage range is provided. When the capacitance value of the variable capacitor array is small, it can provide a smaller voltage range. Because the voltage range is smaller, its accuracy is higher. Therefore, based on the voltage range, a detection voltage with sufficient accuracy can be provided to accurately measure the RDAC. The amount of capacitance mismatch of the low capacitance.

With reference to the first aspect of the embodiments of the present application, in the first implementation of the first aspect of the embodiments of the present application, the calibration control circuit is also used to generate a third control signal to control the variable capacitor array to adjust the capacitance value .

In the foregoing implementation manner, the third control signal is generated by the correction control circuit to realize the adjustment of the capacitance value of the variable capacitor array, which improves the flexibility and selectivity of the solution.

With reference to the first implementation manner of the first aspect of the embodiments of the present application, in the second implementation manner of the first aspect of the embodiments of the present application, the correction control circuit includes: a state machine for outputting a third control signal, The variable capacitance array is controlled to adjust the capacitance value so that the adjusted capacitance value matches the mismatch amount of the capacitance to be measured.

In the foregoing implementation manner, the third control signal is generated by the state machine in the correction control circuit to realize the adjustment of the capacitance value of the variable capacitance array, so that the capacitance value of the adjusted variable capacitance array is different from the capacitance to be measured. Matching the dosage increases the flexibility and selectivity of the scheme.

In combination with the first implementation or the second implementation of the first aspect of the embodiments of the present application, in the third implementation of the first aspect of the embodiments of the present application, the variable capacitor array includes a plurality of capacitor branches connected in parallel , And each capacitor branch includes a capacitor and a switch connected in series.

In the foregoing implementation manner, a variable capacitor array is formed by a plurality of parallel capacitor branches, which improves the flexibility and selectivity of the solution.

In combination with the third implementation manner of the first aspect of the embodiments of the present application, in the fourth implementation manner of the first aspect of the embodiments of the present application, the variable capacitor array is used to: control at least one capacitor branch according to a third control signal Switch in the switch.

In the foregoing implementation manner, after receiving the third control signal sent by the correction control circuit, the variable capacitor array can control the switch in at least one capacitor branch to switch according to the third control signal, thereby adjusting its own capacitance value so that The adjusted capacitance value can match the mismatch amount of the capacitance to be measured in the RDCA to accurately detect the capacitance mismatch amount of the capacitance to be measured.

In combination with the first aspect of the embodiments of the present application and any one of the first to fourth implementation manners of the first aspect of the embodiments of the present application, in the fifth implementation manner of the first aspect of the embodiments of the present application The SAR control circuit is used to control the capacitor array in the CDAC to switch on and off according to the first control signal to output the first voltage.

In the foregoing implementation manner, after receiving the first control signal sent by the correction control circuit, the SRA control circuit can switch the capacitor array in the CDAC based on the first control signal, so that the CDAC outputs the first voltage, which improves the flexibility of the solution. Degree and selectivity.

In combination with the fifth implementation manner of the first aspect of the embodiments of the present application, in the sixth implementation manner of the first aspect of the embodiments of the present application, the SAR control circuit is used to: control the capacitance of the capacitance to be measured of the capacitance array in the CDAC The switch and the switch of the low capacitance whose median of the capacitance array is lower than the capacitance to be measured are switched to output the first voltage, and the first voltage is related to the mismatch of the capacitance to be measured.

In the foregoing implementation manner, after receiving the first control signal sent by the correction control circuit, the SRA control circuit can switch the capacitance to be measured of the capacitance array in the CDAC based on the first control signal, and the median of the capacitance array is lower than The switch of the low capacitance of the capacitance to be measured is switched, so that the CDAC outputs the first voltage, which improves the flexibility and selectivity of the solution.

The second aspect of the embodiments of the present application provides a method for detecting mismatch voltage, which is applied to a successive approximation analog-to-digital converter, and the successive approximation analog-to-digital converter includes: CDAC, comparator, SAR control circuit, RDAC, The variable capacitance array and the correction control circuit, wherein the capacitance value of the variable capacitance array is adjustable, the method includes:

Generating the first control signal through the correction control circuit;

The SAR control circuit controls the CDAC to output the first voltage according to the first control signal;

Generating a comparison result according to the first voltage and the second voltage through a comparator;

Generating the second control signal according to the comparison result through the correction control circuit;

The RDAC outputs the analog voltage according to the second control signal and charges the variable capacitor array to generate the second voltage.

In the above method for detecting mismatch voltage, since the capacitance value of the variable capacitor array for providing the second voltage is adjustable, a variable voltage range is provided. When the capacitance value of the variable capacitor array is small, it can provide a smaller voltage range. Because the voltage range is smaller, its accuracy is higher. Therefore, based on the voltage range, a detection voltage with sufficient accuracy can be provided to accurately measure the RDAC. The amount of capacitance mismatch of the low capacitance.

With reference to the second aspect of the embodiments of the present application, in the first implementation of the second aspect of the embodiments of the present application, the method further includes: generating a third control signal through the calibration control circuit to control the variable capacitor array to perform capacitance. Value adjustment.

With reference to the first implementation manner of the second aspect of the embodiments of the present application, in the second implementation manner of the second aspect of the embodiments of the present application, the correction control circuit includes: a state machine, which generates a third control signal through the correction control circuit, Adjusting the capacitance value by controlling the variable capacitance array includes:

The third control signal is output through the state machine to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch amount of the capacitance to be measured.

In combination with the first implementation or the second implementation of the second aspect of the embodiments of the present application, in the third implementation of the second aspect of the embodiments of the present application, the variable capacitor array includes a plurality of capacitor branches connected in parallel , And each capacitor branch includes a capacitor and a switch connected in series, and controlling the variable capacitor array to adjust the capacitor value includes:

The variable capacitor array controls the switch in at least one capacitor branch to switch according to the third control signal.

In combination with the second aspect of the embodiments of the present application and any one of the first to third implementation manners of the second aspect of the embodiments of the present application, in the fourth implementation manner of the first aspect of the embodiments of the present application , Controlling the CDAC to output the first voltage according to the first control signal by the SAR control circuit includes:

The SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal to output the first voltage.

In combination with the fourth implementation manner of the second aspect of the embodiments of the present application, in the fifth implementation manner of the second aspect of the embodiments of the present application, the SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal. To output the first voltage includes:

The SAR control circuit controls the switch of the capacitance to be measured of the capacitance array in the CDAC and the switch of the low capacitance of the capacitance array whose median is lower than the capacitance to be measured to output the first voltage, the first voltage and the capacitance to be measured The amount of mismatch of the bit capacitance is correlated.

The third aspect of the embodiments of the present application also provides a communication chip, including an antenna, a radio frequency front-end, a digital processing circuit, and any one of the first aspect or the first implementation to the sixth implementation of the first aspect A said successive approximation analog-to-digital converter;

Antenna, used to receive analog signals;

RF front-end, used for down-frequency processing of analog signals to obtain the down-frequency analog signals;

The successive approximation analog-to-digital converter is used to perform analog-to-digital conversion on the down-frequency analog signal to obtain a digital signal;

Digital processing circuit, used to encode and decode digital signals.

The embodiment of the present application provides a SAR ADC and a method for detecting mismatch voltage. The SAR ADC includes: a CDAC, a comparator, a SAR control circuit, an RDAC, a variable capacitor array, and a correction control circuit. When performing capacitance mismatch detection, the SAR control circuit is used to control the CDAC to output a first voltage according to the first control signal, and the first voltage is related to the capacitance mismatch amount of the CDAC. The variable capacitor array is used to provide a second voltage, and the second voltage is used to detect the magnitude of the first voltage. The comparator is used to generate a comparison result according to the first voltage and the second voltage. The correction control circuit is used to generate a first control signal and generate a second control signal according to the comparison result. The RDAC is used to output an analog voltage and charge the variable capacitor array according to the second control signal to generate the second voltage. In the foregoing capacitance mismatch detection process, since the capacitance of the variable capacitance array is adjustable, a variable voltage range is provided. When the capacitance of the variable capacitor array is small, it can provide a smaller voltage range. Because the voltage range is smaller, its accuracy is higher. Therefore, based on the voltage range, it can provide a second (detection) voltage with sufficient accuracy to be accurate Measure the amount of mismatch of the low capacitance in the CDAC.

Description of the drawings

FIG. 1 is a schematic structural diagram of a SAR ADC provided by an embodiment of the application;

Figure 2 is a schematic diagram of the structure of CDAC;

Figure 3 is a schematic diagram of the capacitance switch state of the CDAC;

Figure 4 is another schematic diagram of the capacitor switch state of the CDAC;

Figure 5 is another schematic diagram of the capacitance switch state of the CDAC;

Fig. 6 is another schematic diagram of the capacitance switch state of the CDAC;

Fig. 7 is a schematic diagram of the structure of the variable capacitor array.

Detailed ways

The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the drawings in the embodiments of the present application.

Fig. 1 is a schematic structural diagram of a SAR ADC provided by an embodiment of the application. Please refer to Fig. 1. The SAR ADC includes a main circuit for analog-to-digital conversion and a correction circuit for capacitance mismatch correction.

The main loop includes CDAC, comparator and SAR control circuit. Among them, the output terminal of CDAC is coupled with the input terminal of the comparator, the output terminal of the comparator is coupled with the input terminal of the SAR control circuit, and the output terminal of the SAR control circuit is coupled with the capacitance of the CDAC Switch coupling. When the SAR ADC is in the analog-to-digital conversion mode, the CDAC first samples and quantizes the input analog signal, and then the comparator compares according to the sampling and quantization results. The SAR control circuit finally outputs the digital signal according to the comparison result, and then completes the analog signal and Conversion between digital signals.

The CDAC can be composed of a binary weighted capacitor array. For ease of understanding, the structure of the CDAC will be described in detail below in conjunction with Figure 2. Figure 2 is a schematic diagram of the structure of the CDAC. As shown in Figure 2, the CDAC is composed of multiple bits with a ^{total capacitance of 2 N.} Capacitor composition, the capacitance value of the highest capacitance is 2 ^N-1 C, the capacitance value of the second highest capacitance is 2 ^N-2 C, and so on, the capacitance value of the lowest capacitance is 1C. However, in practical applications, the actual capacitance value of each capacitor will deviate from the ideal capacitance value. For example, the ideal capacitance value of the lowest capacitance is 1C, and the actual capacitance value may be 0.8C, that is, there is a capacitance mismatch. Therefore, it is particularly important to correct the capacitance mismatch of the CDAC. Among them, the most critical link is the measurement of the capacitance mismatch. Specifically, the capacitance mismatch of each capacitor can be measured through the correction loop.

The correction loop includes RDAC, variable capacitor array and correction control circuit. Among them, the output terminal of the RDAC is coupled with the input terminal of the comparator through the variable capacitance array, the output terminal of the comparator is coupled with the input terminal of the correction control circuit, and the output terminal of the correction control circuit is coupled with the input terminal of the RDAC. The output terminal is coupled with the variable capacitor array, and the output terminal of the correction control circuit is coupled with the input terminal of the SAR control circuit. When the SAR ADC is in the capacitance mismatch correction mode, the capacitance mismatch detection can be performed through the correction loop first.

When the correction loop detects capacitance mismatch, the correction control circuit first generates a first control signal, and sends the first control signal to the SAR control circuit, so that the SAR control circuit controls the CDAC to output the first voltage according to the first control signal (that is, the mismatch Voltage), the first voltage is associated with the capacitance mismatch of the CDAC. In a possible implementation manner, the SAR control circuit controls the capacitor array in the CDAC to switch according to the first control signal, so that the output of the CDAC is the first voltage. Furthermore, the SAR control circuit controls the switches of the capacitance to be measured of the capacitance array in the CDAC and switches of all low capacitances whose median of the capacitance array is lower than the capacitance to be measured to output the first voltage, The first voltage is associated with the mismatch of the capacitance to be measured, that is, the first voltage can reflect the magnitude of the capacitance mismatch of the capacitance to be measured.

Specifically, the first control signal generated by the calibration control circuit is used to indicate the capacitance to be measured in the CDAC. After receiving the first control signal, the SAR control circuit can determine which capacitance in the CDAC is the capacitance to be measured, and A fourth control signal is generated based on the first control signal and sent to the CDAC. The fourth control signal is used to control the switch of the capacitance to be measured and the switches of all low capacitances whose number of bits are lower than the capacitance to be measured. Therefore, after the CDAC receives the fourth control signal, it can switch the switch of the capacitor to be measured and the switches of all the capacitors whose digits are lower than the capacitance to be measured according to the fourth control signal, so that the CDAC output corresponds to the capacitance to be measured The first voltage can reflect the capacitance mismatch of the capacitance to be measured.

For ease of understanding, the following describes the capacitance switch switching process in the above CDAC with reference to FIG. 3, FIG. 4, FIG. 5, and FIG. 6. Figure 3 is a schematic diagram of the capacitance switch state of the CDAC. As shown in Figure 3, the capacitance to be measured is the highest capacitance. At this time, the capacitance of the CDAC is in the normal power-on state, the first switch of all the capacitors (hereinafter referred to as the common terminal) is connected to the common mode voltage V _CM , and the highest capacitance C _{MSB of the} CDAC (capacitance value 2 ^N-1 C) is the first switch The second switch (hereinafter referred to as the free end) is grounded, and the second switch (hereinafter referred to as the free end) of the remaining bit capacitance C _MSB' (the equivalent capacitance of all the remaining bit capacitances whose digits are lower than the highest bit capacitance) is connected to the reference voltage V _DD , In order to measure _{the capacitance mismatch of the highest capacitance C MSB} , the state of the switch can be changed. Figure 4 is another schematic diagram of the capacitance switch state of the CDAC, as shown in Figure 4. At this time, the CDAC controls the capacitance based on the fourth control signal. The switch is switched. Specifically, the common end of all capacitors is not connected to the common mode voltage V _CM , the free end of the highest capacitance C _MSB of CDAC is connected to the reference voltage V _DD , and the free end of the remaining capacitance C _MSB' is grounded, so the common end is generated A first voltage V _RES , and the magnitude of the first voltage V _RES can reflect the capacitance mismatch of the highest capacitance.

In the same way, Fig. 5 is another schematic diagram of the capacitance switch state of the CDAC. As shown in Fig. 5, the capacitance to be measured is assumed to be the next highest capacitance. At this time, the capacitor of CDAC is in the normal power-on state, the common terminal of all capacitors is connected to the common mode voltage V _CM , the highest capacitance C _{MSB of} CDAC (capacitance value 2 ^N-1 C) and the second highest capacitance C _MSB-1 ( The free end of the capacitance value 2 ^N-2 C) is grounded, and the free end of the remaining bit capacitance C _MSB-1' (the equivalent capacitance of all the remaining bit capacitances with a number lower than the second highest capacitance) is connected to the reference voltage V _DD , in order to Measuring the capacitance mismatch of the next highest capacitance C _MSB-1 can change the state of the switch. Figure 6 is another schematic diagram of the capacitance switch state of CDAC, as shown in Figure 6. At this time, CDAC is based on the fourth control signal. The switch of the capacitor is switched. Specifically, the common end of all capacitors is not connected to the common mode voltage V _CM , the free end of the highest capacitance C _MSB of CDAC remains unchanged, and the free end of the second highest capacitance C _MSB-1 (capacitance value 2 ^N-2 C) Connected to the reference voltage V _DD , the free end of the remaining bit capacitance C _MSB-1' is grounded, so a first voltage V _RES-1 is generated at the common end, and the magnitude of the first voltage V _RES-1 can reflect the next highest bit The power loss distribution capacity of the capacitor. In the same way, if it is necessary to measure the capacitance mismatch of the remaining bit capacitors, the above-mentioned operation can also be performed, which will not be repeated here.

After the CDAC generates the first voltage corresponding to the capacitance to be measured, the capacitance value of the variable capacitance array can be adjusted. In a possible implementation manner, the correction control circuit may generate a third control signal and send it to the variable capacitor array to control the variable capacitor array to adjust the capacitance value. Furthermore, the calibration control circuit includes: a state machine for outputting a third control signal to control the variable capacitor array to adjust the capacitance value so that the capacitance value of the adjusted variable capacitance array is equal to the capacitance value of the capacitance to be measured The amount of mismatch matches.

In practical applications, there are many ways to adjust the capacitance value of the variable capacitor array through the third control signal. The specific method is adapted to the structure of the variable capacitor array. In one possible way, the variable capacitor The array includes a plurality of capacitor branches connected in parallel, and each capacitor branch includes capacitors and switches connected in series. In order to facilitate understanding, the structure of the variable capacitor array will be described in detail below in conjunction with FIG. 7, which shows the structure of the variable capacitor array. A schematic diagram of the structure, as shown in Figure 7, the variable capacitor array is composed of multiple capacitors in parallel, and the capacitance value of each capacitor can be set according to actual needs, and there is no specific limitation here. A switch is provided on the branch where each capacitor is located. The switch is controlled by the third control signal generated by the correction control circuit. When a switch is connected to "1", it means that the corresponding capacitor is in the connected state. When the switch is connected to "0", it means that the corresponding capacitor is in the exit state. Therefore, by controlling the switching state of the capacitor branch, the total capacitance value of the variable capacitor array can be changed. Since a capacitance value corresponds to a fixed voltage range, the variable capacitor array provides a variable voltage range. When the capacitance of the variable capacitor array is large, a larger voltage range can be provided, based on which a large enough detection voltage can be provided to accurately measure the capacitance mismatch of the high-level capacitance in the DAC. When the capacitance of the variable capacitor array is small, it can provide a smaller voltage range. Because the voltage range is smaller, its accuracy is higher. Therefore, based on this voltage range, it can provide a detection voltage with sufficient accuracy to accurately measure the low-level of the DAC. The amount of capacitance mismatch of the capacitor.

Furthermore, the variable capacitor array can control the switch in at least one capacitor branch to switch according to the third control signal to adjust its own capacitance value so that the adjusted capacitance value matches the mismatch amount of the capacitance to be measured. Specifically, the correction control circuit may generate a third control signal and send it to the variable capacitor array, so that the variable capacitor array adjusts the size of the capacitor according to the third control signal, where the third control signal includes a signal used to adjust the variable capacitor array Information about its own capacitance value. It is worth noting that the correction control circuit is preset with the corresponding relationship between the capacitance value of the variable capacitor array and the capacitance mismatch of the capacitance to be measured. For example, when the correction control circuit determines that the capacitance to be measured is the highest capacitance (The corresponding capacitance mismatch is the largest). The capacitance value of the variable capacitor array can be maximized by the third control signal. When the calibration control circuit determines that the capacitance to be measured is a low-level capacitance (its corresponding capacitance mismatch Then smaller), the capacitance value of the variable capacitor array can be reduced by the third control signal, and so on. The adjusted variable capacitor array can be equivalent to a capacitor with a fixed capacitance value. The correction control circuit can charge the variable capacitor array through RDAC. If the capacitance value of the variable capacitor array is larger, the RDAC is changing. The maximum voltage that can be generated on the capacitor array is also larger, that is, a larger voltage range is provided. If the capacitance value of the variable capacitor array is small, the maximum voltage that the RDAC can generate on the variable capacitor array is smaller, that is, A smaller voltage range is provided, but its accuracy is higher. Therefore, when the variable capacitor array is adjusted by the calibration control circuit, it is equivalent to providing a voltage range, and the calibration control circuit can select a certain size of the second voltage (detection voltage) within the voltage range to detect and to be measured. The magnitude of the mismatch voltage corresponding to the capacitance is used to determine the capacitance mismatch amount of the capacitance to be measured.

After the capacitance value of the variable capacitor array is adjusted, the correction control circuit can generate a second control signal according to the comparison result output by the comparator, and send the second control signal to the RDAC, so that the RDAC outputs an analog voltage according to the second control signal. The variable capacitor array is charged based on the analog voltage to generate a second voltage on the variable capacitor array.

Specifically, when the variable capacitor array is just adjusted, the input terminal of the comparator is connected to the output terminal of the CDAC and the variable capacitor array. Therefore, the input signal of the comparator is the mismatch voltage corresponding to the capacitance to be measured and the first The difference between the two voltages (because the RDAC has not yet received the second control signal, the variable capacitor array has not been charged yet, that is, the second voltage is zero), that is, V _X =丨V in Figure 2 _RES丨-丨Second voltage丨, after the comparator receives the input signal, it can compare according to the input signal, that is, judge the positive and negative value of the input signal, and then send the comparison result to the correction control circuit. At this time, the comparison result indicates that the difference between the mismatch voltage and the detection voltage is different from zero (for example, the comparison result is 111111……11 or 000000……00, indicating that the difference between the two voltages is always greater than zero or less than Zero, it can be considered that there is a certain gap with zero), the correction control circuit can generate a second control signal according to the comparison result, so that the RDAC charges the variable capacitor array, and generates a second voltage with a certain magnitude on the variable capacitor array . If the comparison result output by the comparator still indicates that there is a gap between the difference between the mismatch voltage and the detection voltage and zero, the correction control circuit can continue to generate a second control signal according to the comparison result, which is used to adjust the The magnitude of the second voltage until the comparison result output by the comparator indicates that the difference between the mismatch voltage and the detection voltage is close to zero, (for example, the comparison result is 101010101010……10, indicating that the difference between the two voltages is greater than zero If you switch between and less than zero, you can consider that the difference is approximately equal to zero), the correction control circuit can determine that the second voltage is the first voltage, and the second voltage reflects the capacitance loss of the capacitance to be measured. Distributing, that is, the capacitance mismatch detection of the capacitance to be measured is completed.

It is worth noting that the second control signal includes codeword information for adjusting the RDAC and estimated information of the first voltage corresponding to the capacitance to be measured. Specifically, the code word information of the RDAC is the voltage step size for the RDAC to charge the variable capacitor array, and the RDAC can adjust the voltage (ie, the second voltage) of the variable capacitor array according to requirements, as in the detection of the highest capacitance. When corresponding to the first voltage, the voltage step can be set to 0.1V, so that the RDAC adjusts the voltage of the variable capacitor array with a precision of 0.1V. Another example is to set the voltage step when detecting the first voltage corresponding to the lowest capacitance. The length is 0.01V, so that the RDAC adjusts the voltage of the variable capacitor array with an accuracy of 0.01V. Therefore, the correction control circuit can control the accuracy when adjusting the magnitude of the second voltage by adjusting the code word information in the second control signal. In addition, the correction control circuit is also preset with the estimated information of the mismatch voltage corresponding to each capacitance of the CDAC. For example, in the CDAC, the actual first voltage corresponding to the highest capacitance is 0.81V, and the lowest capacitance corresponds to If the actual first voltage is 0.0088V, the corresponding estimated information is set in the correction control circuit: the estimated first voltage corresponding to the highest capacitance is 0.80V, and the estimated first voltage corresponding to the lowest capacitance is 0.0090 V. Therefore, the correction control circuit can adjust the magnitude of the second voltage generated by the RDAC on the variable capacitor array by adjusting the estimated information of the mismatch voltage in the second control signal.

As in the above example, when the calibration control circuit is measuring the first voltage corresponding to the highest capacitance, it can generate a second control signal, which contains codeword information of 0.01V, and the value of the first voltage corresponding to the highest capacitance. Estimated information (0.80V). After receiving the second control signal, the RDAC adjusts the second voltage generated by the variable capacitor array with a precision of 0.01V based on the second control signal until the second voltage is about 0.80V (For example, the voltage is floating between 0.79V and 0.82V). At this time, the second voltage generated by the variable capacitor array is almost equal to the first voltage corresponding to the highest capacitance, and the comparator receives the two After the input signal is composed of the difference between the voltages and compared, the comparison result can be output, which is used to indicate to the correction control circuit that the difference between the two voltages is close to zero, that is, the second voltage can be correctly measured to the highest Based on the first voltage corresponding to the bit capacitance, the capacitance mismatch amount of the highest bit capacitance can be determined based on the second voltage.

After determining the capacitance mismatch of the current capacitance to be measured, the capacitance mismatch detection of the next capacitance can be entered. At this time, the correction control circuit can control the RDAC to reset, thereby making the variable capacitance array in an uncharged state , And then control the CDAC to output the first voltage corresponding to the next capacitor, then adjust the capacitance value of the variable capacitor array, and charge the adjusted variable capacitor array to generate a second voltage, and adjust the size of the second voltage through feedback , The capacitance mismatch amount of the next capacitor is determined by the comparison result of the comparator. For this process, please refer to the aforementioned related content, which will not be described in detail here. After determining the capacitance mismatch of each capacitor in the CDAC, the capacitance mismatch of each capacitor can be gradually corrected.

In the SAR ADC provided in the embodiment of the present application, since the capacitance of the variable capacitor array is adjustable, a variable voltage range is provided. When the capacitance of the variable capacitor array is small, it can provide a smaller voltage range. Because the voltage range is smaller, its accuracy is higher. Therefore, based on this voltage range, it can provide a detection voltage with sufficient accuracy to accurately measure the low-level of the CDAC. The amount of capacitance mismatch.

The above is a specific introduction to the SAR ADC provided by the embodiment of the present application. The method for detecting the mismatch voltage provided by the embodiment of the present application will be described below. The method is applied to the SAR ADC corresponding to FIG. 1, and the method includes:

S1: Generate the first control signal through the correction control circuit;

S2: Control the CDAC to output the first voltage according to the first control signal through the SAR control circuit;

S3: Generate a comparison result according to the first voltage and the second voltage through a comparator;

S4: Generate a second control signal according to the comparison result through the correction control circuit;

S5: Output the analog voltage through the RDAC according to the second control signal and charge the variable capacitor array to generate the second voltage.

It should be noted that, for the specific description of steps S1 to S5, reference may be made to the relevant description part in the embodiment corresponding to FIG. 1, which will not be repeated here.

Optionally, the method further includes: generating a third control signal through the correction control circuit to control the variable capacitor array to adjust the capacitance value.

Optionally, the correction control circuit includes: a state machine, and the third control signal is generated by the correction control circuit to control the variable capacitor array to adjust the capacitance value includes:

Optionally, the variable capacitor array includes a plurality of capacitor branches connected in parallel, and each capacitor branch includes a capacitor and a switch connected in series, and controlling the variable capacitor array to adjust the capacitance value includes:

Optionally, controlling the CDAC to output the first voltage according to the first control signal by the SAR control circuit includes:

Optionally, controlling the capacitor array in the CDAC to switch by the SAR control circuit according to the first control signal to output the first voltage includes:

It should be noted that, for the specific description of each of the above-mentioned optional embodiments, reference may be made to the relevant description part in the embodiment corresponding to FIG. 1, which will not be repeated here.

In addition, after the capacitance mismatch detection of the capacitors of each CDAC is completed, the capacitance mismatch correction can be performed on the CDAC. The capacitance mismatch correction process for the CDAC can be:

(1) Start the capacitance mismatch correction mode;

(2) Start correction from the highest capacitance of CDAC, and control the switch of CDAC to switch, so that CDAC outputs the mismatch voltage corresponding to the highest capacitance;

(3) Control the capacitance switch of the variable capacitance array to switch to control the capacitance of the variable capacitance array;

(4) Adjust the code word information of the RDAC so that the RDAC charges the variable capacitor array to generate a detection voltage;

(5) Read the comparison result of the comparator, adjust the size of the detection voltage or detect the capacitance mismatch of the next capacitor;

(6) Correct the capacitance mismatch of each capacitor of CDAC from high position to low position.

The embodiment of the present application also relates to a communication chip. The communication chip may be, for example, an information transceiver chip in an optical communication system, and a data acquisition chip in a medical imaging system, an industrial process control system, etc. The communication chip includes: an antenna, RF front-end, digital processing circuit and SAR ADC corresponding to Figure 1.

Among them, the antenna is used to receive analog signals. The radio frequency front end is used to perform frequency reduction processing on the analog signal to obtain the reduced frequency analog signal. SAR ADC is used to perform analog-to-digital conversion on the down-converted analog signal to obtain a digital signal. Digital processing circuit, used to encode and decode digital signals.

In the above chip, because the SAR ADC includes a main circuit for analog-to-digital conversion and a correction circuit for capacitance mismatch correction, the correction circuit has an adjustable variable capacitance array, so it can accurately measure the low level of the CDAC in the main circuit. The amount of mismatch of the capacitance and the realization of capacitance mismatch correction can effectively improve the performance of the communication chip to meet higher demands in practical applications.

Claims

A successive approximation analog-to-digital converter, which is characterized in that it comprises:

Capacitive digital-to-analog converter CDAC;

The successive approximation SAR control circuit is used to control the CDAC to output the first voltage according to the first control signal;

The variable capacitor array is used to provide the second voltage;

A comparator, configured to generate a comparison result according to the first voltage and the second voltage;

A correction control circuit for generating the first control signal, and generating a second control signal according to the comparison result;

The resistance digital-to-analog converter RDAC is configured to output an analog voltage according to the second control signal and charge the variable capacitor array to generate the second voltage;

Wherein, the capacitance value of the variable capacitor array is adjustable.
The successive approximation analog-to-digital converter according to claim 1, wherein the correction control circuit is further configured to generate a third control signal to control the variable capacitor array to adjust the capacitance value.
The successive approximation analog-to-digital converter according to claim 2, wherein the correction control circuit comprises: a state machine, and the state machine is used to output the third control signal to control the variable capacitor array The capacitance value is adjusted so that the adjusted capacitance value matches the mismatch amount of the capacitance to be measured.
The successive approximation analog-to-digital converter according to claim 2 or 3, wherein the variable capacitor array includes a plurality of capacitor branches connected in parallel, and each capacitor branch includes a capacitor and a switch connected in series.
The successive approximation analog-to-digital converter according to claim 4, wherein the variable capacitor array is used to control at least one switch in the capacitor branch to switch according to the third control signal.
The successive approximation analog-to-digital converter according to any one of claims 1 to 5, wherein the SAR control circuit is used to control the capacitor array in the CDAC to switch according to the first control signal, so as to The first voltage is output.
The successive approximation analog-to-digital converter according to claim 6, wherein the SAR control circuit is used to: control the switch of the capacitance to be measured of the capacitance array in the CDAC, and the median of the capacitance array A switch of a low capacitance lower than the capacitance to be measured is switched to output the first voltage, and the first voltage is associated with a mismatch amount of the capacitance to be measured.
A method for detecting mismatch voltage is characterized in that it is applied to a successive approximation analog-to-digital converter, and the successive approximation analog-to-digital converter includes: CDAC, comparator, SAR control circuit, RDAC, variable capacitor array, and correction control A circuit, wherein the capacitance value of the variable capacitance array is adjustable, and the method includes:

Generating a first control signal through the correction control circuit;

Controlling the CDAC to output the first voltage according to the first control signal through the SAR control circuit;

Generating a comparison result according to the first voltage and the second voltage by the comparator;

Generating a second control signal according to the comparison result by the correction control circuit;

The RDAC outputs an analog voltage according to the second control signal and charges the variable capacitor array to generate the second voltage.
8. The method according to claim 8, wherein the method further comprises: generating a third control signal through the correction control circuit to control the variable capacitor array to adjust the capacitance value.
The method according to claim 9, wherein the correction control circuit comprises: a state machine, and the generation of a third control signal by the correction control circuit to control the variable capacitor array to adjust the capacitance value comprises :

The third control signal is output by the state machine to control the variable capacitor array to adjust the capacitance value so that the adjusted capacitance value matches the mismatch amount of the capacitance to be measured.
The method according to claim 9 or 10, wherein the variable capacitor array includes a plurality of capacitor branches connected in parallel, and each capacitor branch includes a capacitor and a switch connected in series, and the control of the variable capacitor The adjustment capacitance value of the capacitor array includes:

The variable capacitor array controls at least one switch in the capacitor branch to switch according to the third control signal.
The method according to any one of claims 8 to 11, wherein the controlling the CDAC to output the first voltage according to the first control signal by the SAR control circuit comprises:

The SAR control circuit controls the capacitor array in the CDAC to switch on and off according to the first control signal to output the first voltage.
The method according to claim 12, wherein the controlling the capacitor array in the CDAC to switch on and off according to the first control signal by the SAR control circuit to output the first voltage comprises:

The SAR control circuit controls the switch of the capacitance to be measured of the capacitance array in the CDAC, and the switch of the low capacitance of the capacitance array whose median is lower than the capacitance to be measured is switched to output the The first voltage is associated with the mismatch amount of the capacitance to be measured.
A communication chip, characterized by comprising an antenna, a radio frequency front end, a digital processing circuit, and the successive approximation analog-to-digital converter according to any one of claims 1 to 7;

The antenna is used to receive analog signals;

The radio frequency front end is used to perform frequency reduction processing on the analog signal to obtain a frequency-reduced analog signal;

The successive approximation analog-to-digital converter is used to perform analog-to-digital conversion on the frequency-down analog signal to obtain a digital signal;

The digital processing circuit is used for encoding and decoding the digital signal.