CN113437152A - Semiconductor chip structure without using photoetching machine and photoresist and process method thereof - Google Patents
Semiconductor chip structure without using photoetching machine and photoresist and process method thereof Download PDFInfo
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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- H01L29/772—Field effect transistors
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Abstract
The invention discloses a semiconductor chip structure without using a photoetching machine and photoresist and a process method thereof, and the semiconductor chip structure without using the photoetching machine and the photoresist comprises a substrate, wherein a P-type semiconductor layer and an N-type semiconductor layer are sequentially stacked on the substrate and are arranged in a spaced manner, the P-type semiconductor layer is at least 2, and the N-type semiconductor layer is at least 2. The invention forms the P-type semiconductor layer and the N-type semiconductor layer by stacking through a chemical vapor deposition method, and forms the conducting layer by adopting a physical etching and plasma cleaning mode, thereby avoiding using a mask, a photoresist and a photoetching machine to manufacture a semiconductor chip, reducing the process complexity of the semiconductor chip and improving the yield of semiconductor chip products.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a semiconductor chip structure without using a photoetching machine and photoresist and a process method thereof.
Background
Since the advent of semiconductor chips, whether diodes, transistors, NMOS, CMOS, or LED products, the manufacturing process required masks, photoresists, lithography machines, wet etches, or plasma etches. With the continuous reduction of the minimum physical size of the semiconductor chip, the key technology, material, machine and patent technology of the semiconductor chip industry are not mastered in the strong hands of Europe, America, Japan, Korean and the like, and the semiconductor chip industry peels, grazes and even seals the electronic industry and the basic industry in China. For the development and the growth of national nationalities, a new semiconductor production process which thoroughly breaks away from a photomask (mask), a photoresist and a photoetching machine is urgently needed to be searched for in a situation of turning semiconductor process patents to a strong control. Lithography machine (MASK ALIGNER), also known as stepper alignment exposure machine, is a technology similar to photo-lithography. The PHOTO MASK is also called PHOTO MASK or MASK, and has a function similar to a PHOTO negative film, and photoresist liquid (PHOTO RESIST) or photoresist, also called PHOTO RESIST liquid, is further classified as positive photoresist or negative photoresist, and is similar to a positive film or negative film of a PHOTO negative film. The process flow of semiconductor manufacturing using masks, photoresists and lithography machines is shown in figure 1. The production of semiconductor chips using a lithography machine has the following disadvantages:
1) the machine, materials and patents are in the hands of Europe and America, and the sanction crisis is generated to the semiconductor industry of China at any time;
2) the process is too complicated, and strong acid causes environmental pollution;
3) the minimum size of the process is reduced to nanometer level, but the photoresist still adopts the spin coating process, the thickness is still maintained at about 5 microns, so the etching interval of 5 nanometers is formed between the photoresists with the height of 5um, the height ratio reaches 1000 times of terrorism, the larger minimum size photoresist height is more than 200 times of the etching interval, and the process yield of the photoresist and the etching is difficult to control.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a semiconductor chip structure and a process method thereof without using a photo-etching machine and a photo-resist, which overcome the defect that the semiconductor chip process in the prior art can not avoid using a photo-mask, a photo-resist and a photo-etching machine.
The technical scheme adopted by the invention for solving the technical problems is as follows:
the utility model provides a need not use photoetching machine and semiconductor chip structure of photoresist, includes the base plate pile up in proper order on the base plate and set up P type semiconductor layer and N type semiconductor layer, P type semiconductor layer with N type semiconductor layer sets up alternately, P type semiconductor layer is 2 layers at least, N type semiconductor layer is 2 layers at least.
According to an embodiment of the present invention, the substrate is adjacent to one of the P-type semiconductor layers.
According to an embodiment of the present invention, the substrate is adjacent to one of the N-type semiconductor layers.
According to the embodiment of the invention, a P-WELL P-WELL is arranged in the P-type semiconductor layer.
According to the embodiment of the invention, a conductive layer and an insulating layer are arranged in at least part of the P-type semiconductor layer.
According to an embodiment of the present invention, the conductive layer and the insulating layer occupy a local region of the P semiconductor layer.
According to an embodiment of the present invention, a P-type heavily doped region P + is disposed in the P-well.
According to the embodiment of the invention, the conducting layer, the insulating layer, the P-well and the P-type heavily doped region form devices such as a field effect transistor, a capacitor or a resistor in a structural mode and/or a connection mode.
According to an embodiment of the present invention, an N-WELL is provided in the N-type semiconductor layer.
According to the embodiment of the present invention, a conductive layer and an insulating layer are provided in at least a part of the N-type semiconductor layer.
According to an embodiment of the present invention, the conductive layer and the insulating layer occupy a partial region of the N semiconductor layer.
According to the embodiment of the invention, an N-type heavily doped region N + is arranged in the N well.
According to the embodiment of the invention, the conducting layer, the insulating layer, the N well and the N-type heavily doped region form devices such as a field effect transistor, a capacitor or a resistor in a structural mode and/or a connection mode.
According to an embodiment of the present invention, a thickness of the substrate is set to 500 μm to 10000 μm, and thicknesses of the P-type semiconductor layer and the N-type semiconductor layer are set to 0.1 μm to 10 μm.
A semiconductor chip processing method without using a photoetching machine and photoresist comprises the following steps:
a1, arranging a substrate, and arranging a P-type semiconductor layer on the substrate by a chemical vapor deposition method;
a2, simultaneously arranging a conductive layer in the P-type semiconductor layer by a sputtering method, arranging an insulating layer in the P-type semiconductor layer by a chemical vapor deposition method, arranging a P well in the P-type semiconductor layer by the chemical vapor deposition method, and arranging a P-type heavily doped region in the P well by an ion implantation method;
a3, arranging an N-type semiconductor layer on the P-type semiconductor layer through a chemical vapor deposition method;
a4, simultaneously arranging a conductive layer in the N-type semiconductor layer by a sputtering method, arranging an insulating layer in the N-type semiconductor layer by a chemical vapor deposition method, arranging an N well in the N-type semiconductor layer by the chemical vapor deposition method, and arranging an N-type heavily doped region in the N well by an ion implantation method;
a5, arranging a P-type semiconductor layer on the N-type semiconductor layer through a chemical vapor deposition method, and repeating the step A2;
a6, repeating the steps A3 and A4;
a7, repeating the step A5.
According to an embodiment of the present invention, the step a2 includes the steps of: and chemically etching or physically etching the conductive layer.
According to an embodiment of the invention, the physical etching comprises laser engraving, electron beam engraving, ion beam engraving and masked laser engraving.
According to the embodiment of the invention, after the physical etching, plasma cleaning or ultrasonic cleaning is carried out on the etching surface.
A semiconductor chip processing method without using a photoetching machine and photoresist comprises the following steps:
b1, arranging a substrate, and arranging an N-type semiconductor layer on the substrate by a chemical vapor deposition method;
b2, simultaneously arranging a conductive layer in the N-type semiconductor layer by a sputtering method, arranging an insulating layer in the N-type semiconductor layer by a chemical vapor deposition method, arranging an N well in the N-type semiconductor layer by the chemical vapor deposition method, and arranging an N-type heavily doped region in the N well by an ion implantation method;
b3, arranging a P-type semiconductor layer on the N-type semiconductor layer through a chemical vapor deposition method;
b4, simultaneously arranging a conductive layer in the P-type semiconductor layer by a sputtering method, arranging an insulating layer in the P-type semiconductor layer by a chemical vapor deposition method, arranging a P well in the P-type semiconductor layer by the chemical vapor deposition method, and arranging a P-type heavily doped region in the P well by an ion implantation method;
b5, arranging an N-type semiconductor layer on the P-type semiconductor layer through a chemical vapor deposition method, and repeating the step B2;
b6, repeating the steps B3 and B4;
b7, repeating the step B5.
According to an embodiment of the present invention, the step B2 includes the steps of: and chemically etching or physically etching the conductive layer.
According to an embodiment of the invention, the physical etching comprises laser engraving, electron beam engraving, ion beam engraving and masked laser engraving.
According to the embodiment of the invention, after the physical etching, plasma cleaning or ultrasonic cleaning is carried out on the etching surface.
The invention has the beneficial effects that: the invention forms the P-type semiconductor layer and the N-type semiconductor layer by stacking through a chemical vapor deposition method, and forms the conducting layer by adopting a physical etching and plasma cleaning mode, thereby avoiding using a mask, a photoresist and a photoetching machine to manufacture a semiconductor chip, reducing the process complexity of the semiconductor chip and improving the yield of semiconductor chip products.
Drawings
The advantages and realisation of the invention will be more apparent from the following detailed description, given by way of example, with reference to the accompanying drawings, which are given for the purpose of illustration only, and which are not to be construed in any way as limiting the invention, and in which:
FIG. 1 is a prior art semiconductor chip process flow diagram;
FIG. 2 is a schematic diagram of a semiconductor chip structure without using a photolithography machine and a photoresist according to the present invention;
FIG. 3 is a schematic diagram of a field effect transistor formed in a semiconductor chip structure without the use of a lithography machine and photoresist in accordance with the present invention;
FIG. 4 is a flow chart of a semiconductor chip processing method without using a photolithography machine and photoresist according to the present invention.
Detailed Description
As shown in fig. 2 and 3, the semiconductor chip structure without using a photolithography machine and a photoresist according to the present invention includes a substrate 100, on which a P-type semiconductor layer and an N-type semiconductor layer are sequentially stacked and disposed, the P-type semiconductor layer and the N-type semiconductor layer are alternately disposed, the P-type semiconductor layer is at least 2 layers, and the N-type semiconductor layer is at least 2 layers. According to an embodiment of the present invention, the substrate is adjacent to one of the P-type semiconductor layers. The substrate is adjacent to one of the N-type semiconductor layers. A P-WELL 130 (P-WELL) is disposed in the P-type semiconductor layer. A conductive layer 110 and an insulating layer 120 are provided in at least a portion of the P-type semiconductor layer. The conductive layer 110 and the insulating layer 120 occupy a partial region of the P semiconductor layer. A P-type heavily doped region P + is provided in the P well. The conducting layer 110, the insulating layer 120, the P-well 130 and the P-type heavily doped region form devices such as a field effect transistor, a capacitor or a resistor in a structural mode and/or a connection mode, the thickness of the substrate is set to be 500-10000 μm, and the thickness of the P-type semiconductor layer and the N-type semiconductor layer is set to be 0.1-10 μm.
According to another embodiment of the present invention, an N-WELL N-WELL is provided in the N-type semiconductor layer. A conductive layer and an insulating layer are provided in at least a part of the N-type semiconductor layer. The conductive layer and the insulating layer occupy a partial region of the N semiconductor layer. An N-type heavily doped region N + is disposed in the N well. The conducting layer, the insulating layer, the N well and the N-type heavily-doped region form devices such as a field effect tube, a capacitor or a resistor in a structural mode and/or a connection mode, the thickness of the substrate is set to be 500-10000 mu m, and the thicknesses of the P-type semiconductor layer and the N-type semiconductor layer are set to be 0.1-10 mu m.
As shown in fig. 4, the semiconductor chip processing method without using a photolithography machine and a photoresist of the present invention includes the steps of:
a1, arranging a substrate 100, and arranging a P-type semiconductor layer on the substrate 100 by a chemical vapor deposition method;
a2, simultaneously arranging a conductive layer 110 in the P-type semiconductor layer by a sputtering method, an insulating layer 120 in the P-type semiconductor layer by a chemical vapor deposition method, a P well 130 in the P-type semiconductor layer by a chemical vapor deposition method, and a P-type heavily doped region in the P well 130 by an ion implantation method;
a3, arranging an N-type semiconductor layer on the P-type semiconductor layer by a chemical vapor deposition method;
a4, simultaneously arranging a conductive layer in the N-type semiconductor layer by a sputtering method, arranging an insulating layer in the N-type semiconductor layer by a chemical vapor deposition method, arranging an N well in the N-type semiconductor layer by the chemical vapor deposition method, and arranging an N-type heavily doped region in the N well by an ion implantation method;
a5, arranging a P-type semiconductor layer on the N-type semiconductor layer through a chemical vapor deposition method, and repeating the step A2;
a6, repeating the steps A3 and A4;
a7, repeating the step A5.
Step a2 includes the steps of: and chemically etching or physically etching the conductive layer. Physical etching includes laser engraving, electron beam engraving, ion beam engraving, and masked laser engraving. After physical etching, plasma cleaning or ultrasonic cleaning is carried out on the etching surface.
As shown in fig. 4, another embodiment of the semiconductor chip processing method without using a photolithography machine and a photoresist of the present invention includes the steps of:
b1, arranging a substrate, and arranging an N-type semiconductor layer on the substrate by a chemical vapor deposition method;
b2, simultaneously, arranging a conductive layer in the N-type semiconductor layer by a sputtering method, arranging an insulating layer in the N-type semiconductor layer by a chemical vapor deposition method, arranging an N well in the N-type semiconductor layer by the chemical vapor deposition method, and arranging an N-type heavily doped region in the N well by an ion implantation method;
b3, arranging a P-type semiconductor layer on the N-type semiconductor layer through a chemical vapor deposition method;
b4, simultaneously, arranging a conductive layer in the P-type semiconductor layer by a sputtering method, arranging an insulating layer in the P-type semiconductor layer by a chemical vapor deposition method, arranging a P well in the P-type semiconductor layer by the chemical vapor deposition method, and arranging a P-type heavily doped region in the P well by an ion implantation method;
b5, arranging an N-type semiconductor layer on the P-type semiconductor layer through a chemical vapor deposition method, and repeating the step B2;
b6, repeating the steps B3 and B4;
b7, repeating the step B5.
According to an embodiment of the present invention, step B2 includes the steps of: and chemically etching or physically etching the conductive layer. Physical etching includes laser engraving, electron beam engraving, ion beam engraving, and masked laser engraving. After physical etching, plasma cleaning or ultrasonic cleaning is carried out on the etching surface.
The invention aims to solve the problems that the semiconductor production industry must use a photomask, a photoresist, a photoetching machine and wet etching, reduce the cost, shorten the development period, reduce the environmental pollution and enable China to independently and independently produce semiconductors. In order to achieve the above purpose, the present invention provides any material capable of bearing semiconductor elements on a substrate, after the surface activity of the substrate is improved (the substrate can be activated by ion bombardment or laser modification), a WELL layer of a semiconductor is formed by chemical vapor deposition, the WELL can be P-WELL or N-WELL, a source electrode (SOCRCE) and a DRAIN electrode (DRAIN) are sequentially formed, a grid electrode (GATE) is formed by a conductive layer, and two-dimensional and three-dimensional structures of the grid electrode are directly engraved by a laser engraving machine or an electron beam. The invention adopts all physical etching on the semiconductor process, uses laser light or electron beams to directly form three microstructures, and uses a planarization process to ensure the accuracy of each subsequent layer. Most of the cleaning steps of the invention are plasma cleaning, ultrasonic cleaning and plasma bombardment, which are zero-pollution to low-pollution processes. The self-propelled sewage and the gas recovery treatment of the vacuum pump are matched, so that the environmental protection standard can be reached, and no pollution is caused. Plasma cleaning, also known as dry etching (DRY ETCHING), is performed by maintaining a vacuum in a vacuum chamber, introducing a suitable plasma gas, such as argon, or introducing different gases to different etching materials to form a plasma gas or a reactive gas, thereby achieving a suitable etching rate. The process can form a passive device in addition to the active device, and form a capacitor by sandwiching an insulating layer between two metal wires. The metal lines and the well regions may form resistors, and the resistive elements may also form design rules based on a large amount of data. The production process can be generated due to layout without special independent level use. The capacitance method comprises the following steps: the capacitor can be formed by sandwiching a dielectric between the conductive layers of the same area between the adjacent 2 layers. The resistance method comprises the following steps: the resistor can be formed by P-WELL or N-WELL, different resistors can be formed by conducting wires with different widths, and the resistor can be formed by connecting wire connecting HOLEs (CONTACT HOLEs) with different sizes in series with the P-WELL or N-WELL.
As shown in fig. 2, for the P-layer example, the P + and VTP (P-type semiconductor threshold voltage) may be adjusted by ion implantation (ion implantation separates positive and negative ions in a gas, selects appropriate ions to accelerate to an appropriate kinetic energy in a spot magnetic field to improve the ion doping ratio in the semiconductor to form P-WELL or N-WELL or P + and N + regions or adjust the threshold voltage). After P-WELL P-WELL layer, spin coating material with approximate thermal expansion coefficient on the surface of the element, solidifying, depositing by PECVD (PLASMA ENHANCE CHEMICAL VAPOR DEPOSITION), activating the insulating layer, forming N-WELL layer by MOCVD (Metal ORGANIC CHEMICAL VAPOR DEPOSITION) to repeat the generation of N + element. The P-WELL is connected to the elements of the N-WELL layer and to interconnect lines (INTERCONNECTIONs) when the conductor layer is to be formed. Thermal expansion coefficient material: the metal material, the polymer, the non-metal material, the glass and the like have different thermal expansion coefficients, and the material with the thermal expansion coefficient close to that of each layer is used as far as possible in the process flow of the invention, so that the reliability failure caused by expansion with heat and contraction with cold is avoided. And sequentially transferring the sequence of the P-WELL, the N-WELL, the P-WELL and the N-WELL to a circuit design according to the logic design, and then carrying out layout, wherein all elements and interconnection lines are completely finished. After all the elements and the interconnection lines are completed in sequence, the final conductive layer is thickened and a bonding PAD (BOND PAD) is reserved, and the transition to the back-end packaging PROCESS (assembly PROCESS) can be smoothly carried out according to the DESIGN RULE (DESIGN RULE). And (3) a planarization process: coating the water glass on the surface of the chip by a glue scraping mode, evaporating water to be flat, and then performing plasma enhanced chemical vapor deposition or hot wire chemical vapor deposition of SIO2 and using a densification technology to enable the density and the flatness to reach the standard. VTN is the N-type semiconductor threshold voltage.
Compared with the traditional semiconductor production process, the invention has the following advantages:
1. and replacing the photoetching machine with laser etching or ion beams.
1.1 laser etching machine or ion beam, electron beam and other machines, the Chinese advantage is more obvious. The lithography machine is completely monopolized by foreign forces.
1.2 can be intelligently aligned, and the yield is improved.
2. No resist liquid is required.
2.1 the thickness of the photoresist solution is in micron level, and the semiconductor process has been required to reach nanometer level, which is equivalent to the requirement of drilling 1 meter of road in the city wall with a height of 1 km, which is too strict.
2.2 avoid many high-pollution and yield-damaging actions such as developing, fixing, photoresist baking and photoresist removing.
2.3 can be avoided for wet etching, since wet etching is a highly toxic and highly contaminating process.
2.4 for dry etching, the height and width are relatively close, so the process is easier to be carried out, and the yield is also obviously improved.
3. The construction cost of a semiconductor factory can be reduced from billions of dollars to 80 percent and from billions of RMB.
4. All machines, materials and patents are made into a home-made product. Even can be completed by being centralized in an industrial park. Greatly improving the comprehensive competitiveness of China in the field of semiconductors.
As will be apparent to those skilled in the art, many modifications can be made to the invention without departing from the spirit and scope thereof, and it is intended that the present invention cover all modifications and equivalents of the embodiments of the invention covered by the appended claims.
Claims (22)
1. A semiconductor chip structure without using a photoetching machine and photoresist is characterized in that: the semiconductor device comprises a substrate, wherein a P type semiconductor layer and an N type semiconductor layer are sequentially stacked on the substrate, the P type semiconductor layer and the N type semiconductor layer are alternately arranged, the P type semiconductor layer is at least 2 layers, and the N type semiconductor layer is at least 2 layers.
2. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 1, wherein: the substrate is adjacent to one of the P-type semiconductor layers.
3. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 1, wherein: the substrate is adjacent to one of the N-type semiconductor layers.
4. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 1, wherein: and a P WELL P-WELL is arranged in the P type semiconductor layer.
5. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 4, wherein: and a conductive layer and an insulating layer are arranged in at least part of the P-type semiconductor layer.
6. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 5, wherein: the conductive layer and the insulating layer occupy a local region of the P semiconductor layer.
7. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 6, wherein: and a P-type heavily doped region P + is arranged in the P well.
8. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 7, wherein: the conducting layer, the insulating layer, the P well and the P-type heavily-doped region form devices such as a field effect tube, a capacitor or a resistor in a structural mode and/or a connection mode.
9. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 1, wherein: an N-WELL N-WELL is disposed in the N-type semiconductor layer.
10. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 9, wherein: and a conductive layer and an insulating layer are arranged in at least part of the N-type semiconductor layer.
11. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 10, wherein: the conductive layer and the insulating layer occupy a local region of the N semiconductor layer.
12. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 11, wherein: and an N-type heavily doped region N + is arranged in the N well.
13. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 12, wherein: the conducting layer, the insulating layer, the N trap and the N-type heavily-doped region form devices such as a field effect tube, a capacitor or a resistor in a structural mode and/or a connection mode.
14. The semiconductor chip structure without using a photolithography machine and a photoresist according to claim 1, wherein:
the thickness of the substrate is set to be 500 to 10000 μm, and the thickness of the P-type semiconductor layer and the N-type semiconductor layer is set to be 0.1 to 10 μm.
15. A semiconductor chip processing method without using a photoetching machine and photoresist is characterized by comprising the following steps:
a1, arranging a substrate, and arranging a P-type semiconductor layer on the substrate by a chemical vapor deposition method;
a2, simultaneously arranging a conductive layer in the P-type semiconductor layer by a sputtering method, arranging an insulating layer in the P-type semiconductor layer by a chemical vapor deposition method, arranging a P well in the P-type semiconductor layer by the chemical vapor deposition method, and arranging a P-type heavily doped region in the P well by an ion implantation method;
a3, arranging an N-type semiconductor layer on the P-type semiconductor layer through a chemical vapor deposition method;
a4, simultaneously arranging a conductive layer in the N-type semiconductor layer by a sputtering method, arranging an insulating layer in the N-type semiconductor layer by a chemical vapor deposition method, arranging an N well in the N-type semiconductor layer by the chemical vapor deposition method, and arranging an N-type heavily doped region in the N well by an ion implantation method;
a5, arranging a P-type semiconductor layer on the N-type semiconductor layer through a chemical vapor deposition method, and repeating the step A2;
a6, repeating the steps A3 and A4;
a7, repeating the step A5.
16. The semiconductor chip processing method without using a photolithography machine and a photoresist according to claim 15, wherein the step a2 comprises the steps of: and chemically etching or physically etching the conductive layer.
17. The semiconductor chip processing method without using a photolithography machine and a photoresist according to claim 16, wherein: the physical etching comprises laser engraving, electron beam engraving, ion beam engraving and laser engraving with a mask.
18. The semiconductor chip processing method without using a photolithography machine and a photoresist according to claim 17, wherein: and after the physical etching, carrying out plasma cleaning or ultrasonic cleaning on the etching surface.
19. A semiconductor chip processing method without using a photoetching machine and photoresist is characterized by comprising the following steps:
b1, arranging a substrate, and arranging an N-type semiconductor layer on the substrate by a chemical vapor deposition method;
b2, simultaneously arranging a conductive layer in the N-type semiconductor layer by a sputtering method, arranging an insulating layer in the N-type semiconductor layer by a chemical vapor deposition method, arranging an N well in the N-type semiconductor layer by the chemical vapor deposition method, and arranging an N-type heavily doped region in the N well by an ion implantation method;
b3, arranging a P-type semiconductor layer on the N-type semiconductor layer through a chemical vapor deposition method;
b4, simultaneously arranging a conductive layer in the P-type semiconductor layer by a sputtering method, arranging an insulating layer in the P-type semiconductor layer by a chemical vapor deposition method, arranging a P well in the P-type semiconductor layer by the chemical vapor deposition method, and arranging a P-type heavily doped region in the P well by an ion implantation method;
b5, arranging an N-type semiconductor layer on the P-type semiconductor layer through a chemical vapor deposition method, and repeating the step B2;
b6, repeating the steps B3 and B4;
b7, repeating the step B5.
20. The semiconductor chip processing method without using a photolithography machine and a photoresist according to claim 19, wherein the step B2 comprises the steps of: and chemically etching or physically etching the conductive layer.
21. The semiconductor chip processing method without using a photolithography machine and a photoresist according to claim 20, wherein: the physical etching comprises laser engraving, electron beam engraving, ion beam engraving and laser engraving with a mask.
22. The semiconductor chip processing method without using a photolithography machine and a photoresist according to claim 21, wherein: and after the physical etching, carrying out plasma cleaning or ultrasonic cleaning on the etching surface.
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