CN115332069B - Method for etching polycrystalline silicon by dry method and preparation method of semiconductor structure - Google Patents
Method for etching polycrystalline silicon by dry method and preparation method of semiconductor structure Download PDFInfo
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
- H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Abstract
The invention provides a method for dry etching of polycrystalline silicon and a method for preparing a semiconductor structure, wherein the method for dry etching of polycrystalline silicon comprises the following steps: providing a semiconductor substrate; forming a polycrystalline silicon layer on the surface of the semiconductor substrate; forming a photoresist layer on the surface of the polysilicon layer, and patterning the photoresist layer to form an open region and a stop region on the photoresist layer, wherein the open region penetrates through the photoresist layer; performing N-type element ion implantation on the polycrystalline silicon layer below the opening region based on the opening region to realize N-type ion doping on the polycrystalline silicon layer below the opening region; carrying out micro adjustment on the characteristic size of the blocking area to obtain the blocking area with the preset characteristic size; on the basis of the opening area, the polycrystalline silicon layer is etched by a dry method to form a polycrystalline silicon through hole; the photoresist layer is removed. The invention greatly increases the dry etching rate of the polysilicon layer by doping the N-type element to the polysilicon layer, greatly reduces the dry etching time and reduces the influence of physical bombardment on a semiconductor substrate.
Description
Technical Field
The invention relates to the field of semiconductor process preparation, in particular to a method for dry etching of polycrystalline silicon and a preparation method of a semiconductor structure.
Background
As the size of Complementary Metal Oxide Semiconductor (CMOS) processes continues to shrink, the thickness of gate Oxide is also gradually decreasing, and the etching of polysilicon gates becomes more challenging. The polysilicon gate is completely etched, and the gate oxide layer cannot be etched, so that the silicon substrate is damaged.
By adjusting the process pressure, the radio frequency power and the proportion of etching gas in the etching process, the selection ratio of the polysilicon gate to the grid oxide layer can be improved to a certain extent, the etching amount of the grid oxide layer is reduced, and therefore the silicon substrate is prevented from being damaged. However, when the thickness of the gate oxide layer is reduced along with the reduction of the CMOS node, simply increasing the selection ratio can only reduce the chemical etching of the gate oxide layer during the polysilicon etching process, and the physical bombardment of the plasma can still damage the gate oxide layer, thereby causing damage to the silicon substrate, the occurrence of steps on the silicon substrate, and the occurrence of a leakage phenomenon.
In view of the above, there is a need to provide a method for dry etching of polysilicon and a method for manufacturing a semiconductor structure, which are used to solve the problems in the prior art that the damage to a semiconductor substrate can only be reduced by increasing the selectivity, and the influence caused by physical bombardment in the etching process cannot be reduced.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a method for dry etching polysilicon and a method for manufacturing a semiconductor structure, which are used to solve the problems that in the prior art, damage to a semiconductor substrate can only be reduced by increasing a selectivity, and an influence caused by physical bombardment in an etching process cannot be reduced.
In order to achieve the above objects and other related objects, the present invention provides a method for dry etching polysilicon and a method for manufacturing a semiconductor structure, the method for dry etching polysilicon comprising:
s1: providing a semiconductor substrate;
s2: forming a polycrystalline silicon layer on the surface of the semiconductor substrate;
s3: forming a light resistance layer on the surface of the polycrystalline silicon layer, and patterning the light resistance layer so that an opening area and a stopping area are formed on the light resistance layer, and the opening area penetrates through the light resistance layer;
s4: performing N-type element ion implantation on the polycrystalline silicon layer below the opening region based on the opening region to realize N-type ion doping on the polycrystalline silicon layer below the opening region;
s5: carrying out micro adjustment on the characteristic size of the blocking area to obtain the blocking area with a preset characteristic size;
s6: on the basis of the opening area, the polycrystalline silicon layer is subjected to dry etching to form a polycrystalline silicon through hole;
s7: and removing the photoresist layer.
Optionally, in step S1, the semiconductor substrate includes a silicon substrate layer and a gate oxide layer, and the polysilicon layer is in direct contact with the gate oxide layer.
Optionally, in step S2, a method for forming the polysilicon layer is a low pressure chemical vapor deposition method.
Optionally, in step S2, after the polysilicon layer is formed, a step of measuring the thickness of the control wafer of the same batch of the polysilicon layer is further included.
Optionally, after the step S2, the method further includes a step of cleaning the semiconductor substrate and the polysilicon layer on the surface thereof with deionized water, and drying the semiconductor substrate and the polysilicon layer.
Alternatively, in step S4, the N-type element includes phosphorus or arsenic.
Optionally, in step S4, the ions are implantedThe energy range is 8 keV to 20 keV; dosage range of 2e 15 cm -2 ~ 4e 15 cm -2 。
Optionally, in step S5, a plasma deslagging process is used to perform a fine adjustment on the feature size of the blocking region.
Optionally, in step S5, a step of measuring the characteristic size of the blocking area is further included, and if the preset characteristic size is not reached, the characteristic size of the blocking area needs to be resized again until the preset characteristic size is reached.
Optionally, in step S6, the gas used in the dry etching includes a gas containing a halogen element.
The invention also provides a preparation method of the semiconductor structure, which comprises the method for dry etching of the polycrystalline silicon.
As described above, the method for dry etching polysilicon and the method for manufacturing a semiconductor structure according to the present invention have the following advantages: the invention greatly increases the dry etching rate of the polysilicon layer by doping the polysilicon layer with N-type elements, greatly reduces the dry etching time and reduces the influence of physical bombardment on a semiconductor substrate; the invention considers the transverse diffusion of ion implantation in advance, and realizes the requirement of the polycrystalline silicon layer on the characteristic dimension by increasing and carrying out micro adjustment on the characteristic dimension of the stopping area; the invention has simple operation and low cost, and is convenient for popularization.
Drawings
Fig. 1 shows a schematic flow chart of the method for dry etching polysilicon according to the present invention.
Fig. 2 to 8 show the structural schematic diagrams of the steps of the polysilicon dry etching method of the present invention.
Fig. 9 is a schematic diagram of a prior art polysilicon etch followed by transmission electron microscopy.
Fig. 10 shows a schematic diagram of the polysilicon dry etching method of the present invention after etching by a transmission electron microscope.
Description of the element reference numerals
The structure comprises a semiconductor substrate 10, a silicon substrate layer 11, a gate oxide layer 12, a polycrystalline silicon layer 20, a polycrystalline silicon through hole 21, a light resistance layer 30, an opening area 31, a blocking area 32, an N-type element 40, a blocking area characteristic dimension CD1, a blocking area preset characteristic dimension CD2 and a distance CD3 between two adjacent polycrystalline silicon through holes.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
As in the detailed description of the embodiments of the present invention, the cross-sectional views illustrating the device structure are not partially enlarged in general scale for convenience of illustration, and the schematic views are only examples, which should not limit the scope of the present invention.
For convenience in description, spatial relational terms such as "below," "beneath," "below," "under," "over," "upper," and the like may be used herein to describe one structure or feature's relationship to another structure or feature as illustrated in the figures. It will be understood that these terms of spatial relationship are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. As used herein, "between 8230%" \8230: "means both end points are included.
In the context of this application, a structure described as a first feature being "on" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features are formed in between the first and second features, such that the first and second features may not be in direct contact.
Please refer to fig. 1 to 10. It should be noted that the drawings provided in the present embodiment are only for schematically illustrating the basic idea of the present invention, and the drawings only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Example one
As shown in fig. 1 to fig. 8, this embodiment provides a method for polysilicon dry etching, where the method for polysilicon dry etching includes the following steps:
s1: providing a semiconductor substrate 10;
s2: forming a polysilicon layer 20 on the surface of the semiconductor substrate 10;
s3: forming a photoresist layer 30 on the surface of the polysilicon layer 20, and patterning the photoresist layer 30, so that an open region 31 and a stop region 32 are formed on the photoresist layer 30, and the open region 31 penetrates through the photoresist layer 30;
s4: performing N-type element 40 ion implantation on the polysilicon layer 20 below the opening region 31 based on the opening region 31 to realize N-type ion doping on the polysilicon layer 20 below the opening region 31;
s5: the characteristic size of the blocking area 32 is subjected to micro adjustment to obtain the blocking area 32 with a preset characteristic size;
s6: dry etching the polysilicon layer to form a polysilicon via 21 based on the open region 31;
s7: the photoresist layer 30 is removed.
In this embodiment, the N-type element 40 is doped into the polysilicon layer 20, so that the dry etching rate of the polysilicon layer 20 is greatly increased, the dry etching time is greatly reduced, and the influence of physical bombardment on the semiconductor substrate 10 is reduced; in this embodiment, the lateral diffusion of ion implantation is considered in advance, and the step of performing a fine adjustment on the feature size of the stop region 32 is added, so as to meet the requirement of the polysilicon layer 20 on the feature size; the embodiment is simple to operate, low in cost and convenient to popularize.
Referring to fig. 1 to 10, the present embodiment is further described below with reference to the accompanying drawings.
As shown in fig. 1 and 2, as an example, step S1 is first performed to provide a semiconductor substrate 10.
As an example, the semiconductor substrate 10 includes a silicon substrate layer 11 and a gate oxide layer 12, and the polysilicon layer 20 is in direct contact with the gate oxide layer 12.
With the continuous reduction of the size of the CMOS process, the thickness of the gate oxide layer 12 is correspondingly gradually reduced, and because the polysilicon layer 20 is in direct contact with the gate oxide layer 12, the etching of the polysilicon layer 20 is particularly important, and the thickness of the gate oxide layer 12 is too small, and if the process for etching the polysilicon layer 20 is unqualified, the silicon substrate layer 11 is also affected, which has very strict requirements on the polysilicon etching process.
As shown in fig. 1 and 3, as an example, a step S2 is performed to form a polysilicon layer 20 on the surface of the semiconductor substrate 10.
As an example, a method of forming the polysilicon layer 20 is a Low Pressure Chemical Vapor Deposition (LPCVD) method.
Transferring the semiconductor substrate 10 into a low pressure chemical vapor deposition apparatus through which silane is introduced, decomposing the silane to deposit a silicon layer containing amorphous silicon on the surface of the semiconductor substrate 10, and H at a predetermined temperature 2 And annealing in an atmosphere of O to form the polysilicon layer 20. Of course, the method for forming the polysilicon layer 20 includes, but is not limited to, a low pressure chemical vapor deposition method, and other methods may be selected according to the actual situation.
As an example, in step S2, after the polysilicon layer 20 is formed, a step of measuring the thickness of the polysilicon layer 20 in the same batch is further included. After the step S2, the method further includes a step of cleaning the semiconductor substrate 10 and the polysilicon layer 20 on the surface with deionized water, and drying the semiconductor substrate and the polysilicon layer.
The thickness of the control wafer of the same batch of the polysilicon layer 20 is measured to ensure the thickness consistency of the polysilicon layer 20, and to avoid influencing the processing of the subsequent process due to the defect of flatness, for example, when a certain part of the polysilicon layer 20 is higher than the preset thickness and the depth of the polysilicon layer during etching does not reach the gate oxide layer 12, or when a certain part of the polysilicon layer 20 is lower than the preset thickness, the gate oxide layer 12 is directly damaged during etching, which can influence the processing of the subsequent process, thus causing the consequences of low product yield and more damages. If the measured height of the polycrystalline silicon layer 20 is higher than the preset thickness, thinning treatment is required; if the measured height of the polysilicon layer 20 is lower than the preset thickness, the preparation of the polysilicon layer 20 needs to be performed again.
After the polysilicon layer 20 is prepared, deionized water is needed to remove residual dust on the semiconductor substrate 10 and the polysilicon layer 20 on the surface after the polysilicon layer 20 is prepared, and after the semiconductor substrate and the polysilicon layer are washed clean, the semiconductor substrate and the polysilicon layer 20 are dried, wherein the drying temperature can be set according to actual needs without limitation, so that the subsequent process is ensured to be smoothly carried out, and short circuit is avoided.
As shown in fig. 1 and 4, as an example, step S3 is performed to form a photoresist layer 30 on the surface of the polysilicon layer 20, and the photoresist layer 30 is patterned, so that an open region 31 and a stop region 32 are formed in the photoresist layer 30, and the open region 31 penetrates through the photoresist layer 30.
The material of the photoresist layer 30 is one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and PI is preferably used in this embodiment to further reduce the process difficulty and the process cost. The method for forming the photoresist layer 30 includes one of plastic package process, compression molding, transfer molding, liquid seal molding, vacuum lamination molding and spin coating molding, in this embodiment, spin coating molding is preferably adopted, and the specific thickness of the photoresist layer 30 is set according to actual needs, which is not limited herein. After the photoresist layer 30 is formed, the opening region 31 and the blocking region 32 are formed by photolithography and etching processes, and at this time, the characteristic dimension of the blocking region 32 is measured as CD1. The process of forming the opening region 31 and the blocking region 32 may be performed in the lightThe resist layer 30 is directly subjected to dry etching using a gas including all gas types, for example, O 2 、N 2 、AR、CF 4 、N 2 H 2 And the selection of the specific etching gas can be set according to actual needs, and is not limited herein. The dry etching process can reduce the generation of waste water, reduce environmental pollution and is more environment-friendly. The process method for forming the opening region 31 and the blocking region 32 includes, but is not limited to, the above two process methods.
As shown in fig. 1 and fig. 5, as an example, step S4 is performed next, and N-type element ions are implanted into the polysilicon layer 20 below the open region 31 based on the open region 31, so as to implement N-type ion doping into the polysilicon layer 20 below the open region 31.
As an example, in step S4, the N-type element includes phosphorus or arsenic; the energy range of ion implantation is 8 keV-20 keV; dosage range of 2e 15 cm -2 ~ 4e 15 cm-2. Other ion implantation conditions can be selected according to actual needs, and are not limited herein.
As shown in fig. 1 and 6, as an example, step S5 is performed to perform a fine adjustment on the feature size of the blocking region 32, so as to obtain the blocking region 32 with a preset feature size.
As an example, in step S5, a plasma deslagging process is used to fine-tune the feature size of the exclusion zone 32.
In this embodiment, the characteristic dimension of the polysilicon layer 20 is realized by adding a step of performing a fine adjustment on the characteristic dimension of the blocking region 32 in consideration of the lateral diffusion of the ion implantation in advance, where the characteristic dimension of the blocking region 32 refers to the characteristic dimension CD1 of the blocking region 32 in fig. 4 and 5.
After the feature size CD1 of the blocking region 32 is adjusted in a micro manner, a blocking region preset feature size CD2 is obtained, that is, the lateral feature size of the opening region 31 is increased, where CD1 is greater than CD2, at this time, the lateral feature size of the opening region 31 is the preset feature size to be etched by the polysilicon layer 20, where it should be noted that the lateral direction in the lateral feature size of the opening region 31 refers to the length direction of CD1.
As an example, the step S5 further includes a step of measuring the characteristic size of the blocking area 32, and if the characteristic size of the blocking area 32 does not reach the preset characteristic size, the characteristic size of the blocking area 32 needs to be resized again until the preset characteristic size is reached.
As shown in fig. 1 and 7, as an example, step S6 is performed next, and the polysilicon layer 20 is dry-etched to form a polysilicon via 21 based on the open region 31.
The gas used in the dry etching includes a gas containing a halogen element, and the selection of the specific etching gas can be set according to actual needs, which is not limited herein. The dry etching of the polysilicon layer 20 uses a gas with a halogen element, and halogen particles adsorbed on the surface of the polysilicon layer 20 can penetrate through a surface potential barrier, destroy Si-Si bonds below the surface, and form a SiFx etching product to be desorbed. The N-type doped polysilicon layer 20 can generate positive space charges in a depletion region of a semiconductor chip, and the positive space charges attract negatively charged halogen particles to the position below the surface of the polysilicon layer 20 due to the coulomb force, so that the etching rate can be accelerated and improved. In addition, the dry etching process can also reduce the generation of waste water, lighten environmental pollution and is more environment-friendly. At this time, based on the open region 31, the feature size of the polysilicon via 21 formed on the polysilicon layer 20 is the same as the lateral feature size of the open region 31, and the distances CD3 and CD2 between two adjacent polysilicon vias 21 are the same. By doping the polysilicon layer 20 with N-type elements, the dry etching rate of the polysilicon layer 30 is greatly increased, the dry etching time is greatly reduced, and the influence of physical bombardment on the semiconductor substrate 10 is also reduced.
As shown in fig. 1 and 8, step S7 is finally performed to remove the photoresist layer 30.
The method for removing the photoresist layer 30 may be a dry etching process, and the removing method includes, but is not limited to, the above method as long as the removing requirement can be met, and may be specifically set according to actual needs, and is not limited herein.
Fig. 9 is a schematic diagram of a conventional polysilicon etching process by transmission electron microscopy, and it is apparent that the semiconductor substrate 10 is damaged at the bottom of the polysilicon via 21 and stepped. Fig. 10 shows a schematic diagram of the polysilicon dry etching method of the present invention, which is presented by a transmission electron microscope after etching, and it can be clearly seen from the diagram that the problem existing in fig. 9 is significantly improved, and the gate oxide layer 12 and the silicon substrate layer 11 have good appearance and no damage trace.
Example two
The embodiment provides a specific method for dry etching of polycrystalline silicon, which comprises the following steps:
providing a semiconductor substrate 10 which is a silicon substrate layer 11 and a gate oxide layer 12 in sequence, wherein the gate oxide layer 12 is positioned on the upper layer structure of the semiconductor substrate 10.
Forming a polysilicon layer 20 on the surface of the gate oxide layer 12 by a low pressure chemical vapor deposition method, transferring the semiconductor substrate 10 into a low pressure chemical vapor deposition device which is communicated with silane, depositing a silicon layer containing amorphous silicon on the surface of the gate oxide layer 12 at the temperature of 620 ℃, and depositing a silicon layer containing amorphous silicon on the surface of the gate oxide layer H 2 Annealing treatment is performed in an atmosphere of O, and the polysilicon layer 20 of 1000A is formed. After the polysilicon layer 20 is formed, the thickness of the control wafer of the polysilicon layer 20 of the same batch is measured to ensure the uniform thickness of the polysilicon layer 20, and then deionized water is used to clean the semiconductor substrate 10 and the polysilicon layer 20 on the surface, and the deionized water is dried to remove residual dust particles in the chemical vapor deposition equipment, so as to ensure the smooth processing of the subsequent process.
Forming a photoresist layer 30 made of PI on the surface of the silicon wafer layer 20 through a spin-on molding process, and then forming the opening region 31 and the blocking region 32 through photolithography and etching processes, wherein the characteristic dimension of the blocking region 32 is CD1 at this time through measurement.
Implanting phosphorus ions in the open region 31 by using energyIn an amount of 20 keV; dosage of 3e 15 cm -2 So that the silicon layer 20 under the open region 31 is doped with phosphorus ions to a depth equal to the thickness of the silicon layer 20.
And then, adopting a plasma deslagging process to transversely shrink the photoresist region 32, wherein the preset characteristic dimension of the blocking region 32 is CD2 at the moment as shown by measurement.
Based on the opening area 31, the polysilicon layer 20 is dry-etched by using an etching gas containing a halogen element to form polysilicon via holes 21, the distance between two adjacent polysilicon via holes 21 is CD3, and the CD3 and the CD2 are the same in size.
And finally, removing the photoresist layer 30 by using dry etching.
EXAMPLE III
The embodiment provides a preparation method of a semiconductor structure, which includes the method for dry etching of polycrystalline silicon described in the first embodiment.
In summary, the present invention provides a method for dry etching of polysilicon and a method for manufacturing a semiconductor structure, wherein the method for dry etching of polysilicon comprises: s1: providing a semiconductor substrate; s2: forming a polycrystalline silicon layer on the surface of the semiconductor substrate; s3: forming a light resistance layer on the surface of the polycrystalline silicon layer, and patterning the light resistance layer to form an opening area and a stopping area on the light resistance layer, wherein the opening area penetrates through the light resistance layer; s4: performing N-type element ion implantation on the polycrystalline silicon layer below the opening region based on the opening region to realize N-type ion doping on the polycrystalline silicon layer below the opening region; s5: carrying out micro adjustment on the characteristic size of the blocking area to obtain the blocking area with a preset characteristic size; s6: on the basis of the opening area, the polycrystalline silicon layer is subjected to dry etching to form a polycrystalline silicon through hole; s7: and removing the photoresist layer. According to the invention, the polycrystalline silicon layer is doped with N-type elements, so that the dry etching rate of the polycrystalline silicon layer is greatly increased, the dry etching time is greatly reduced, and the influence of physical bombardment on a semiconductor substrate is reduced; the invention considers the transverse diffusion of ion implantation in advance, and realizes the requirement of the polycrystalline silicon layer on the characteristic dimension by increasing and carrying out micro adjustment on the characteristic dimension of the stopping area; the invention has simple operation and low cost, and is convenient for popularization. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which may be made by those skilled in the art without departing from the spirit and scope of the present invention as defined in the appended claims.
Claims (11)
1. A method for polysilicon dry etching is characterized by comprising the following steps:
s1: providing a semiconductor substrate;
s2: forming a polycrystalline silicon layer on the surface of the semiconductor substrate;
s3: forming a light resistance layer on the surface of the polycrystalline silicon layer, and patterning the light resistance layer to form an opening area and a stopping area on the light resistance layer, wherein the opening area penetrates through the light resistance layer;
s4: performing N-type element ion implantation on the polycrystalline silicon layer below the opening region based on the opening region to realize N-type ion doping on the polycrystalline silicon layer below the opening region;
s5: carrying out micro adjustment on the characteristic size of the blocking area to obtain the blocking area with a preset characteristic size;
s6: on the basis of the opening area, the polycrystalline silicon layer is subjected to dry etching to form a polycrystalline silicon through hole;
s7: and removing the photoresist layer.
2. The method for polysilicon dry etching according to claim 1, wherein: in the step S1, the semiconductor substrate comprises a silicon substrate layer and a gate oxide layer, and the polycrystalline silicon layer is in direct contact with the gate oxide layer.
3. The method for polysilicon dry etching according to claim 1, wherein: in step S2, the method for forming the polysilicon layer is a low pressure chemical vapor deposition method.
4. The method for polysilicon dry etching according to claim 1, wherein: in step S2, after the polysilicon layer is formed, a step of measuring the thickness of the polysilicon layer in the same batch of control wafers is further included.
5. The method for polysilicon dry etching according to claim 1, wherein: after the step S2, the method further includes the steps of cleaning the semiconductor substrate and the polysilicon layer on the surface thereof with deionized water, and drying.
6. The method for polysilicon dry etching according to claim 1, wherein: in step S4, the N-type element includes phosphorus or arsenic.
7. The method for polysilicon dry etching according to claim 1, wherein: in step S4, the energy range of ion implantation is 8 keV to 20 keV; dosage range of 2e 15 cm -2 ~ 4e 15 cm -2 。
8. The method for polysilicon dry etching according to claim 1, wherein: in step S5, a plasma deslagging process is adopted to carry out micro-adjustment on the characteristic size of the blocking area.
9. The method for polysilicon dry etching according to claim 1, wherein: in step S5, a step of measuring the characteristic size of the blocking area is further included, and if the characteristic size of the blocking area does not reach the preset characteristic size, the characteristic size of the blocking area needs to be resized again until the preset characteristic size is reached.
10. The method for polysilicon dry etching according to claim 1, wherein: in step S6, the gas used for the dry etching includes a gas containing a halogen element.
11. A method for manufacturing a semiconductor structure is characterized in that: the preparation method comprises the method for dry etching the polycrystalline silicon as claimed in any one of claims 1 to 10.
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