CN112652566B - Method for preparing integrated circuit - Google Patents
Method for preparing integrated circuit Download PDFInfo
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- CN112652566B CN112652566B CN202011604276.2A CN202011604276A CN112652566B CN 112652566 B CN112652566 B CN 112652566B CN 202011604276 A CN202011604276 A CN 202011604276A CN 112652566 B CN112652566 B CN 112652566B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/682—Mask-wafer alignment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
Abstract
The invention discloses a preparation method of an integrated circuit, which at least comprises the following steps: providing a machine table; placing a wafer substrate on the machine platform; forming a plurality of chip areas with the same shape and size on a wafer substrate, wherein each chip area is separated by a cutting path area, and each chip area comprises a plurality of chips arranged in an array or/and a plurality of chips arranged in a non-array; arranging a second photomask on the chip, arranging a second graph and a third graph at the edge area of the second photomask, and forming a plurality of second patterns and a plurality of third patterns which are the same and respectively correspond to the second graph and the third graph at the position of a cutting path area between each chip area through the second photomask; and forming an electrode layer on the chip, wherein the electrode layer is aligned through the plurality of second patterns and the plurality of third patterns. The invention solves the problem of resource waste caused by the need of independently manufacturing the electrode alignment layer photomask meeting the requirements of different wafer products.
Description
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to a preparation method of an integrated circuit.
Background
In the manufacturing process of the integrated circuit, effective chips need to be formed on a wafer, and in order to ensure the quality of the chips, the nesting precision needs to be ensured among different films, so that effective patterns need to be formed on alignment films for alignment of the films. In the prior art, an integrated circuit product formed on a wafer can be divided into an array wafer product and a multi-project wafer product, the array wafer product is the same in each chip and is arranged in an array manner, the multi-project wafer product is different in each chip type, size and shape and is in a non-array form in arrangement, an electrode alignment layer is used for independently forming alignment marks in the manufacturing process of the different wafer products, the electrode alignment layer is only used for forming the alignment marks for alignment, and all the alignment marks are randomly arranged in a cutting channel area, so that a product using the electrode alignment layer is required to manufacture an electrode alignment layer photomask meeting requirements, and the photomask is high in manufacturing cost and causes waste of cost resources.
Disclosure of Invention
The invention aims to provide a preparation method of an integrated circuit, which solves the problem that cost and resources are wasted because different wafer products need to be manufactured with electrode alignment layer photomasks meeting requirements independently.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the invention provides a preparation method of an integrated circuit, which at least comprises the following steps:
providing a machine table;
placing a wafer substrate on the table top of the machine table;
forming a plurality of chip areas with the same shape and size on the wafer substrate, wherein each chip area is separated by a cutting path area, each chip area comprises a plurality of chips arranged in an array or/and a plurality of chips arranged in a non-array, and the preparation method of the chips comprises the following steps:
providing a first photomask, wherein a plurality of first patterns are arranged at the edge area of the first photomask, and a plurality of first patterns respectively corresponding to the plurality of first patterns are formed at the positions of the wafer substrate corresponding to the cutting path area through the first photomask;
aligning the first reticle with the tool using the plurality of first patterns;
forming a plurality of thin film layers on the wafer substrate;
arranging a second photomask on the multilayer film layer of the chip, arranging a second graph and a third graph at the edge area of the second photomask, and forming a plurality of second patterns and a plurality of third patterns which are identical and respectively correspond to the second graph and the third graph at the position of the cutting path area between each chip area through the second photomask;
forming an electrode layer on the plurality of thin film layers of the chip, the electrode layer being aligned by the plurality of second patterns and the plurality of third patterns.
In one embodiment of the present invention, the plurality of second patterns and the plurality of third patterns do not overlap with each other.
In one embodiment of the present invention, the first pattern, the second pattern and the third pattern have different horizontal heights between the frame region and the middle region.
In one embodiment of the invention, the second pattern and the third pattern are not identical in shape.
In one embodiment of the present invention, the outer frame of the second pattern and the outer frame of the third pattern have different sizes.
In one embodiment of the present invention, the second pattern and the third pattern are spaced apart along an outer frame of the chip region.
In an embodiment of the present invention, an area enclosed by the second pattern is larger than an area enclosed by the third pattern.
In one embodiment of the present invention, the second pattern and the third pattern are spaced apart by a distance greater than 10 μm.
In one embodiment of the present invention, the second mask is the same as the first mask.
In an embodiment of the present invention, the first photomask is further provided with a second pattern and a third pattern.
The invention fixes the same electrode contraposition layer light shield in the chip areas with the same size of different wafer products, and forms the same contraposition pattern in the cutting path area of the chip area, so that various wafer products with the same chip area size can share the light shield, thereby improving the repeated utilization rate of the light shield, effectively reducing the manufacturing times of the light shield, and the scheme can popularize the design of all related products of integrated circuits and achieve the aim of reducing the cost.
Of course, it is not necessary for any product to practice the invention to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the description below are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a flow chart of a method for fabricating an integrated circuit according to the present invention;
FIG. 2 is a schematic top view of the step S31 according to an embodiment of the present invention;
FIG. 3 is a schematic top view illustrating another embodiment of the present invention corresponding to step S31;
FIG. 4 is a schematic top view illustrating another embodiment of the present invention corresponding to step S31;
FIG. 5 is a schematic top view of the step S4 according to an embodiment of the present invention;
FIG. 6 is a schematic top view illustrating another embodiment of the present invention corresponding to step S4;
FIG. 7 is a schematic view of a preparation method corresponding to step S31;
FIG. 8 is a schematic view of a preparation method corresponding to step S4;
fig. 9 is a schematic view of a preparation method corresponding to step S5.
Reference numerals
The structure comprises a machine table 1, a wafer substrate 2, a first photomask 31, a second photomask 32, a first pattern 41, a second pattern 42, a third pattern 43, a dicing channel region 6, a multilayer thin film layer 7, a first electrode layer 8, a second electrode layer 9, a chip region 10, a chip 101 and a photoresist layer 12.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 2 to 6, the wafer product includes an array wafer product and a multi-project wafer product, the chips 101 in the chip areas 10 on the array wafer product are the same and arranged in regular array, the multi-project wafer product is that each chip 101 has a different model, the chips 101 in the chip areas 10 are arranged according to actual conditions and present a non-array arrangement form, the electrode alignment layers are used to form alignment marks separately in the manufacturing process of these different wafer products, the electrode alignment layers are only used to form the alignment marks for alignment, and all the alignment marks are randomly placed in the scribe line areas 6, even if the chip areas 10 have the same size, the electrode alignment layer masks are required to be manufactured for the products using the electrode alignment layers because the positions of the alignment marks formed by the electrode alignment layer masks in the chip areas 10 of different types of products are different, and the electrode alignment layer masks can not be shared, and the cost is wasted due to the high manufacturing cost of the masks.
Referring to fig. 1, the present invention provides a method for manufacturing an integrated circuit, which at least includes the following steps:
s1, providing a machine table 1;
s2, placing a wafer substrate 2 on the table top of the machine table 1;
s3, forming a plurality of chip areas 10 with the same shape and size on the wafer substrate 2, wherein each chip area 10 is separated by a cutting street area 6, each chip area 10 comprises a plurality of chips 101 arranged in an array or/and a plurality of chips 101 arranged in a non-array, and the preparation method of the chips 101 comprises the following steps:
s31, providing a first photomask 31, wherein a plurality of first patterns are arranged at the edge area of the first photomask 31, and a plurality of first patterns 41 respectively corresponding to the plurality of first patterns are formed at the positions, corresponding to the scribe line areas 6, of the wafer substrate 2 through the first photomask 31;
s32, aligning the first photomask 31 with the machine table 1 by using the plurality of first patterns 41;
s33, forming a plurality of thin film layers 7 on the wafer substrate 2;
s4, arranging a second photomask 32 on the multilayer thin film layer 7 of the chip 101, arranging a second graph and a third graph at the edge area of the second photomask 32, and forming a plurality of second patterns 42 and a plurality of third patterns 43 which are identical and respectively correspond to the second graph and the third graph at the position of the cutting street area 6 between each chip area 10 through the second photomask 32;
s5, forming an electrode layer on the multiple thin film layers 7 of the chip 101, the electrode layer being aligned by the plurality of second patterns 42 and the plurality of third patterns 43.
Referring to fig. 1, in step S1, a machine table 1 is provided, where the machine table 1 is a lithography machine, the lithography machine may be an optical lithography machine or a non-optical lithography machine, and more specifically, the selected lithography machine may be a contact lithography machine, a proximity lithography machine, a projection lithography machine, a scanning projection lithography machine, a step-and-scan projection lithography machine, or an electron beam lithography machine, an X-ray lithography machine, and an ion beam lithography machine, which is not specifically limited in this application.
Referring to fig. 1, in step S2, a wafer substrate 2 is placed on the table top of the machine 1, the material of the wafer substrate 2 may include, but is not limited to, single crystal or polycrystalline semiconductor material, and the wafer substrate 2 may also include an intrinsic single crystal silicon wafer substrate 2 or a doped silicon wafer substrate 2. The wafer substrate 2 includes a wafer substrate 2 of a first doping type, where the first doping type may be a P-type or an N-type, and in this embodiment, the first doping type is only a P-type, that is, in this embodiment, the wafer substrate 2 only uses the P-type wafer substrate 2 as an example, and is, for example, a P-type silicon wafer substrate 2. In some embodiments, the wafer substrate 2 may also be a single crystal silicon wafer substrate 2, a ge wafer substrate 2, a sige wafer substrate 2, a Silicon On Insulator (SOI), or any combination thereof, and an appropriate semiconductor material may be selected as the wafer substrate 2 according to the actual requirements of the device, which is not limited herein. In some embodiments, the wafer substrate 2 may also be composed of a compound semiconductor material, such as a group III-V semiconductor material or a group II-VI semiconductor material.
Referring to fig. 2 to 6, in step S3, a plurality of chip regions 10 with the same shape and size are formed on the wafer substrate 2, each chip region 10 is separated by a scribe line region 6, and each chip region 10 includes a plurality of chips 101 arranged in an array or/and a plurality of chips 101 arranged in a non-array. The plurality of chips 101 in the chip region 10 arranged in an array are, for example, arranged in a horizontal array or in a vertical array, or divided into a plurality of regions, and the chips 101 are arranged in an array in each region. The plurality of chips 101 in the non-array chip region 10 include, for example, a plurality of size-specified chips 101 arranged as needed. The preparation method of the chip 101 comprises the following steps: in steps S31 to S33, a first mask 31 is provided, a plurality of first patterns are disposed at an edge region of the first mask 31, in some embodiments, a plurality of second patterns and/or a plurality of third patterns may be further disposed at the edge region of the first mask 31, and outer frames of the first patterns, the second patterns and the third patterns may be in the same shape or different shapes, for example, some are circular, some are square, some are large in size, and some are small in size. In other embodiments, areas surrounded by outer frames of the first, second, and third patterns may be different, transmittances of the first, second, and third patterns may be different, and transmittances of respective areas of the first, second, and third patterns may also be different, for example, transmittances at frames of the first, second, and third patterns are worse than a transmittance at a middle area, or transmittances at frames of the first, second, and third patterns are better than a transmittance at a middle area, so that an alignment pattern having a convex middle area or a concave middle area may be correspondingly formed in the scribe line area 6 of the wafer substrate 2 by using the photomask, thereby achieving a better alignment purpose, for example, the middle area is 100% transparent, and the frame area is 50% transparent, so that the frame of the pattern has a convex shape, which is convenient to identify when observed. In some embodiments, a plurality of first patterns 41 respectively corresponding to the first pattern are formed at the position of the corresponding scribe line region 6 of the wafer substrate 2 by the first mask 31, and in some embodiments, a plurality of first patterns 41, a plurality of second patterns 42 and/or a plurality of third patterns 43 respectively corresponding to the first pattern, the second pattern and the third pattern may be formed at the position of the corresponding scribe line region 6 of the wafer substrate 2 by the first mask 31, where the plurality of first patterns 41, the plurality of second patterns 42 and the plurality of third patterns 43 do not overlap with each other, and the shapes and sizes of the three patterns may be different, in this embodiment, the second patterns 42 and the third patterns 43 may be different in shape, the second patterns 42 and the third patterns 43 may be the same in shape, but the outer peripheral lengths of the second patterns 42 and the third patterns 43 are different, that is, the area surrounded by the second patterns 42 and the third patterns 43 is not the same, that is, the area of the second patterns 42 and the third patterns 43 is not the same, that is the area of the second patterns 42 and the third patterns 43 is larger than the area of the second patterns 42, and the third patterns 43 is not easy to be larger than the area of the second patterns 42, and the third patterns 42, and the area of the third patterns 43 is not larger than the area of the second patterns 10, and the area of the third patterns in the second patterns 42 is not easy to be larger than the area of the second patterns. A plurality of the second patterns 42 and a plurality of the third patterns 43 are symmetrically disposed between the opposite sides of the outer frame of the chip region 10, respectively. The position of the first pattern 41 may be arranged as desired, with the second pattern 42 and the third pattern 43 being secured in position within the dicing lane.
Referring to fig. 7, in the present embodiment, the first mask 31 is manufactured by a method of providing a substrate of the first mask 31, wherein the substrate may be quartz glass or soda glass with good light transmittance. Chromium-containing materials are selected as the light-shielding material layer, the chromium can be plated to have uniform thickness, fine circuits can be processed in the etching process, the high-resolution target is realized, and the chromium is a non-toxic and pollution-free element, so that the manufacturing process meets the environment-friendly standard. And then coating photoresist on the chromium thin film layer for exposure, removing the redundant photoresist, performing an etching process on the chromium thin film layer, reserving a plurality of first patterns, a plurality of second patterns and a plurality of third patterns, and removing the photoresist to obtain the first photomask 31. And performing pattern transfer on the plurality of first patterns, the plurality of second patterns and the plurality of third patterns on the first photomask 31 to form a first pattern 41, a second pattern 42 and a third pattern 43 corresponding to the first pattern, the second pattern and the third pattern on the wafer substrate 2, and aligning the first photomask 31 with the machine table 1 by using the plurality of first patterns 41. Specifically, a photoresist layer 12 is coated on the wafer substrate 2, the photoresist layer 12 may be a positive photoresist or a negative photoresist, and the first photomask 31 is disposed on the photoresist layer 12, where the first photomask 31 may include a plurality of first patterns, a plurality of second patterns, and a plurality of third patterns. When the wafer substrate 2 coated with the photoresist layer 12 is exposed, the characteristics of the photoresist layer 12 change after being exposed to light, and the light-sensitive portion of the positive photoresist becomes easily dissolved, whereas the negative photoresist is reversed. And then developing the wafer substrate 2, wherein the positive photoresist is dissolved after developing, only the part which is not irradiated with light is left to form a first alignment layer, the first alignment layer can comprise a first pattern 41, a second pattern 42 and a third pattern 43 which correspond to the first pattern, the second pattern and the third pattern, if the negative photoresist is adopted, the part which is irradiated with light becomes difficult to dissolve, and the part which is irradiated with light is left to form the first alignment layer after developing, and the first alignment layer comprises the first pattern 41, the second pattern 42 and the third pattern 43 which correspond to the first pattern, the second pattern and the third pattern. Then, the wafer substrate 2 is etched, a first pattern 41, a second pattern 42 and a third pattern 43 are formed in the corresponding scribe line region 6 on the wafer substrate 2, and finally, the remaining photoresist is removed. When forming a plurality of patterns in the scribe line region 6, other patterns than the first patterns 41 may be planarized and removed without affecting the subsequent process, and the first mask 31 is aligned with the machine 1 by using the first patterns 41. In this embodiment, each of the scribe line regions 6 on the corresponding side of the chip region 10 of the wafer substrate 2 at least includes a first pattern 41, a second pattern 42 and a third pattern 43, and a distance between adjacent patterns is, for example, 10 to 70 μm. The pattern comprises a plurality of groups of strip marks which are arranged in parallel along a first direction and a second direction, and the first direction is vertical to the second direction.
Referring to fig. 8, in step S34, a plurality of thin film layers 7 are formed on the wafer substrate 2, specifically, the plurality of thin film layers 7 may be a plurality of layers of different materials and different thicknesses, which may include a conductive layer or an insulating layer, grown on the surface of the wafer substrate 2. The process for manufacturing the multi-layered thin film layer 7 may include, but is not limited to, an oxidation process, a deposition process, a photolithography process, an etching process, a diffusion process, an ion implantation process, and the like. Specifically, for example, thin films of various materials required for the integrated circuit may be grown on the wafer substrate 2 through an oxidation process and/or a deposition process, or a set of semiconductors, conductors, and isolation materials on various layers that constitute the integrated circuit may be obtained on the wafer substrate 2 through a photolithography process and an etching process, these structures are patterned on each photomask, and then the patterns are transferred onto the wafer substrate 2 through a pattern conversion process. In the process of manufacturing the multilayer thin film layer 7, various impurities can be doped to specific positions of the wafer substrate 2 according to design requirements to form a source/drain terminal and the like. In the present embodiment, the single processes are not limited to be used alone, repeatedly, and in combination.
Referring to fig. 5 and 6 together, in step S4, a second mask 32 is disposed on the multi-layer thin film layer 7 of the chip 101, an edge area of the second mask 32 includes a second pattern and a third pattern, a plurality of second patterns 42 and a plurality of third patterns 43, which are the same and respectively correspond to the second pattern and the third pattern, are formed at positions of the scribe line area 6 between each chip area 10 by the second mask 32, and the second mask 32 may be the same as the first mask 31 or different from the first mask 31, and in some embodiments, when the second mask 32 is the same as the first mask 31, the second mask 32 may be common to the first mask 31, thereby further reducing the number of masks to be manufactured. The plurality of second patterns 42 and the plurality of third patterns 43 do not overlap with each other. In this embodiment, the second pattern 42 and the third pattern 43 may have different shapes, and the second pattern 42 and the third pattern 43 may have the same shape, but have different frame sizes, for example, the second pattern 42 and the third pattern 43 are both square, but the square outer peripheries of the second pattern 42 and the third pattern 43 are different, that is, the areas surrounded by the second pattern 42 and the third pattern 43 are different, in this embodiment, for example, the area of the second pattern 42 is larger than the area of the third pattern 43, the second pattern 42 and the third pattern 43 are spaced apart along the outer frame of the chip region 10, that is, the second pattern 42 and the third pattern 43 are spaced apart in the scribe line, and the spacing distance between the second pattern 42 and the third pattern 43 is larger than 10 μm, so as to avoid the problem of difficult alignment in the later period due to too close. A plurality of the second patterns 42 and a plurality of the third patterns 43 are symmetrically disposed between the opposite sides of the outer frame of the chip region 10, respectively.
Referring to fig. 8, the second mask 32 is disposed on the multi-layer thin film layer 7, and a plurality of second patterns 42 and a plurality of third patterns 43 are formed in the scribe line region 6 of the wafer substrate 2 through the second mask 32, in some embodiments, the first mask 31 used in step S3 may be similarly disposed on the multi-layer thin film layer 7 as the second mask 32 without fabricating a new mask, specifically, a photoresist layer 12 is coated on the multi-layer thin film layer 7, the photoresist layer 12 may be a positive photoresist or a negative photoresist, and then the second mask 32 is disposed on the photoresist layer 12, where the second mask 32 includes a plurality of second patterns and a plurality of third patterns. Upon exposure of the photoresist layer 12, the photoresist changes its properties after being exposed to light, the light-sensitive portion of the positive photoresist becomes readily soluble, and the negative photoresist is reversed. And then developing, dissolving the positive photoresist after developing, only leaving the part which is not irradiated by light to form patterns corresponding to the plurality of second patterns and the plurality of third patterns, namely obtaining the electrode alignment layer, if adopting the negative photoresist, the part which is irradiated by light can be not easily dissolved, and leaving the part which is irradiated by light to form the patterns corresponding to the plurality of second patterns and the plurality of third patterns after developing. And then etching downwards along the vertical direction until reaching the wafer substrate 2, forming a plurality of second patterns 42 and a plurality of third patterns 43 on the wafer substrate 2 corresponding to the scribe line region 6, finally removing the residual photoresist, and removing other patterns except the plurality of second patterns 42 and the plurality of third patterns 43 by planarization.
Referring to fig. 9, in step S5, an electrode layer is formed on the plurality of thin film layers 7 of the chip 101, and the electrode layer is aligned by the plurality of second patterns 42 and the plurality of third patterns 43. Specifically, the first electrode layer 8 may be formed by a deposition process, and the first electrode layer 8 may include, for example, a conductive metal such as copper or aluminum. A plurality of first reference alignment mark patterns are arranged at the edge of the first electrode layer 8 corresponding to the scribe lines, and the first reference alignment mark patterns are aligned with the plurality of second patterns 42 and the plurality of third patterns 43 formed on the wafer substrate 2 in step S4, so as to align the first electrode layer 8, wherein the plurality of second patterns 42 and the plurality of third patterns 43 are outside the chip region 10, so that the chip 101 is not affected. In some embodiments, a second electrode layer 9 may be further formed on the first electrode layer 8, specifically, the second electrode layer 9 may be formed by a deposition process, and the second electrode layer 9 may include, for example, a conductive metal such as copper, aluminum, and the like. A plurality of second reference alignment mark patterns are disposed at the edge of the second electrode layer 9 corresponding to the scribe lines, and the second reference alignment mark patterns are aligned with the plurality of second patterns 42 and the plurality of third patterns 43 formed on the wafer substrate 2 in step S4, so as to align the second electrode layer 9, where the plurality of second patterns 42 and the plurality of third patterns 43 are outside the chip region 10, and thus do not affect the chip 101.
Referring to fig. 1 to 9, the same electrode alignment layer mask, such as the second mask 32, is fixed in the chip areas 10 of different wafer products with the same size, and the same alignment pattern is formed in the scribe line area 6 of the chip area 10, so that each type of wafer product with the same chip area size can share the mask, thereby increasing the reuse rate of the mask, effectively reducing the mask manufacturing frequency.
In the description herein, references to the description of "one embodiment," "an example," "a specific example," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above disclosure of selected embodiments of the invention is intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand the invention for and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.
Claims (8)
1. A method of fabricating an integrated circuit, comprising the steps of:
providing a machine table;
placing a wafer substrate on the table top of the machine table;
forming a plurality of chip areas with the same shape and size on the wafer substrate, wherein each chip area is separated by a cutting track area, each chip area comprises a plurality of chips arranged in an array or/and a plurality of chips arranged in a non-array, and the preparation method of the chips comprises the following steps:
providing a first photomask, wherein a plurality of first patterns are arranged at the edge area of the first photomask, and a plurality of first patterns respectively corresponding to the plurality of first patterns are formed at the positions of the wafer substrate corresponding to the cutting path area through the first photomask;
aligning the first reticle with the tool using the plurality of first patterns;
forming a plurality of thin film layers on the wafer substrate;
arranging a second photomask on the multilayer film layer of the chip, arranging a second graph and a third graph at the edge area of the second photomask, and forming a plurality of second patterns and a plurality of third patterns which are identical and respectively correspond to the second graph and the third graph at the position of the cutting path area between each chip area through the second photomask;
forming an electrode layer on the plurality of thin film layers of the chip, the electrode layer being aligned by the plurality of second patterns and the plurality of third patterns;
wherein the plurality of first patterns, the plurality of second patterns, and the plurality of third patterns are not overlapped with each other;
the second pattern is spaced apart from the third pattern by a distance greater than 10 μm.
2. The method as claimed in claim 1, wherein the first pattern, the second pattern and the third pattern have different frame areas and middle areas.
3. The method as claimed in claim 1, wherein the second pattern and the third pattern are different in shape.
4. The method as claimed in claim 1, wherein the outer frame of the second pattern is different from the outer frame of the third pattern.
5. The method of claim 1, wherein the second pattern and the third pattern are spaced apart along the outer frame of the chip region.
6. The method of claim 1, wherein an area enclosed by the second pattern is larger than an area enclosed by the third pattern.
7. The method of claim 1, wherein the second mask is the same as the first mask.
8. The method as claimed in claim 1, wherein the first mask further has the second pattern and the third pattern.
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| CN114548015B (en) * | 2022-04-21 | 2022-08-02 | 成都复锦功率半导体技术发展有限公司 | Semiconductor laser cutting MPW layout design method and chip and terminal prepared by method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1162507A2 (en) * | 2000-06-08 | 2001-12-12 | Kabushiki Kaisha Toshiba | Alignment method, overlay deviation inspection method and photomask |
| CN103091974A (en) * | 2013-02-27 | 2013-05-08 | 上海华力微电子有限公司 | Photolithography mask structure |
| CN106569386A (en) * | 2015-10-08 | 2017-04-19 | 无锡华润上华科技有限公司 | A photomask and a method of performing simultaneous preparation of a plurality of chips by utilizing the photomask |
| CN107037692A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Mask assembly and alignment method for measurement |
| CN211628000U (en) * | 2020-03-23 | 2020-10-02 | 合肥晶合集成电路有限公司 | Light shield |
| CN112071824A (en) * | 2020-09-18 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Grating device mask and manufacturing method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI305683B (en) * | 2006-08-10 | 2009-01-21 | Bridgelux Inc | Light-emitting diode device and method for fabricating the same |
| US11022877B2 (en) * | 2017-03-13 | 2021-06-01 | Applied Materials, Inc. | Etch processing system having reflective endpoint detection |
-
2020
- 2020-12-30 CN CN202011604276.2A patent/CN112652566B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1162507A2 (en) * | 2000-06-08 | 2001-12-12 | Kabushiki Kaisha Toshiba | Alignment method, overlay deviation inspection method and photomask |
| CN103091974A (en) * | 2013-02-27 | 2013-05-08 | 上海华力微电子有限公司 | Photolithography mask structure |
| CN106569386A (en) * | 2015-10-08 | 2017-04-19 | 无锡华润上华科技有限公司 | A photomask and a method of performing simultaneous preparation of a plurality of chips by utilizing the photomask |
| CN107037692A (en) * | 2016-02-03 | 2017-08-11 | 中芯国际集成电路制造(上海)有限公司 | Mask assembly and alignment method for measurement |
| CN211628000U (en) * | 2020-03-23 | 2020-10-02 | 合肥晶合集成电路有限公司 | Light shield |
| CN112071824A (en) * | 2020-09-18 | 2020-12-11 | 上海华虹宏力半导体制造有限公司 | Grating device mask and manufacturing method |
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