CN113436670A - Memory detection method and memory detection system - Google Patents
Memory detection method and memory detection system Download PDFInfo
- Publication number
- CN113436670A CN113436670A CN202010207558.2A CN202010207558A CN113436670A CN 113436670 A CN113436670 A CN 113436670A CN 202010207558 A CN202010207558 A CN 202010207558A CN 113436670 A CN113436670 A CN 113436670A
- Authority
- CN
- China
- Prior art keywords
- memory chip
- data
- retention time
- qualified
- data retention
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 21
- 230000014759 maintenance of location Effects 0.000 claims abstract description 111
- 238000012360 testing method Methods 0.000 claims abstract description 94
- 238000007619 statistical method Methods 0.000 claims abstract description 25
- 238000012423 maintenance Methods 0.000 claims abstract description 9
- 238000010998 test method Methods 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 4
- 238000012795 verification Methods 0.000 claims 1
- 238000004458 analytical method Methods 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
- 238000007689 inspection Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/56—External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor
- G11C29/56008—Error analysis, representation of errors
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
A memory detection method and a memory detection system are provided. The memory detection system comprises a test machine and a computer system. The memory detection method comprises the following steps: performing a first data retention time test on the memory chip to obtain a first qualified memory chip; performing a second data retention time test on the first qualified memory chip to obtain a second qualified memory chip; and carrying out a third data holding time test on the second qualified memory chip to obtain a third qualified memory chip. And performing a statistical analysis step on the third qualified memory chips according to the first data maintenance time, the second data maintenance time and the third data maintenance time of each third qualified memory chip to obtain the final qualified memory chip. Thus, a memory chip having a Variable Retention Time (VRT) problem can be efficiently detected.
Description
Technical Field
The invention relates to a memory detection method and a memory detection system. In particular, to a memory detection method and a memory detection system suitable for a Variable Retention Time (VRT) problem.
Background
Dynamic Random Access Memory (DRAM) stores charge (data) in a capacitor through a transistor. Over time, the data stored in the capacitor may disappear. The dram chip has a Variable Retention Time (VRT) problem. Conventionally, the problem of variable retention time of a dram chip is detected by writing data to the dram chip and performing a test for data loss a plurality of times after a period of time has elapsed.
However, even if the DRAM chip is determined as a normal chip in the first test cycle, it may be determined as a chip having a VRT problem due to data loss in the second test cycle. Therefore, it is difficult to efficiently detect a chip having a VRT problem.
Disclosure of Invention
Embodiments of the present invention provide a memory test method and a memory test system, which can efficiently detect a memory chip having a VRT problem.
According to an embodiment of the invention, in the memory test method, a first data retention time test is first performed on the memory chip to obtain a first qualified memory chip. Then, a second data holding time test is carried out on the first qualified memory chip to obtain a second qualified memory chip. Then, a third data holding time test is performed on the second qualified memory chips to obtain third qualified memory chips, wherein each third qualified memory chip has a first data holding time, a second data holding time and a third data holding time, the first data holding time is obtained from the first data holding time test, the second data holding time is obtained from the second data holding time test, and the third data holding time is obtained from the third data holding time test. Then, a statistical analysis step is performed on each third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of the third qualified memory chip to obtain at least one final qualified memory chip.
In some embodiments, in the aforementioned step of statistical analysis, a data retention time difference of each third qualified memory chip is first calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, it is determined whether an absolute value of the data holding time difference value of one of the third qualified memory chips is greater than a preset threshold. And then, if the absolute value of the data maintaining time difference is larger than a preset threshold, judging that the third qualified memory chip is unqualified. And if the absolute value of the data maintaining time difference is less than or equal to the preset threshold, judging the third qualified memory chip as a final qualified memory chip.
In some embodiments, in the aforementioned step of statistical analysis, a data retention time difference of each third qualified memory chip is first calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, the root mean square value of each third qualified memory chip is calculated according to the data retention time difference value of each third qualified memory chip. Then, whether the root mean square value of one of the third qualified memory chips is larger than a preset threshold value is judged. And then, if the root mean square value is larger than a preset threshold value, judging that the third qualified memory chip is unqualified. And if the root mean square value is less than or equal to a preset threshold value, determining that the third qualified memory chip is the at least final qualified memory chip.
In some embodiments, in the aforementioned step of statistical analysis, a root mean square value of each third qualified memory chip is first calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, it is determined whether the root mean square value of one of the third qualified memory chips is greater than a preset threshold. And then, if the root mean square value is larger than the preset threshold value, judging that the third qualified memory chip is unqualified. And if the root mean square value is less than or equal to the preset threshold value, judging that the third qualified memory chip is finally qualified.
In some embodiments, in the aforementioned step of statistical analysis, the average value of the data holding time of each third qualified memory chip is first calculated according to the first data holding time, the second data holding time and the third data holding time of each third qualified memory chip. Then, the root mean square value of each third qualified memory chip is calculated according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip. Then, the ratio of the mean value of the data retention time of each third qualified memory chip to the root mean square value is calculated. Then, whether the ratio of one of the third qualified memory chips is larger than a preset threshold is judged. Then, if the ratio is larger than the preset threshold, the third qualified memory chip is determined to be unqualified. And if the ratio is less than or equal to the preset threshold, judging the third qualified memory chip as the final qualified memory chip.
In some embodiments, the first time interval between the first data hold time test and the second data hold time test is greater than or equal to 6 hours, and the second time interval between the second data hold time test and the third data hold time test is greater than or equal to 6 hours.
According to an embodiment of the present invention, the memory test system includes a test machine and a computer system. The testing machine is used for: a first data retention time test is performed on the memory chip to obtain a first qualified memory chip. Then, a second data holding time test is carried out on the first qualified memory chip to obtain a second qualified memory chip. Then, a third data holding time test is performed on the second qualified memory chips to obtain third qualified memory chips, wherein each third qualified memory chip has a first data holding time, a second data holding time and a third data holding time, the first data holding time is obtained from the first data holding time test, the second data holding time is obtained from the second data holding time test, and the third data holding time is obtained from the third data holding time test. The computer system is used for performing a statistical analysis step on each third qualified memory chip according to the first data maintenance time, the second data maintenance time and the third data maintenance time of the third qualified memory chip to obtain at least one final qualified memory chip.
In some embodiments, in the aforementioned step of statistical analysis, a data retention time difference of each third qualified memory chip is first calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, it is determined whether an absolute value of the data holding time difference value of one of the third qualified memory chips is greater than a preset threshold. And then, if the absolute value of the data maintaining time difference is larger than a preset threshold, judging that the third qualified memory chip is unqualified. And if the absolute value of the data maintaining time difference is less than or equal to the preset threshold, judging the third qualified memory chip as a final qualified memory chip.
In some embodiments, in the aforementioned step of statistical analysis, a data retention time difference of each third qualified memory chip is first calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, the root mean square value of each third qualified memory chip is calculated according to the data retention time difference value of each third qualified memory chip. Then, whether the root mean square value of one of the third qualified memory chips is larger than a preset threshold value is judged. And then, if the root mean square value is larger than a preset threshold value, judging that the third qualified memory chip is unqualified. And if the root mean square value is less than or equal to a preset threshold value, determining that the third qualified memory chip is the at least final qualified memory chip.
In some embodiments, in the aforementioned step of statistical analysis, a root mean square value of each third qualified memory chip is first calculated according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Then, it is determined whether the root mean square value of one of the third qualified memory chips is greater than a preset threshold. And then, if the root mean square value is larger than the preset threshold value, judging that the third qualified memory chip is unqualified. And if the root mean square value is less than or equal to the preset threshold value, judging that the third qualified memory chip is finally qualified.
In some embodiments, in the aforementioned step of statistical analysis, the average value of the data holding time of each third qualified memory chip is first calculated according to the first data holding time, the second data holding time and the third data holding time of each third qualified memory chip. Then, the root mean square value of each third qualified memory chip is calculated according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip. Then, the ratio of the mean value of the data retention time of each third qualified memory chip to the root mean square value is calculated. Then, whether the ratio of one of the third qualified memory chips is larger than a preset threshold is judged. Then, if the ratio is larger than the preset threshold, the third qualified memory chip is determined to be unqualified. And if the ratio is less than or equal to the preset threshold, judging the third qualified memory chip as the final qualified memory chip.
In some embodiments, the first time interval between the first data hold time test and the second data hold time test is greater than or equal to 6 hours, and the second time interval between the second data hold time test and the third data hold time test is greater than or equal to 6 hours.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 illustrates a memory detection system according to an embodiment of the invention.
FIG. 2 is a flow chart illustrating a memory detection method according to an embodiment of the invention.
FIG. 3 shows a flow chart of the statistical analysis step according to an embodiment of the present invention.
FIG. 4 shows a flow chart of the statistical analysis step according to an embodiment of the present invention.
FIG. 5 shows a flow chart of the statistical analysis step according to an embodiment of the present invention.
FIG. 6 is a flow chart illustrating a memory detection method according to an embodiment of the invention.
Wherein the reference numerals are as follows:
100: memory detection system
110: test machine
112: wafer
114: probe apparatus
120: computer system
200: memory detection method
210-240: step (ii) of
342-344: step (ii) of
344a to 344 c: step (ii) of
442-444: step (ii) of
444a to 444 c: step (ii) of
542-548: step (ii) of
548a-548 c: step (ii) of
600: memory detection method
640: step (ii) of
Detailed Description
Referring to FIG. 1, a memory sensing system 100 according to an embodiment of the invention is shown. The memory test system 100 includes a test machine 110 and a computer system 120. The testing machine 110 is used for testing a plurality of memory chips on the wafer 112 to obtain test data of each memory chip. In an embodiment of the invention, the Memory chips on the wafer 112 are Dynamic Random Access Memory (DRAM) chips. The computer system 120 is electrically connected to the testing machine 110 to obtain the testing data of the memory chip and analyze the testing data.
In the present embodiment, the testing machine 110 includes a probe device 114, which can apply electrical signals to the memory chips of the wafer 112 and obtain the test data of the memory chips. The test data may include, but is not limited to, the location of the memory chip and the data retention time of the memory chip.
Referring to fig. 2, a flow chart of a memory detection method 200 according to an embodiment of the invention is shown. In the memory inspection method 200, step 210 is performed to perform a first data retention time test on the memory chips on the wafer 112 to obtain a plurality of first qualified memory chips. In step 210, the testing machine 110 measures the data retention time of each memory chip, and then determines whether the memory chip passes the test according to a preset data retention time threshold, so as to select a first qualified memory chip from the memory chips. However, the embodiment of the invention is not limited thereto, and other suitable data retention time testing methods can be applied to the step 210.
Then, step 220 is performed to perform a second data retention time test on the first qualified memory chips on the wafer 112 to obtain a plurality of second qualified memory chips. Similarly, in step 220, the testing machine 110 measures the data retention time of each first qualified memory chip. Then, whether the first memory chip passes the test or not is judged according to a preset data maintaining time threshold value, so that a second qualified memory chip is selected from the first qualified memory chip. However, the embodiment of the invention is not limited thereto, and other suitable data retention time testing methods can be applied to the step 220.
Then, step 230 is performed to perform a third data retention time test on the second qualified memory chips on the wafer 112, so as to obtain a plurality of third qualified memory chips. Similarly, in step 230, the testing machine 110 measures the data retention time of each second qualified memory chip. Then, whether the second memory chip passes the test is judged according to a preset data maintaining time threshold value, so that a third qualified memory chip is selected. However, the embodiment of the invention is not limited thereto, and other suitable data retention time testing methods can be applied to step 230.
In an embodiment of the present invention, the time interval between the first data duration test and the second data duration test is at least 6 hours, and the time interval between the second data duration test and the third data duration test is also at least 6 hours. For example, after the first data duration test is finished, the second data duration test is performed after at least 6 hours have elapsed. For another example, the third data duration test is performed after at least 6 hours after the second data duration test is completed. In the embodiment, the time interval between the first data duration test and the second data duration test is 24 hours, and the time interval between the second data duration test and the third data duration test is also 24 hours.
Then, step 240 is performed to perform statistical analysis on the third qualified memory chip by using the computer system 120 to obtain a final qualified memory chip. In the embodiment of the present invention, step 240 is to perform a statistical analysis step on the third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of the third qualified memory chip to obtain at least one finally qualified memory chip therefrom.
Referring to FIG. 3, a flowchart of step 240 according to an embodiment of the invention is shown. In this embodiment, step 240 is to perform a statistical analysis by using the difference of the data maintaining time. As shown in fig. 3, step 342 is performed to calculate a data retention time difference of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. For example, a difference between the first data holding time and the second data holding time is calculated; calculating the difference value of the second data maintaining time and the third data maintaining time; and calculating a difference between the first data holding time and the third data holding time. Thus, step 342 can obtain the three data retention time differences of each third qualified memory chip.
Next, step 344 is performed to determine whether a third qualified memory chip to be analyzed can be a final qualified memory chip. In step 344, first, step 344a is performed to determine whether the absolute value of the data retention time difference of the third qualified memory chip is greater than a predetermined threshold. In the present embodiment, the preset threshold is 30 milliseconds (ms), but the embodiments of the present invention are not limited thereto. If the data retention time difference of the third qualified memory chip is not greater than the predetermined threshold, step 344b is performed to determine that the third qualified memory chip is the final qualified memory chip. If the data retention time difference of the third qualified memory chip is greater than the predetermined threshold, step 344c is performed to determine that the third qualified memory chip is a failed chip.
In the present embodiment, in step 344a, it is determined whether all of the three data retention time differences of the third qualified memory chip to be analyzed are greater than the preset threshold. However, embodiments of the invention are not so limited.
In another embodiment of the present invention, step 344a determines whether one of the three data retention time differences is greater than a predetermined threshold. If the determination result is negative, step 344b is performed to determine that the third qualified memory chip is the final qualified memory chip. If so, step 344c is performed to determine that the third qualified memory chip is a failed chip.
In another embodiment of the present invention, step 344a determines whether two of the three data-holding time difference values are both greater than a predetermined threshold. If the determination result is negative, step 344b is performed to determine that the third qualified memory chip is the final qualified memory chip. If so, step 344c is performed to determine that the third qualified memory chip is a failed chip.
Referring to FIG. 4, a flowchart of step 240 according to an embodiment of the invention is shown. In this embodiment, step 240 is to perform a statistical analysis by using the root mean square value of the data retention time. As shown in FIG. 4, step 442 is performed to calculate a Root Mean Square (RMS) value of each third qualified memory chip according to the first data-holding time, the second data-holding time, and the third data-holding time of each third qualified memory chip. The equation for the root mean square value of the third pass memory chip is as follows:
wherein R is the root mean square value of a third pass memory chip, and D1、D2、D3The time difference is maintained for three data of the third qualified memory chip.
Then, step 444 is performed to determine whether a third qualified memory chip to be analyzed can be a final qualified memory chip. In step 444, first, step 444a is performed to determine whether the root mean square value of the third qualified memory chip is greater than a predetermined threshold. In the present embodiment, the preset threshold is 45, but the embodiments of the present invention are not limited thereto. If the root mean square value of the third qualified memory chip is not greater than the predetermined threshold, step 444b is performed to determine that the third qualified memory chip is the final qualified memory chip. If the root mean square value of the third qualified memory chip is greater than the predetermined threshold, step 444c is performed to determine that the third qualified memory chip is a failed chip.
Referring to FIG. 5, a flowchart of step 240 according to an embodiment of the invention is shown. In this embodiment, step 240 is to perform a statistical analysis by using the AR value of the data retention time, wherein the AR value is the ratio of the average value of the data retention time to the root-mean-square value. As shown in fig. 5, step 542 is performed to calculate an average value of the data retention time of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip. Next, step 544 is performed to calculate a root mean square value of each third pass memory chip according to the first data holding time, the second data holding time, and the third data holding time of each third pass memory chip. Step 544 is similar to step 442 described above and therefore will not be described herein.
Then, step 546 is performed to calculate A Ratio (AR) of the data retention time average to the root mean square value of each third qualified memory chip, wherein the AR value is calculated as follows:
wherein, T1、T2、T3The data holding times of the third qualified memory chip measured in the first, second and third data holding time tests。
Next, step 548 is performed to determine whether a third qualified memory chip to be analyzed can be a final qualified memory chip. In step 548, first, step 548a is performed to determine whether the AR value of the third qualified memory chip is greater than a predetermined threshold. In the present embodiment, the preset threshold is 3, but the embodiments of the present invention are not limited thereto. If the AR value of the third qualified memory chip is not greater than the predetermined threshold, step 548b is performed to determine that the third qualified memory chip is the final qualified memory chip. If the AR value of the third qualified memory chip is greater than the predetermined threshold, step 548c is performed to determine that the third qualified memory chip is a failed chip.
Referring to fig. 6, a flow chart of a memory detection method 600 according to an embodiment of the invention is shown. The memory test method 600 is similar to the memory test method 200, except that the step 640 of the memory test method 600 integrates a plurality of statistical analysis steps to analyze the third qualified memory chip. For example, step 640 may integrate the embodiments of fig. 3 and 4 (e.g., steps 344 and 444) to perform an analysis on a third qualified memory chip. Specifically, if a third qualified memory chip passes the judgment of one of the steps 344 and 444, the third qualified memory chip is determined to be the final qualified memory chip. As another example, step 640 may integrate the embodiments of FIGS. 3, 4, and 5 (e.g., steps 344, 444, and 548) to analyze a third qualified memory chip. Specifically, if a third qualified memory chip passes the determination of one of the steps 344, 444 and 548, the third qualified memory chip is determined to be the final qualified memory chip.
As can be seen from the above description, the memory test system and the memory test method according to the embodiments of the present invention perform statistical analysis on the memory chips that have passed multiple data retention time tests, so that the memory chips having the VRT problem can be efficiently detected. In addition, although the statistical analysis step of the above embodiment uses the data retention time difference, the root mean square, and the AR value for analysis, the embodiment of the present invention is not limited thereto. Other suitable statistical analysis methods may also be applied to embodiments of the present invention.
Although the present invention has been described with reference to the above embodiments, it should be understood that the scope of the present invention is not limited to the above embodiments, and it should be understood that various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the present invention.
Claims (10)
1. A method for memory verification, comprising:
performing a first data retention time test on the plurality of memory chips to obtain a plurality of first qualified memory chips;
performing a second data retention time test on the first qualified memory chip to obtain a plurality of second qualified memory chips;
performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips, wherein each third qualified memory chip has a first data retention time, a second data retention time and a third data retention time, the first data retention time is obtained from the first data retention time test, the second data retention time is obtained from the second data retention time test, and the third data retention time is obtained from the third data retention time test; and
and performing a statistical analysis on the third qualified memory chips according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip to obtain at least one final qualified memory chip.
2. The memory test method of claim 1, wherein the step of statistically analyzing comprises:
calculating a data retention time difference of each third pass memory chip according to the first data retention time, the second data retention time and the third data retention time of each third pass memory chip; and
judging whether the absolute value of the data holding time difference value of one of the third qualified memory chips is larger than a preset threshold value or not;
if the absolute value of the data maintaining time difference is larger than the preset threshold, determining that the third qualified memory chip is unqualified;
and if the absolute value of the data holding time difference is less than or equal to the preset threshold, determining that the third qualified memory chip is the at least one final qualified memory chip.
3. The memory test method of claim 1, wherein the step of statistically analyzing comprises:
calculating a root mean square value of each third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip; and
judging whether the root mean square value of one of the third qualified memory chips is larger than a preset threshold value;
if the root mean square value is larger than the preset threshold value, determining that the third qualified memory chip is unqualified;
and if the root mean square value is less than or equal to the preset threshold value, determining that the third qualified memory chip is the at least one final qualified memory chip.
4. The memory test method of claim 1, wherein the step of statistically analyzing comprises:
calculating a data retention time average value of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip;
calculating a root mean square value of each third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip;
calculating a ratio of the data retention time average value and the root mean square value of each third pass memory chip; and
judging whether the ratio of one of the third qualified memory chips is larger than a preset threshold value;
if the ratio is greater than the preset threshold, determining that the third qualified memory chip is unqualified;
if the ratio is less than or equal to the predetermined threshold, determining that the one of the third qualified memory chips is the at least one finally qualified memory chip.
5. The method as claimed in claim 1, wherein a first time interval between the first data hold time test and the second data hold time test is greater than or equal to 6 hours, and a second time interval between the second data hold time test and the third data hold time test is greater than or equal to 6 hours.
6. A memory detection system, comprising:
a testing machine for:
performing a first data retention time test on the plurality of memory chips to obtain a plurality of first qualified memory chips;
performing a second data retention time test on the first qualified memory chip to obtain a plurality of second qualified memory chips; and
performing a third data retention time test on the second qualified memory chips to obtain a plurality of third qualified memory chips, wherein each of the third qualified memory chips has a first data retention time obtained from the first data retention time test, a second data retention time obtained from the second data retention time test, and a third data retention time obtained from the third data retention time test; and
and the computer system is used for performing a statistical analysis step on the third qualified memory chips according to the first data maintenance time, the second data maintenance time and the third data maintenance time of each third qualified memory chip so as to obtain at least one final qualified memory chip.
7. The memory test system of claim 6, wherein the step of statistically analyzing comprises:
calculating a data retention time difference of each third pass memory chip according to the first data retention time, the second data retention time and the third data retention time of each third pass memory chip; and
judging whether the absolute value of the data holding time difference value of one of the third qualified memory chips is larger than a preset threshold value or not;
if the absolute value of the data maintaining time difference is larger than the preset threshold, determining that the third qualified memory chip is unqualified;
and if the absolute value of the data holding time difference is less than or equal to the preset threshold, determining that the third qualified memory chip is the at least one final qualified memory chip.
8. The memory test system of claim 6, wherein the step of statistically analyzing comprises:
calculating a root mean square value of each third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip; and
judging whether the root mean square value of one of the third qualified memory chips is larger than a preset threshold value;
if the root mean square value is larger than the preset threshold value, determining that the third qualified memory chip is unqualified;
and if the root mean square value is less than or equal to the preset threshold value, determining that the third qualified memory chip is the at least one final qualified memory chip.
9. The memory test system of claim 6, wherein the step of statistically analyzing comprises:
calculating a data retention time average value of each third qualified memory chip according to the first data retention time, the second data retention time and the third data retention time of each third qualified memory chip;
calculating a root mean square value of each third qualified memory chip according to the first data maintaining time, the second data maintaining time and the third data maintaining time of each third qualified memory chip;
calculating a ratio of the data retention time average value and the root mean square value of each third pass memory chip; and
judging whether the ratio of one of the third qualified memory chips is larger than a preset threshold value;
if the ratio is greater than the preset threshold, determining that the third qualified memory chip is unqualified;
if the ratio is less than or equal to the predetermined threshold, determining that the one of the third qualified memory chips is the at least one finally qualified memory chip.
10. The memory sensing system of claim 6, wherein a first time interval between the first data retention time test and the second data retention time test is greater than or equal to 6 hours, and a second time interval between the second data retention time test and the third data retention time test is greater than or equal to 6 hours.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010207558.2A CN113436670B (en) | 2020-03-23 | 2020-03-23 | Memory detection method and memory detection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010207558.2A CN113436670B (en) | 2020-03-23 | 2020-03-23 | Memory detection method and memory detection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113436670A true CN113436670A (en) | 2021-09-24 |
| CN113436670B CN113436670B (en) | 2024-03-26 |
Family
ID=77753250
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010207558.2A Active CN113436670B (en) | 2020-03-23 | 2020-03-23 | Memory detection method and memory detection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113436670B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154468A (en) * | 2006-09-27 | 2008-04-02 | 上海华虹Nec电子有限公司 | Test method for embedded memory chip |
| JP2011165231A (en) * | 2010-02-04 | 2011-08-25 | Renesas Electronics Corp | Method, program, and apparatus for testing semiconductor memory |
| CN102890971A (en) * | 2012-10-22 | 2013-01-23 | 上海宏力半导体制造有限公司 | Reliability test method for memory |
| US20150037914A1 (en) * | 2013-07-31 | 2015-02-05 | Micron Technology, Inc. | Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus |
| CN108831517A (en) * | 2018-05-23 | 2018-11-16 | 武汉忆数存储技术有限公司 | A kind of method and test device judging flash chip reliability based on operating time or electric current |
| CN110010163A (en) * | 2019-04-16 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of data in magnetic disk holding capacity test method and relevant apparatus |
| CN110083519A (en) * | 2019-04-30 | 2019-08-02 | 中国联合网络通信集团有限公司 | Load test approach and system |
-
2020
- 2020-03-23 CN CN202010207558.2A patent/CN113436670B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101154468A (en) * | 2006-09-27 | 2008-04-02 | 上海华虹Nec电子有限公司 | Test method for embedded memory chip |
| JP2011165231A (en) * | 2010-02-04 | 2011-08-25 | Renesas Electronics Corp | Method, program, and apparatus for testing semiconductor memory |
| CN102890971A (en) * | 2012-10-22 | 2013-01-23 | 上海宏力半导体制造有限公司 | Reliability test method for memory |
| US20150037914A1 (en) * | 2013-07-31 | 2015-02-05 | Micron Technology, Inc. | Method for manufacturing tested apparatus and method for manufacturing system including tested apparatus |
| CN108831517A (en) * | 2018-05-23 | 2018-11-16 | 武汉忆数存储技术有限公司 | A kind of method and test device judging flash chip reliability based on operating time or electric current |
| CN110010163A (en) * | 2019-04-16 | 2019-07-12 | 苏州浪潮智能科技有限公司 | A kind of data in magnetic disk holding capacity test method and relevant apparatus |
| CN110083519A (en) * | 2019-04-30 | 2019-08-02 | 中国联合网络通信集团有限公司 | Load test approach and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113436670B (en) | 2024-03-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104238543B (en) | The bad pattern method of inspection and its device of the sensing data of time series form | |
| US20190339056A1 (en) | Monitoring system and method for verifying measurements in pattened structures | |
| US8271113B2 (en) | Audio testing system and method | |
| CN101133340B (en) | Test device, test method, electronic device manufacturing method, test simulator, and test simulation method | |
| US7386420B2 (en) | Data analysis method for integrated circuit process and semiconductor process | |
| US20100114520A1 (en) | Test apparatus, test method, program, and recording medium reducing the influence of variations | |
| US7557598B2 (en) | Method of inspecting quiescent power supply current in semiconductor integrated circuit and device for executing the method | |
| US6872582B2 (en) | Selective trim and wafer testing of integrated circuits | |
| US20060171221A1 (en) | Method for analyzing critical defects in analog integrated circuits | |
| CN108051722A (en) | The lifetime estimation method and system of hot carrier injection effect | |
| CN113436670B (en) | Memory detection method and memory detection system | |
| US7962302B2 (en) | Predicting wafer failure using learned probability | |
| TWI716284B (en) | Memory inspecting method and memory inspecting system | |
| US6553521B1 (en) | Method for efficient analysis semiconductor failures | |
| US7984353B2 (en) | Test apparatus, test vector generate unit, test method, program, and recording medium | |
| US20090206870A1 (en) | Method for analyzing ic devices and wafers | |
| CN102081138A (en) | Method for wafer-level burn-in test of semiconductor devices | |
| JPS59228726A (en) | Malfunction analyzer | |
| US7265568B2 (en) | Semi-conductor component test process and a system for testing semi-conductor components | |
| TWI647658B (en) | Device, system and method for automatically identifying image features | |
| KR100940414B1 (en) | A test method of a wafer for reducing a site difference | |
| JP3934384B2 (en) | Semiconductor device test equipment | |
| TWI731671B (en) | Method and system for detecing abnormal dies | |
| JP3696009B2 (en) | Semiconductor test apparatus, semiconductor test method, and recording medium | |
| CN113625149A (en) | Abnormal chip detection method and abnormal chip detection system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |